Bug 111775

Summary:	[CI][DRMTIP] igt@kms_flip@dpms-vs-vblank-race - fail - Failed assertion: drmModeConnectorSetProperty(fd, connector->connector_id, dpms, mode) == 0
Product:	DRI	Reporter:	Lakshmi <lakshminarayana.vudum>
Component:	DRM/Intel	Assignee:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Status:	RESOLVED DUPLICATE	QA Contact:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity:	not set
Priority:	not set	CC:	intel-gfx-bugs
Version:	DRI git
Hardware:	Other
OS:	All
Whiteboard:
i915 platform:	ICL	i915 features:	display/Other

Description Lakshmi 2019-09-23 11:55:06 UTC

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_373/fi-icl-u4/igt@kms_flip@dpms-vs-vblank-race.html

Starting subtest: dpms-vs-vblank-race
(kms_flip:1362) igt_kms-CRITICAL: Test assertion failure function kmstest_set_connector_dpms, file ../lib/igt_kms.c:1367:
(kms_flip:1362) igt_kms-CRITICAL: Failed assertion: drmModeConnectorSetProperty(fd, connector->connector_id, dpms, mode) == 0
(kms_flip:1362) igt_kms-CRITICAL: Last errno: 22, Invalid argument
Subtest dpms-vs

Comment 1 CI Bug Log 2019-09-23 11:55:48 UTC

The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* ICL: igt@kms_flip@dpms-vs-vblank-race - fail - Failed assertion: drmModeConnectorSetProperty(fd, connector-&gt;connector_id, dpms, mode) == 0
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_373/fi-icl-u4/igt@kms_flip@dpms-vs-vblank-race.html

Comment 2 Matt Roper 2019-09-26 21:05:05 UTC

Another link training failure that results in us not being able to drive the requested mode.  The IGT signature is slightly different this time because the failure happens while using the legacy ConnectorSetProperty() interface to toggle DPMS, rather than the more common modesetting interfaces, but the end result is the same --- the underlying atomic transaction is rejected and EINVAL (22) is propagated up to userspace as the error code.

In this case the modeline being attempted is
"1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

The 148500 clock on this mode * a minimum RGB bpp of 18 means that we require a data rate of 2683000/8 = 334125 to drive this mode.  However the previous link training gave us

<7> [354.746236] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 162000 max bpp 24 pixel clock 148500KHz

Since 334125 > 2*162000, we don't have enough bandwidth to drive the desired mode.

*** This bug has been marked as a duplicate of bug 111185 ***

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