Bug 111975

Summary:	[CI][BAT] [KBL] suspend tests - incomplete - PM: suspend entry (s2idle)
Product:	DRI	Reporter:	Lakshmi <lakshminarayana.vudum>
Component:	DRM/Intel	Assignee:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Status:	RESOLVED MOVED	QA Contact:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity:	not set
Priority:	not set	CC:	intel-gfx-bugs
Version:	DRI git
Hardware:	Other
OS:	All
Whiteboard:
i915 platform:	KBL	i915 features:

Description Lakshmi 2019-10-11 08:12:27 UTC

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

<6> [333.357813] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
<7> [333.358655] [drm:drm_mode_addfb2] [FB:126]
<7> [333.447458] [drm:drm_mode_setcrtc] [CRTC:51:pipe A]
<7> [333.447489] [drm:drm_mode_setcrtc] [CONNECTOR:95:eDP-1]
<7> [333.465385] [drm:drm_mode_setcrtc] [CRTC:72:pipe B]
<7> [333.466680] [drm:drm_mode_setcrtc] [CRTC:93:pipe C]
<7> [333.482061] [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [333.482514] [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [333.482831] [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [333.482952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz
<7> [333.483052] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [333.483152] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24
<7> [333.483251] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000
<7> [333.483353] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [333.483514] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [fastset]
<7> [333.483617] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [333.483718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [333.483820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
<7> [333.483920] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [333.484020] [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [333.484031] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.484128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [333.484138] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.484239] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0xa
<7> [333.484336] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
<7> [333.484467] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [333.484568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [333.484667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [333.484765] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
<7> [333.484860] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [333.484959] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:126] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes
<7> [333.485056] [drm:intel_dump_pipe_config [i915]] 	rotation: 0x1, scaler: -1
<7> [333.485155] [drm:intel_dump_pipe_config [i915]] 	src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0
<7> [333.485377] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<7> [333.497469] [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [333.497608] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A]
<7> [333.497824] [drm:verify_single_dpll_state.isra.153 [i915]] DPLL 0
<7> [333.580850] [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [333.580903] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz
<7> [333.580944] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [333.580985] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24
<7> [333.581024] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000
<7> [333.581066] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [333.581119] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [fastset]
<7> [333.581159] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [333.581200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [333.581240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
<7> [333.581279] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [333.581318] [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [333.581359] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.581401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [333.581406] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.581449] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0xa
<7> [333.581493] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
<7> [333.581535] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [333.581578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [333.581621] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [333.581663] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
<7> [333.581705] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [333.581750] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:126] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes
<7> [333.581790] [drm:intel_dump_pipe_config [i915]] 	rotation: 0x1, scaler: -1
<7> [333.581830] [drm:intel_dump_pipe_config [i915]] 	src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0
<7> [333.581938] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<7> [333.597293] [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [333.597377] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A]
<7> [333.597478] [drm:verify_single_dpll_state.isra.153 [i915]] DPLL 0
<7> [333.597677] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb (   0 -  847) -> (   0 -    0), size  847 ->    0
<7> [333.597709] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm ->  wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm
<7> [333.597741] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   lines    0,   4,   5,   5,   9,  11,  12,  14,   0 ->    0,   0,   0,   0,   0,   0,   0,   0,   0
<7> [333.597773] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]  blocks   26,  98, 136, 152, 281, 340, 365, 432,   0 ->    0,   0,   0,   0,   0,   0,   0,   0,   0
<7> [333.597803] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb   27,  99, 137, 153, 282, 341, 366, 433,   0 ->    0,   0,   0,   0,   0,   0,   0,   0,   0
<7> [333.614043] [drm:drm_mode_addfb2] [FB:125]
<7> [333.637488] [drm:drm_mode_setcrtc] [CRTC:51:pipe A]
<7> [333.637515] [drm:drm_mode_setcrtc] [CONNECTOR:95:eDP-1]
<7> [333.637594] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb (   0 -    0) -> (   0 -  847), size    0 ->  847
<7> [333.637618] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   level  wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm
<7> [333.637641] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   lines    0,   0,   0,   0,   0,   0,   0,   0,   0 ->    0,   4,   5,   5,   9,  11,  12,  14,   0
<7> [333.637663] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]  blocks    0,   0,   0,   0,   0,   0,   0,   0,   0 ->   26,  98, 136, 152, 281, 340, 365, 432,   0
<7> [333.637685] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb    0,   0,   0,   0,   0,   0,   0,   0,   0 ->   27,  99, 137, 153, 282, 341, 366, 433,   0
<7> [333.647452] [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [333.647570] [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [333.647612] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz
<7> [333.647647] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [333.647680] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24
<7> [333.647714] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000
<7> [333.647750] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [333.647791] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [fastset]
<7> [333.647825] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [333.647858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [333.647891] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
<7> [333.647924] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [333.647958] [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [333.647961] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.647994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [333.647996] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.648030] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0xa
<7> [333.648063] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
<7> [333.648095] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [333.648128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [333.648160] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [333.648194] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
<7> [333.648226] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [333.648259] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:125] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes
<7> [333.648292] [drm:intel_dump_pipe_config [i915]] 	rotation: 0x1, scaler: -1
<7> [333.648324] [drm:intel_dump_pipe_config [i915]] 	src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0
<7> [333.648437] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<7> [333.663930] [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [333.663980] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A]
<7> [333.664076] [drm:verify_single_dpll_state.isra.153 [i915]] DPLL 0
<7> [333.747546] [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [333.747608] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz
<7> [333.747658] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [333.747706] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24
<7> [333.747753] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000
<7> [333.747803] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [333.747865] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [fastset]
<7> [333.747913] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [333.747961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [333.748008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
<7> [333.748054] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0
<7> [333.748101] [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [333.748106] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.748152] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [333.748156] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [333.748202] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0xa
<7> [333.748249] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
<7> [333.748295] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [333.748342] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no
<7> [333.748430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [333.748479] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
<7> [333.748529] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [333.748577] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:125] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes
<7> [333.748625] [drm:intel_dump_pipe_config [i915]] 	rotation: 0x1, scaler: -1
<7> [333.748673] [drm:intel_dump_pipe_config [i915]] 	src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0
<7> [333.748808] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<7> [333.764017] [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [333.764103] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A]
<7> [333.764238] [drm:verify_single_dpll_state.isra.153 [i915]] DPLL 0
<7> [333.764573] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb (   0 -  847) -> (   0 -    0), size  847 ->    0
<7> [333.764612] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm ->  wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm
<7> [333.764651] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]   lines    0,   4,   5,   5,   9,  11,  12,  14,   0 ->    0,   0,   0,   0,   0,   0,   0,   0,   0
<7> [333.764689] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A]  blocks   26,  98, 136, 152, 281, 340, 365, 432,   0 ->    0,   0,   0,   0,   0,   0,   0,   0,   0
<7> [333.764726] [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb   27,  99, 137, 153, 282, 341, 366, 433,   0 ->    0,   0,   0,   0,   0,   0,   0,   0,   0
<6> [333.857967] PM: suspend entry (s2idle)
<6> [333.859056] Filesystems sync: 0.001 seconds

Comment 1 CI Bug Log 2019-10-11 08:13:44 UTC

The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* KBL: suspend tests - incomplete - PM: suspend entry (s2idle)
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14634/fi-kbl-r/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_383/fi-kbl-r/igt@kms_flip@flip-vs-suspend-interruptible.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_384/fi-kbl-r/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_385/fi-kbl-x1275/igt@kms_flip@flip-vs-suspend.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/fi-kbl-r/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

Comment 2 CI Bug Log 2019-10-11 09:51:47 UTC

A CI Bug Log filter associated to this bug has been updated:

{- KBL: suspend tests - incomplete - PM: suspend entry (s2idle) -}
{+ KBL: igt@* - incomplete - PM: suspend entry (s2idle) +}

New failures caught by the filter:

  * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_386/fi-kbl-r/igt@gem_ctx_isolation@vecs0-s3.html

Comment 3 Martin Peres 2019-11-29 19:38:57 UTC

-- GitLab Migration Automatic Message --

This bug has been migrated to freedesktop.org's GitLab instance and has been closed from further activity.

You can subscribe and participate further through the new bug through this link to our GitLab instance: https://gitlab.freedesktop.org/drm/intel/issues/494.

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