Summary: | R600: ForceLowPowerMode causes display corruption | ||||||||||
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Product: | xorg | Reporter: | Luca Tettamanti <kronos.it> | ||||||||
Component: | Driver/Radeon | Assignee: | xf86-video-ati maintainers <xorg-driver-ati> | ||||||||
Status: | RESOLVED INVALID | QA Contact: | Xorg Project Team <xorg-team> | ||||||||
Severity: | normal | ||||||||||
Priority: | medium | CC: | irgendwer.rob, kronos.it | ||||||||
Version: | 7.4 (2008.09) | ||||||||||
Hardware: | Other | ||||||||||
OS: | All | ||||||||||
Whiteboard: | |||||||||||
i915 platform: | i915 features: | ||||||||||
Attachments: |
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Description
Luca Tettamanti
2009-04-17 05:22:04 UTC
Created attachment 24890 [details]
sample corruption
Created attachment 24891 [details]
sample corruption
Forgot the mention: the chip is a M76 (Mobility HD2600). More information: lspci reports this: LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- I believe that the link width should be 4, no? Does Option "EXANoDownloadFromScreen" work around the problem? Created attachment 24893 [details] [review] possible fix, only drop to x8 Reducing the number of PCIE lanes seems to negatively impact operations that use the gart (UTS/DFS) in some cases. I'm not sure whether it makes more sense to not reduce the pcie lanes as much (8 or 16), or to disable UTS/DFS when the lanes are below a certain level. (In reply to comment #5) > Created an attachment (id=24893) [details] > possible fix, only drop to x8 I can't try it right now, but I believe that there's something wrong with the reprogramming of the lanes count; please note that lspci *always* report: LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgm- At the end of RADEONSetPCIELanes link_width_cntl is 0x000096 (LC_LINK_WIDTH_RD is 1) - regardless of the width requested (I was trying to force 16x). (In reply to comment #4) > Does > > Option "EXANoDownloadFromScreen" > > work around the problem? Yes, it does. *** Bug 25059 has been marked as a duplicate of this bug. *** The bug was related to reducing the active PCIe lanes regardless of what was present in Atom tables. I believe that this bug is fixed in UMS, and no more relevant for KMS (which leaves the PCIe alone as advertised in the BIOS). Close? |
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