Bug 27030

179d2c0e0bcf96fc40107882ccab909af8c89853 is the first bad commit
commit 179d2c0e0bcf96fc40107882ccab909af8c89853
Author: Eric Anholt <eric@anholt.net>
Date:   Tue Mar 2 15:34:17 2010 -0800

    intel: Use drm_intel_bo_alloc_tiled for region allocs.
    
    This moves the logic for how to align pitches, heights, and sizes of
    objects to one central location.  Fixes rendering with texture tiling
    on i915.  Note that current libdrm is required for the change for
    I915_TILING_NONE pitch alignment.

:100644 100644 d108ecdad2941bfdfe78e295529525b9eb294051 e807d4acaf836e6ba69bf37cd13bd09482c1b125 M	configure.ac
:040000 040000 a31b26d4a43572431bca846f70def01d91c4b333 9abd3d60037ffe5d2f9c2db370d7e6112cf1e522 M	src

looks like bug#26966.

*** Bug 26966 has been marked as a duplicate of this bug. ***

unigine tropics requires EXT_framebuffer_multisample, which we don't have support for.  I downloaded the xreal tarball, and it doesn't have the linux binaries.  So I'm having trouble reproducing this.  No piglit testcase produces this assertion any more with current libdrm.  Could you print out the tiling mode and the two pitch values?

Sure, I hope I got this right:

For XreaL:
 
tiling = 0
pitch = 208
aligned_pitch = 800

For the tropics demo:

tiling=0
pitch= 16
aligned_pitch = 8

(I run Tropics with MESA_EXTENSION_OVERRIDE=+GL_EXT_framebuffer_multisample, which at least gets it running but obviously doesn't render anything onscreen)

I met the same issue in MeeGo with latest Mesa-7.8 on 945. It seemed that the pitch calculation in intel_miptree_pitch_align() and drm_intel_gem_bo_alloc_tiled() are different. For tiled buffer allocation, drm_intel_gem_bo_alloc_tiled() requires the pitch to be power of two tile width for pre-965, but intel_miptree_pitch_align() 
doesn't have this requirement, its pitch is just 512 bytes (I915_TILING_X) or 128 bytes (I915_TILING_Y) aligned.

other than above, intel_region_alloc() is also called by intel_alloc_renderbuffer_storage(), which requires non-tiled buffer allocation and its pitch is 64-bytes aligned, but drm_intel_gem_bo_alloc_tiled() doesn't have this requirement. it just set the pitch value to be width * cpp.

So I made below patch, it make sure that the pitch should be power of two tiles on 915/915 for tiled buffer, which is consistent with pitch calculation in drm_intel_gem_bo_alloc_tiled(). Also it doesn't do assertion check for non-tiled buffer.

Eric, would you please review ?

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 4f14946..f876c05 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -244,8 +244,15 @@ int intel_miptree_pitch_align (struct intel_context *intel,
       if (tiling == I915_TILING_NONE && !(pitch & 511) &&
         (pitch + pitch_align) < (1 << ctx->Const.MaxTextureLevels))
         pitch += pitch_align;
-#endif

+      if (tiling != I915_TILING_NONE) {
+         int i;
+
+         for (i = pitch_align; i < pitch; i <<= 1)
+            ;
+         pitch = i;
+      }
+#endif
       pitch /= mt->cpp;
    }
    return pitch;
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index f042bcb..d6ac6a7 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -190,7 +190,8 @@ intel_region_alloc(struct intel_context *intel,
    /* We've already chosen a pitch as part of miptree layout.  It had
     * better be the same.
     */
-   assert(aligned_pitch == pitch * cpp);
+   if (tiling != I915_TILING_NONE)
+      assert(aligned_pitch == pitch * cpp);

    region = intel_region_alloc_internal(intel, cpp, width, height,
                                        pitch, buffer);

This bug also crashes gnome-shell

Sven, looks like you have texture tiling turned off?  Those pitch alignments look like they're to 64b, which was left out of libdrm, but if you have texture tiling on (default), then they should have been to 128 and would have worked out.

libdrm change that fixes this bug:

commit 7c697b1670fe34b54a7b82d8ff0732845caa05a3
Author: Eric Anholt <eric@anholt.net>
Date:   Wed Mar 17 10:05:55 2010 -0700

    intel: Align untiled buffer pitch to 64B.
    
    This is the largest untiled pitch requirement from gen2 through gen4.
    It's only the case for gen3 rendering to color regions with depth, but
    it's rare for this to be a significant factor in memory usage -- for
    example, gen4 requires 1 or 2 times the element size, or up to 64
    bytes depending on the size of the elements.  This is easier than
    encoding all the various little quirks for untiled pitch alignment,
    since we rarely do untiled now.

(In reply to comment #8)
> Sven, looks like you have texture tiling turned off?  Those pitch alignments
> look like they're to 64b, which was left out of libdrm, but if you have texture
> tiling on (default), then they should have been to 128 and would have worked
> out.

Hmm.. I haven't turned it off manually and Xorg.0.log says 
 
(**) intel(0): Tiling enabled

Any idea what could be wrong?

tiling in driconf, not xorg.

Yeah, it's turned on there too.

I experienced this bug as well, and can verify that it is indeed fixed with Mesa and drm master.  Thanks Eric!

(In reply to comment #8)
> Sven, looks like you have texture tiling turned off?  Those pitch alignments
> look like they're to 64b, which was left out of libdrm, but if you have texture
> tiling on (default), then they should have been to 128 and would have worked
> out.
> libdrm change that fixes this bug:
> commit 7c697b1670fe34b54a7b82d8ff0732845caa05a3
> Author: Eric Anholt <eric@anholt.net>
> Date:   Wed Mar 17 10:05:55 2010 -0700
>     intel: Align untiled buffer pitch to 64B.
>     This is the largest untiled pitch requirement from gen2 through gen4.
>     It's only the case for gen3 rendering to color regions with depth, but
>     it's rare for this to be a significant factor in memory usage -- for
>     example, gen4 requires 1 or 2 times the element size, or up to 64
>     bytes depending on the size of the elements.  This is easier than
>     encoding all the various little quirks for untiled pitch alignment,
>     since we rarely do untiled now.

Eric, can you cherry pick it to mesa 7.8 branch?