Bug 32402

Summary:	[piketon -next bisected] Many tests make GPU hang and reset
Product:	DRI	Reporter:	Shuang He <shuang.he>
Component:	DRM/Intel	Assignee:	Chris Wilson <chris>
Status:	CLOSED FIXED	QA Contact:	fangxun <xunx.fang>
Severity:	critical
Priority:	high	CC:	jbarnes, xunx.fang
Version:	XOrg git
Hardware:	Other
OS:	Linux (All)
Whiteboard:
i915 platform:		i915 features:

Description Shuang He 2010-12-14 19:05:15 UTC

System Environment:
--------------------------
Libdrm:        (master)2.4.22-16-g51b895041c65f7ec9ecda48e79279dde29258b07
Mesa:        (master)1eb7a81f2e43842acd59929ce65db2142b69134d
Xserver:       
(master)xorg-server-1.9.0-330-g4e0f8f666e61390206c42ad2087477a912525bc7
Xf86_video_intel:       
(master)2.13.901-5-g0bb135c40e5ac1bf7593ec1d68d2815cbf47aa25


Bug detailed description:
-------------------------
This bug hapens on Piketon. 
Many test suite piglit(3+ cases hang), OGLC(78+ cases hang)
I'm using following tests to do the bisection:
./piglit-run.py -t "texturing/tex3d"  tests/all.tests result

dmesg show:
[drm:i915_hangcheck_ring_idle] *ERROR* Hangcheck timer elapsed... render ring idle [waiting on 18017, at 18017], missed IRQ?
[drm:i915_hangcheck_ring_idle] *ERROR* Hangcheck timer elapsed... render ring idle [waiting on 18638, at 18638], missed IRQ?
[drm:i915_hangcheck_ring_idle] *ERROR* Hangcheck timer elapsed... render ring idle [waiting on 20270, at 20270], missed IRQ?


The manual bisection shows this is issue is introduced by following kernel commit:
commit 88f23b8fa3e6357c423af24ec31c661fc12f884b 160b1543cdae83e9f8914ac7afc3d2bd686140af
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Sun Dec 5 15:08:31 2010 +0000

    drm/i915: Avoid using PIPE_CONTROL on Ironlake

    The workaround is hideous and we are using the STORE_DWORD on all other
    generations on all other rings, so use for the gen5 render ring as
    well.

    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Comment 1 Chris Wilson 2010-12-15 02:08:21 UTC

commit c56bd04f97d9c01ab15348453ffec753cb621d78
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Dec 15 09:56:50 2010 +0000

    Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"
    
    Restore PIPE_CONTROL once again just for Ironlake, as it appears that
    MI_USER_INTERRUPT does have the same coherency guarantees, that is the
    interrupt following a GPU write will arrive after the write is coherent
    from the CPU, as it does on the other generations.
    
    Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
    Reported-by: Shuang He <shuang.he@intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Comment 2 Chris Wilson 2010-12-15 02:14:32 UTC

Rewrote the changelog: b84e3cbc7eed896714e9f813204ded6e34e24715.

Comment 3 fangxun 2010-12-16 21:58:51 UTC

Verified with Kernel:(drm-intel-next)9c04f015ebc2cc2cca5a4a576deb82a311578edc.

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