Bug 46043

Summary: [drm:intel_framebuffer_init] *ERROR* unsupported pixel format 0
Product: DRI Reporter: Robert de Rooy <robert.de.rooy>
Component: DRM/IntelAssignee: Jesse Barnes <jbarnes>
Status: CLOSED FIXED QA Contact:
Severity: normal    
Priority: medium CC: ben, chris, daniel, eugeni, jbarnes
Version: unspecified   
Hardware: Other   
OS: All   
See Also: https://bugzilla.kernel.org/show_bug.cgi?id=42798
Whiteboard:
i915 platform: i915 features:
Bug Depends on:    
Bug Blocks: 44622    

Description Robert de Rooy 2012-02-14 06:53:13 UTC 
On an old ThinkPad X40, recent kernels are printing a new error message during boot about an unsupported pixel format. Otherwise everything seems to work fine.

I have added the patch, as posted on the intel-gfx mailing list to print the pixel format in question, which simply returns '0'.

This is the video controller in question;

$ sudo lspci -vnns 00:2
[sudo] password for robert: 
00:02.0 VGA compatible controller [0300]: Intel Corporation 82852/855GM Integrated Graphics Device [8086:3582] (rev 02) (prog-if 00 [VGA controller])
	Subsystem: IBM Device [1014:0557]
	Flags: bus master, fast devsel, latency 0, IRQ 16
	Memory at e0000000 (32-bit, prefetchable) [size=128M]
	Memory at d0000000 (32-bit, non-prefetchable) [size=512K]
	I/O ports at 1800 [size=8]
	Expansion ROM at <unassigned> [disabled]
	Capabilities: [d0] Power Management version 1
	Kernel driver in use: i915

00:02.1 Display controller [0380]: Intel Corporation 82852/855GM Integrated Graphics Device [8086:3582] (rev 02)
	Subsystem: IBM Device [1014:0557]
	Flags: fast devsel
	Memory at e8000000 (32-bit, prefetchable) [size=128M]
	Memory at d0080000 (32-bit, non-prefetchable) [size=512K]
	Capabilities: [d0] Power Management version 1

And here are the drm messages, when booting with drm.debug=0x04

$ dmesg |grep drm
[    0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-3.3.0-0.rc3.git4.1.local.fc16.i686 root=/dev/mapper/vg_x40-lv_root ro quiet rhgb SYSFONT=latarcyrheb-sun16 LANG=en_US.UTF-8 KEYTABLE=us selinux=0 drm.debug=0x04
[    6.349870] [drm] Initialized drm 1.1.0 20060810
[    6.757171] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[    6.757177] [drm] Driver supports precise vblank timestamp query.
[    6.757266] [drm:init_vbt_defaults], Set default to SSC at 66MHz
[    6.757309] [drm:parse_general_features], BDB_GENERAL_FEATURES int_tv_support 1 int_crt_support 0 lvds_use_ssc 1 lvds_ssc_freq 66 display_clock_mode 0
[    6.757317] [drm:parse_general_definitions], crt_ddc_bus_pin: 2
[    6.757361] [drm:parse_lfp_panel_data], Found panel mode in BIOS VBT tables:
[    6.757366] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 0 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[    6.757378] [drm:parse_sdvo_device_mapping], No SDVO device info is found in VBT
[    6.757626] [drm:intel_dsm_pci_probe], no _DSM method for intel device
[    6.759073] [drm:intel_modeset_init], 2 display pipes available.
[    6.759189] [drm:intel_modeset_init], plane 0 init failed: -19
[    6.759275] [drm:intel_modeset_init], plane 1 init failed: -19
[    6.821289] [drm:tfp410_init], tfp410 not detected got VID FFFFFFFF: from i915 gmbus dpb Slave 56.
[    7.101584] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[    7.101745] [drm:intel_update_fbc], 
[    7.101757] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    7.101772] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    7.101785] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 40
[    7.101798] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 40, C: 2, SR 1
[    7.101821] [drm:i915_get_vblank_timestamp], crtc 1 is disabled
[    7.106844] [drm:intel_update_fbc], 
[    7.106855] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    7.106868] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    7.106881] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 40
[    7.106893] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 40, C: 2, SR 1
[    7.112602] [drm] initialized overlay support
[    7.113689] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[    7.113920] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[    7.113936] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[    7.113959] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[    7.116083] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[    7.116099] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection
[    7.116854] [drm:intel_framebuffer_init] *ERROR* unsupported pixel format 0
[    7.117651] [drm:intel_get_load_detect_pipe], failed to allocate framebuffer for load-detection
[    7.128454] [drm:drm_setup_crtcs], 
[    7.128642] [drm:drm_enable_connectors], connector 5 enabled? yes
[    7.128648] [drm:drm_enable_connectors], connector 9 enabled? no
[    7.128654] [drm:drm_target_preferred], looking for cmdline mode on connector 5
[    7.128660] [drm:drm_target_preferred], looking for preferred mode on connector 5
[    7.128665] [drm:drm_target_preferred], found mode 1024x768
[    7.128670] [drm:drm_setup_crtcs], picking CRTCs for 2048x2048 config
[    7.128761] [drm:drm_setup_crtcs], desired mode 1024x768 set on crtc 4
[    7.141389] [drm:intelfb_create], allocated 1024x768 fb: 0x00020000, bo f305e000
[    7.145303] fbcon: inteldrmfb (fb0) is primary device
[    7.153688] [drm:drm_crtc_helper_set_config], 
[    7.153693] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[    7.153742] [drm:drm_crtc_helper_set_config], 
[    7.153746] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[    7.153951] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
[    7.153957] [drm:drm_crtc_helper_set_config], modes are different, full mode set
[    7.153961] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    7.153969] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[    7.153977] [drm:drm_crtc_helper_set_config], encoder changed, full mode switch
[    7.153982] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
[    7.153987] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    7.153993] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
[    7.153997] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[    7.154119] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[    7.154215] [drm:drm_crtc_helper_set_mode], [CRTC:4]
[    7.154268] [drm:i9xx_crtc_mode_set], using SSC reference clock of 66 MHz
[    7.154955] [drm:i9xx_crtc_mode_set], Mode for pipe B:
[    7.154960] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[    7.155120] [drm] Changing LVDS panel from (+hsync, +vsync) to (-hsync, -vsync)
[    7.199207] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[    7.199223] [drm:intel_update_fbc], 
[    7.199235] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    7.199247] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    7.199259] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    7.199269] [drm:intel_calculate_wm], FIFO watermark level: 6
[    7.199279] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[    7.199290] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[    7.199308] [drm:drm_crtc_helper_set_mode], [ENCODER:6:LVDS-6] set [MODE:12:1024x768]
[    7.199321] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    7.199332] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    7.199343] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    7.199353] [drm:intel_calculate_wm], FIFO watermark level: 6
[    7.199363] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[    7.199373] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[    7.199871] [drm:intel_update_fbc], 
[    7.199881] [drm:intel_lvds_enable], applying panel-fitter: 8, 0
[    7.551571] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[    7.551584] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:5:LVDS-1] set DPMS on
[    7.552745] [drm:drm_crtc_helper_set_config], 
[    7.552755] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[    7.553295] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    7.553308] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
[    7.566413] [drm:drm_crtc_helper_set_config], 
[    7.566422] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[    7.566906] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    7.566919] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
[    7.580048] fb0: inteldrmfb frame buffer device
[    7.580055] drm: registered panic notifier
[    7.580592] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
[    7.779812] [drm:drm_crtc_helper_set_config], 
[    7.779817] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[    7.779923] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    7.779929] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
[    7.893372] [drm:drm_crtc_helper_set_config], 
[    7.893380] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[    7.893388] [drm:drm_crtc_helper_set_config], 
[    7.893393] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[    7.893478] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    7.893485] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
[    7.893901] [drm:drm_crtc_helper_set_config], 
[    7.893906] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[    7.893912] [drm:drm_crtc_helper_set_config], 
[    7.893916] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[    7.893990] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    7.893996] [drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
[    7.894932] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[2]
[    7.894965] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[2]
[    7.894984] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[    7.894997] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[    7.895150] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[    7.895157] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[    7.895172] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[    7.906192] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[    7.906214] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[    7.908301] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[    7.908309] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[    7.908422] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[    7.912094] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[    7.912101] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[    7.964219] [drm:intel_wait_for_vblank], vblank wait timed out
[    8.016243] [drm:intel_wait_for_vblank], vblank wait timed out
[    8.016279] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[    8.016296] [drm:intel_update_fbc], 
[    8.016310] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    8.016324] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[    8.016336] [drm:intel_calculate_wm], FIFO watermark level: 20
[    8.016348] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    8.016361] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    8.016373] [drm:intel_calculate_wm], FIFO watermark level: 6
[    8.016384] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[    8.016397] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[    8.016424] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[    8.016440] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    8.016452] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[    8.016464] [drm:intel_calculate_wm], FIFO watermark level: 20
[    8.016476] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    8.016488] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    8.016500] [drm:intel_calculate_wm], FIFO watermark level: 6
[    8.016511] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[    8.016523] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[    8.017129] [drm:intel_update_fbc], 
[    8.069215] [drm:intel_wait_for_vblank], vblank wait timed out
[    8.071345] [drm:intel_crt_load_detect], starting load-detect on CRT
[    8.084155] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[    8.084182] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[    8.098215] [drm:intel_update_fbc], 
[    8.098226] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    8.098239] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    8.098252] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    8.098264] [drm:intel_calculate_wm], FIFO watermark level: 6
[    8.098276] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[    8.098288] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[    8.098311] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[    8.098355] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[    8.098376] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[    8.100498] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[    8.100513] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[    8.100718] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[    8.109372] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[    8.109385] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[    8.161214] [drm:intel_wait_for_vblank], vblank wait timed out
[    8.213214] [drm:intel_wait_for_vblank], vblank wait timed out
[    8.213231] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[    8.213247] [drm:intel_update_fbc], 
[    8.213259] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    8.213273] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[    8.213285] [drm:intel_calculate_wm], FIFO watermark level: 20
[    8.213297] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    8.213309] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    8.213321] [drm:intel_calculate_wm], FIFO watermark level: 6
[    8.213333] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[    8.213345] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[    8.213372] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[    8.213386] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    8.213399] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[    8.213411] [drm:intel_calculate_wm], FIFO watermark level: 20
[    8.213423] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    8.213435] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    8.213447] [drm:intel_calculate_wm], FIFO watermark level: 6
[    8.213459] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[    8.213471] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[    8.214072] [drm:intel_update_fbc], 
[    8.266217] [drm:intel_wait_for_vblank], vblank wait timed out
[    8.268321] [drm:intel_crt_load_detect], starting load-detect on CRT
[    8.276552] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[    8.276575] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[    8.290214] [drm:intel_update_fbc], 
[    8.290225] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[    8.290238] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[    8.290251] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[    8.290263] [drm:intel_calculate_wm], FIFO watermark level: 6
[    8.290275] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[    8.290287] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[    8.290309] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[    8.464735] [drm:drm_mode_addfb], [FB:14]
[    8.464970] [drm:drm_mode_setcrtc], [CRTC:4]
[    8.465070] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
[    8.465077] [drm:drm_crtc_helper_set_config], 
[    8.465082] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:14] #connectors=1 (x y) (0 0)
[    8.465187] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[    8.476378] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 4096
[    8.476390] [drm:intel_update_fbc], 
[    8.494299] [drm:drm_mode_setcrtc], [CRTC:4]
[    8.494363] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
[    8.494369] [drm:drm_crtc_helper_set_config], 
[    8.494373] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:14] #connectors=1 (x y) (0 0)
[    8.494464] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   17.602347] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   23.586677] [drm:drm_crtc_helper_set_config], 
[   23.586682] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[   23.586692] [drm:drm_crtc_helper_set_config], 
[   23.586695] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[   23.586809] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   23.586840] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   23.586847] [drm:intel_update_fbc], 
[   23.601416] [drm:drm_crtc_helper_set_config], 
[   23.601421] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[   23.601536] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   23.601662] [drm:drm_crtc_helper_set_config], 
[   23.601665] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[   23.601771] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   23.610070] [drm:drm_mode_setcrtc], [CRTC:4]
[   23.610140] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
[   23.610146] [drm:drm_crtc_helper_set_config], 
[   23.610150] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:14] #connectors=1 (x y) (0 0)
[   23.610266] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   23.610275] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 4096
[   23.610283] [drm:intel_update_fbc], 
[   25.101501] [drm:drm_crtc_helper_set_config], 
[   25.101508] [drm:drm_crtc_helper_set_config], [CRTC:4] [NOFB]
[   25.379200] [drm:i915_get_vblank_timestamp], crtc 1 is disabled
[   25.390854] [drm:intel_update_fbc], 
[   25.390868] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   25.390883] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   25.390897] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 40
[   25.390910] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 40, C: 2, SR 1
[   25.399466] [drm:drm_crtc_helper_set_config], 
[   25.399480] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[   25.399522] [drm:drm_crtc_helper_set_config], 
[   25.399533] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[   25.399815] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
[   25.399828] [drm:drm_crtc_helper_set_config], encoder changed, full mode switch
[   25.399841] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
[   25.399854] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   25.399867] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
[   25.399880] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   25.401260] [drm:drm_crtc_helper_set_mode], [CRTC:4]
[   25.401304] [drm:i9xx_crtc_mode_set], using SSC reference clock of 66 MHz
[   25.402942] [drm:i9xx_crtc_mode_set], Mode for pipe B:
[   25.402954] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   25.447115] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   25.447134] [drm:intel_update_fbc], 
[   25.447148] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   25.447162] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   25.447175] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   25.447188] [drm:intel_calculate_wm], FIFO watermark level: 6
[   25.447200] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   25.447212] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   25.447232] [drm:drm_crtc_helper_set_mode], [ENCODER:6:LVDS-6] set [MODE:12:1024x768]
[   25.447247] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   25.447260] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   25.447272] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   25.447284] [drm:intel_calculate_wm], FIFO watermark level: 6
[   25.447296] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   25.447308] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   25.447809] [drm:intel_update_fbc], 
[   25.447820] [drm:intel_lvds_enable], applying panel-fitter: 8, 0
[   25.735425] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
[   25.735443] [drm:drm_crtc_helper_set_config], 	[CONNECTOR:5:LVDS-1] set DPMS on
[   28.003511] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   38.018416] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   48.034371] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   58.261677] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   58.612950] [drm:drm_crtc_helper_set_config], 
[   58.612958] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[   58.612967] [drm:drm_crtc_helper_set_config], 
[   58.612972] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[   58.613344] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   58.621347] [drm:drm_crtc_helper_set_config], 
[   58.621353] [drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB]
[   58.621360] [drm:drm_crtc_helper_set_config], 
[   58.621364] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:13] #connectors=1 (x y) (0 0)
[   58.621623] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   58.622973] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[2]
[   58.622991] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[2]
[   58.628042] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   58.628054] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[   58.628464] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[   58.628471] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   58.628486] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   58.654997] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   58.674056] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   58.679558] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   58.679566] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   58.679899] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   58.683564] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   58.683570] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   58.734057] [drm:intel_wait_for_vblank], vblank wait timed out
[   58.785045] [drm:intel_wait_for_vblank], vblank wait timed out
[   58.785059] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   58.785068] [drm:intel_update_fbc], 
[   58.785074] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   58.785081] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   58.785086] [drm:intel_calculate_wm], FIFO watermark level: 20
[   58.785091] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   58.785097] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   58.785102] [drm:intel_calculate_wm], FIFO watermark level: 6
[   58.785107] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   58.785113] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   58.785128] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   58.785135] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   58.785141] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   58.785146] [drm:intel_calculate_wm], FIFO watermark level: 20
[   58.785151] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   58.785156] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   58.785161] [drm:intel_calculate_wm], FIFO watermark level: 6
[   58.785166] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   58.785171] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   58.785729] [drm:intel_update_fbc], 
[   58.840160] [drm:intel_wait_for_vblank], vblank wait timed out
[   58.842280] [drm:intel_crt_load_detect], starting load-detect on CRT
[   58.852792] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   58.852821] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   58.867056] [drm:intel_update_fbc], 
[   58.867063] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   58.867069] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   58.867075] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   58.867081] [drm:intel_calculate_wm], FIFO watermark level: 6
[   58.867086] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   58.867091] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   58.867103] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   58.867126] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   58.867136] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   58.869159] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   58.869166] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   58.869494] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   58.873144] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   58.873150] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   58.925045] [drm:intel_wait_for_vblank], vblank wait timed out
[   58.977111] [drm:intel_wait_for_vblank], vblank wait timed out
[   58.977134] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   58.977151] [drm:intel_update_fbc], 
[   58.977164] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   58.977178] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   58.977191] [drm:intel_calculate_wm], FIFO watermark level: 20
[   58.977203] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   58.977216] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   58.977228] [drm:intel_calculate_wm], FIFO watermark level: 6
[   58.977239] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   58.977252] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   58.977281] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   58.977297] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   58.977310] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   58.977321] [drm:intel_calculate_wm], FIFO watermark level: 20
[   58.977333] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   58.977346] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   58.977358] [drm:intel_calculate_wm], FIFO watermark level: 6
[   58.977369] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   58.977381] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   58.977948] [drm:intel_update_fbc], 
[   59.030593] [drm:intel_wait_for_vblank], vblank wait timed out
[   59.038339] [drm:intel_crt_load_detect], starting load-detect on CRT
[   59.045190] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   59.045216] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   59.060111] [drm:intel_update_fbc], 
[   59.060124] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   59.060138] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   59.060152] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   59.060164] [drm:intel_calculate_wm], FIFO watermark level: 6
[   59.060176] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   59.060188] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   59.060211] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   63.999626] [drm:drm_mode_addfb], [FB:14]
[   64.000256] [drm:drm_mode_setcrtc], [CRTC:4]
[   64.000600] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
[   64.000613] [drm:drm_crtc_helper_set_config], 
[   64.000624] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:14] #connectors=1 (x y) (0 0)
[   64.001366] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   64.023432] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 4096
[   64.023453] [drm:intel_update_fbc], 
[   64.027444] [drm:drm_mode_setcrtc], [CRTC:4]
[   64.027599] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
[   64.027605] [drm:drm_crtc_helper_set_config], 
[   64.027610] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:14] #connectors=1 (x y) (0 0)
[   64.027911] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   68.294045] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   78.306124] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   79.319160] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[2]
[   79.319205] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[2] ENCODERS[2]
[   79.322626] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   79.322637] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[   79.323170] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[   79.323177] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   79.323667] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   79.327889] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   79.327901] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   79.330524] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.330532] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   79.330958] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   79.334620] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   79.334626] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   79.386110] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.438111] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.438135] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   79.438153] [drm:intel_update_fbc], 
[   79.438166] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.438180] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   79.438193] [drm:intel_calculate_wm], FIFO watermark level: 20
[   79.438205] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.438218] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.438230] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.438242] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   79.438255] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   79.438282] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   79.438298] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.438310] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   79.438322] [drm:intel_calculate_wm], FIFO watermark level: 20
[   79.438334] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.438347] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.438358] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.438370] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   79.438382] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   79.438949] [drm:intel_update_fbc], 
[   79.492097] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.497574] [drm:intel_crt_load_detect], starting load-detect on CRT
[   79.506477] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.506506] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   79.522043] [drm:intel_update_fbc], 
[   79.522050] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.522057] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.522064] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.522069] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.522074] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   79.522080] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   79.522093] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   79.522116] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   79.522125] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   79.529505] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.529513] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   79.529944] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   79.533820] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   79.533826] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   79.586136] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.638056] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.638070] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   79.638078] [drm:intel_update_fbc], 
[   79.638085] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.638091] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   79.638096] [drm:intel_calculate_wm], FIFO watermark level: 20
[   79.638102] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.638108] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.638113] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.638118] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   79.638123] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   79.638139] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   79.638146] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.638152] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   79.638157] [drm:intel_calculate_wm], FIFO watermark level: 20
[   79.638162] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.638167] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.638172] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.638177] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   79.638182] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   79.638740] [drm:intel_update_fbc], 
[   79.690130] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.701504] [drm:intel_crt_load_detect], starting load-detect on CRT
[   79.712613] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.712629] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   79.727730] [drm:intel_update_fbc], 
[   79.727737] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.727745] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.727751] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.727756] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.727761] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   79.727767] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   79.727781] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   79.728944] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   79.728955] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[   79.730988] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[   79.730996] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   79.731304] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   79.738334] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   79.738345] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   79.750978] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.750987] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   79.753127] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   79.756810] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   79.756816] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   79.808163] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.859080] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.859095] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   79.859103] [drm:intel_update_fbc], 
[   79.859110] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.859116] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   79.859121] [drm:intel_calculate_wm], FIFO watermark level: 20
[   79.859127] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.859133] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.859138] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.859143] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   79.859148] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   79.859164] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   79.859172] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.859177] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   79.859182] [drm:intel_calculate_wm], FIFO watermark level: 20
[   79.859188] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.859193] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.859198] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.859203] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   79.859208] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   79.859766] [drm:intel_update_fbc], 
[   79.916077] [drm:intel_wait_for_vblank], vblank wait timed out
[   79.918430] [drm:intel_crt_load_detect], starting load-detect on CRT
[   79.918742] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.918758] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   79.934156] [drm:intel_update_fbc], 
[   79.934163] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   79.934170] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   79.934176] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   79.934182] [drm:intel_calculate_wm], FIFO watermark level: 6
[   79.934187] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   79.934192] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   79.934207] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   79.934230] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   79.934240] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   79.939509] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   79.939517] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   79.939945] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   79.943602] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   79.943608] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   79.994040] [drm:intel_wait_for_vblank], vblank wait timed out
[   80.046058] [drm:intel_wait_for_vblank], vblank wait timed out
[   80.046073] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   80.046081] [drm:intel_update_fbc], 
[   80.046088] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   80.046095] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   80.046100] [drm:intel_calculate_wm], FIFO watermark level: 20
[   80.046105] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   80.046111] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   80.046116] [drm:intel_calculate_wm], FIFO watermark level: 6
[   80.046121] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   80.046127] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   80.046142] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   80.046150] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   80.046155] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   80.046160] [drm:intel_calculate_wm], FIFO watermark level: 20
[   80.046165] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   80.046171] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   80.046176] [drm:intel_calculate_wm], FIFO watermark level: 6
[   80.046181] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   80.046186] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   80.046743] [drm:intel_update_fbc], 
[   80.099043] [drm:intel_wait_for_vblank], vblank wait timed out
[   80.101796] [drm:intel_crt_load_detect], starting load-detect on CRT
[   80.111140] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   80.111157] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   80.129036] [drm:intel_update_fbc], 
[   80.129044] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   80.129051] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   80.129057] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   80.129063] [drm:intel_calculate_wm], FIFO watermark level: 6
[   80.129068] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   80.129074] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   80.129089] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   80.375424] [drm:drm_mode_addfb], [FB:20]
[   80.375564] [drm:drm_mode_setcrtc], [CRTC:4]
[   80.375752] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
[   80.375758] [drm:drm_crtc_helper_set_config], 
[   80.375763] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:20] #connectors=1 (x y) (0 0)
[   80.376847] [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:4]
[   80.391316] [drm:i9xx_update_plane], Writing base 00800000 00000000 0 0 4096
[   80.391330] [drm:intel_update_fbc], 
[   82.567558] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   82.567588] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[   82.568576] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[   82.568592] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   82.570175] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   82.570782] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   82.570804] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   82.575228] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   82.575245] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   82.577051] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   82.585723] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   82.585736] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   82.638251] [drm:intel_wait_for_vblank], vblank wait timed out
[   82.689221] [drm:intel_wait_for_vblank], vblank wait timed out
[   82.689242] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   82.689259] [drm:intel_update_fbc], 
[   82.689272] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   82.689286] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   82.689299] [drm:intel_calculate_wm], FIFO watermark level: 20
[   82.689311] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   82.689324] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   82.689336] [drm:intel_calculate_wm], FIFO watermark level: 6
[   82.689347] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   82.689360] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   82.689388] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   82.689403] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   82.689416] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   82.689427] [drm:intel_calculate_wm], FIFO watermark level: 20
[   82.689439] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   82.689452] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   82.689464] [drm:intel_calculate_wm], FIFO watermark level: 6
[   82.689475] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   82.689487] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   82.690103] [drm:intel_update_fbc], 
[   82.746217] [drm:intel_wait_for_vblank], vblank wait timed out
[   82.748772] [drm:intel_crt_load_detect], starting load-detect on CRT
[   82.761623] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   82.761649] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   82.777219] [drm:intel_update_fbc], 
[   82.777231] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   82.777245] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   82.777258] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   82.777270] [drm:intel_calculate_wm], FIFO watermark level: 6
[   82.777282] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   82.777295] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   82.777318] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   82.777432] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   82.777453] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   82.789676] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   82.789693] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   82.791501] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   82.800124] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   82.800137] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   82.852216] [drm:intel_wait_for_vblank], vblank wait timed out
[   82.904217] [drm:intel_wait_for_vblank], vblank wait timed out
[   82.904235] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   82.904251] [drm:intel_update_fbc], 
[   82.904264] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   82.904277] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   82.904289] [drm:intel_calculate_wm], FIFO watermark level: 20
[   82.904301] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   82.904314] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   82.904326] [drm:intel_calculate_wm], FIFO watermark level: 6
[   82.904338] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   82.904350] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   82.904377] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   82.904392] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   82.904405] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   82.904417] [drm:intel_calculate_wm], FIFO watermark level: 20
[   82.904428] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   82.904441] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   82.904453] [drm:intel_calculate_wm], FIFO watermark level: 6
[   82.904464] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   82.904476] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   82.905092] [drm:intel_update_fbc], 
[   82.958217] [drm:intel_wait_for_vblank], vblank wait timed out
[   82.960684] [drm:intel_crt_load_detect], starting load-detect on CRT
[   82.967753] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   82.967778] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   82.983216] [drm:intel_update_fbc], 
[   82.983228] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   82.983242] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   82.983255] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   82.983267] [drm:intel_calculate_wm], FIFO watermark level: 6
[   82.983279] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   82.983292] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   82.983314] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   83.383761] [drm:intel_crtc_cursor_set], 
[   88.322242] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[   95.225856] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   95.225866] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   95.227291] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   95.230994] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   95.231017] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   95.283219] [drm:intel_wait_for_vblank], vblank wait timed out
[   95.335222] [drm:intel_wait_for_vblank], vblank wait timed out
[   95.335287] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   95.335305] [drm:intel_update_fbc], 
[   95.335321] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   95.335335] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   95.335348] [drm:intel_calculate_wm], FIFO watermark level: 20
[   95.335361] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   95.335375] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   95.335387] [drm:intel_calculate_wm], FIFO watermark level: 6
[   95.335399] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   95.335413] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   95.335445] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   95.335461] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   95.335475] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   95.335487] [drm:intel_calculate_wm], FIFO watermark level: 20
[   95.335499] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   95.335512] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   95.335525] [drm:intel_calculate_wm], FIFO watermark level: 6
[   95.335536] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   95.335549] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   95.336158] [drm:intel_update_fbc], 
[   95.393218] [drm:intel_wait_for_vblank], vblank wait timed out
[   95.395712] [drm:intel_crt_load_detect], starting load-detect on CRT
[   95.409371] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   95.409400] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   95.437221] [drm:intel_update_fbc], 
[   95.437234] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   95.437248] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   95.437262] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   95.437274] [drm:intel_calculate_wm], FIFO watermark level: 6
[   95.437286] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   95.437299] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   96.712592] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   96.712622] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
[   96.714618] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
[   96.714634] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768" 50 54170 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[   96.714672] [drm:drm_mode_getconnector], [CONNECTOR:5:?]
[   96.716462] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   96.716486] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   96.719382] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   96.719399] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   96.719894] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   96.723633] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   96.723638] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   96.775217] [drm:intel_wait_for_vblank], vblank wait timed out
[   96.827216] [drm:intel_wait_for_vblank], vblank wait timed out
[   96.827237] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   96.827254] [drm:intel_update_fbc], 
[   96.827267] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   96.827282] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   96.827294] [drm:intel_calculate_wm], FIFO watermark level: 20
[   96.827306] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   96.827319] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   96.827331] [drm:intel_calculate_wm], FIFO watermark level: 6
[   96.827343] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   96.827355] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   96.827383] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   96.827398] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   96.827411] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   96.827423] [drm:intel_calculate_wm], FIFO watermark level: 20
[   96.827434] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   96.827447] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   96.827459] [drm:intel_calculate_wm], FIFO watermark level: 6
[   96.827470] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   96.827482] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   96.828099] [drm:intel_update_fbc], 
[   96.890250] [drm:intel_wait_for_vblank], vblank wait timed out
[   96.892733] [drm:intel_crt_load_detect], starting load-detect on CRT
[   96.906337] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   96.906363] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   96.920216] [drm:intel_update_fbc], 
[   96.920228] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   96.920242] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   96.920255] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   96.920267] [drm:intel_calculate_wm], FIFO watermark level: 6
[   96.920279] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   96.920292] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   96.920315] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   96.920426] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
[   96.920448] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
[   96.925576] [drm:intel_get_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   96.925592] [drm:intel_get_load_detect_pipe], reusing fbdev for load-detection framebuffer
[   96.926654] [drm:drm_crtc_helper_set_mode], [CRTC:3]
[   96.935956] [drm:i9xx_crtc_mode_set], Mode for pipe A:
[   96.935969] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
[   96.988218] [drm:intel_wait_for_vblank], vblank wait timed out
[   97.039083] [drm:intel_wait_for_vblank], vblank wait timed out
[   97.039091] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096
[   97.039099] [drm:intel_update_fbc], 
[   97.039104] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   97.039110] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   97.039115] [drm:intel_calculate_wm], FIFO watermark level: 20
[   97.039121] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   97.039126] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   97.039131] [drm:intel_calculate_wm], FIFO watermark level: 6
[   97.039136] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   97.039142] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   97.039153] [drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:0:640x480]
[   97.039160] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   97.039165] [drm:intel_calculate_wm], FIFO entries required for mode: 20
[   97.039170] [drm:intel_calculate_wm], FIFO watermark level: 20
[   97.039175] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   97.039181] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   97.039186] [drm:intel_calculate_wm], FIFO watermark level: 6
[   97.039191] [drm:i9xx_update_wm], FIFO watermarks - A: 20, B: 6
[   97.039196] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 20, B: 6, C: 2, SR 1
[   97.039752] [drm:intel_update_fbc], 
[   97.092218] [drm:intel_wait_for_vblank], vblank wait timed out
[   97.094696] [drm:intel_crt_load_detect], starting load-detect on CRT
[   97.098736] [drm:intel_release_load_detect_pipe], [CONNECTOR:9:VGA-1], [ENCODER:10:DAC-10]
[   97.098761] [drm:i915_get_vblank_timestamp], crtc 0 is disabled
[   97.114218] [drm:intel_update_fbc], 
[   97.114230] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) A: 42
[   97.114245] [drm:i85x_get_fifo_size], FIFO size - (0x00015455) B: 42
[   97.114258] [drm:intel_calculate_wm], FIFO entries required for mode: 34
[   97.114271] [drm:intel_calculate_wm], FIFO watermark level: 6
[   97.114283] [drm:i9xx_update_wm], FIFO watermarks - A: 40, B: 6
[   97.114295] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 40, B: 6, C: 2, SR 1
[   97.114319] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] disconnected
[   98.340628] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[  108.354375] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[  118.370370] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
[  128.386375] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 2 to 2
Comment 1 Eugeni Dodonov 2012-02-14 07:01:33 UTC 
So that debugging patch found out which pixel formats we are missing.
Comment 2 Chris Wilson 2012-02-29 14:47:02 UTC 
In airlied/drm-fixes:

commit 5ca0c34ae28344b6b4ca3036bc82f89c8db16a59
Author: Dave Airlie <airlied@redhat.com>
Date:   Thu Feb 23 15:33:40 2012 +0000

    drm/i915: fix mode set on load pipe. (v2)
    
    Booted my i965 machine and it started printing the unsupported pixel
    format of 0 message (once I added content to it).
    
    Oh looksie here, we pass 0. fix.
    
    v2: compile it.
    
    Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45966
    
    Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
    Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: Dave Airlie <airlied@redhat.com>
    Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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