Bug 50243

Summary:

[SNB, IVB, VLV, HSW] verify forcewake with additional thread c0 check

Product:

DRI

Reporter:

Jesse Barnes <jbarnes>

Component:

DRM/Intel

Assignee:

Daniel Vetter <daniel>

Status:

CLOSED FIXED

QA Contact:

Severity:

normal

Priority:

medium

CC:

ben, chris, daniel, jbarnes

Version:

XOrg git

Hardware:

Other

OS:

All

Whiteboard:

i915 platform:

i915 features:

Attachments:

Description	Flags
Bump the CPU to C0	none
Bump the CPU to C0	none
Implement w/a for sporadic read failures	none

Description Jesse Barnes 2012-05-22 14:43:27 UTC

Need to do the force wake poll then wait for thread C0 before knowing we're out of RC6:

http://dt.igk.intel.com/wa_database/DetailsView/Show?wa_name_id=1141

Comment 1 Chris Wilson 2012-05-29 06:31:03 UTC

Created attachment 62224 [details] [review]
Bump the CPU to C0

Something like the attached should do the trick.

Comment 2 Chris Wilson 2012-05-29 06:51:49 UTC

Created attachment 62225 [details] [review]
Bump the CPU to C0

Comment 3 Chris Wilson 2012-06-13 10:35:51 UTC

Created attachment 62980 [details] [review]
Implement w/a for sporadic read failures

Comment 4 Chris Wilson 2012-07-14 09:31:32 UTC

commit c4de7b0ffda2bb4843fd7f1052d0a2bb90bd08a5
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jul 2 11:51:03 2012 -0300

    drm/i915: Implement w/a for sporadic read failures on waking from rc6
    
    As a w/a to prevent reads sporadically returning 0, we need to wait for
    the GT thread to return to TC0 before proceeding to read the registers.
    
    v2: adapt for Haswell changes (Eugeni).
    
    v3: use wait_for_atomic_us for thread status polling.
    
    v3: *really* use wait_for_atomic for polling.
    
Note reveals side-effect bug 51738.

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