Bug 50245

Summary:	[IVB, VLV] moar clock gating
Product:	DRI	Reporter:	Jesse Barnes <jbarnes>
Component:	DRM/Intel	Assignee:	Daniel Vetter <daniel>
Status:	CLOSED FIXED	QA Contact:
Severity:	normal
Priority:	medium	CC:	ben, chris, daniel, jbarnes
Version:	XOrg git
Hardware:	Other
OS:	All
Whiteboard:
i915 platform:		i915 features:

Description Jesse Barnes 2012-05-22 14:48:52 UTC

Chicken salad.

VDS unit: http://dt.igk.intel.com/wa_database/DetailsView/Show?wa_name_id=1185
TDL unit: http://dt.igk.intel.com/wa_database/DetailsView/Show?wa_name_id=1190
L3 bank 2x: http://dt.igk.intel.com/wa_database/DetailsView/Show?wa_name_id=1218

Comment 1 Daniel Vetter 2012-06-18 09:41:03 UTC

Patch merged to dinq:

commit e3f33d46fd917747e966f8e6d25f2940223ad1ee
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Thu Jun 14 11:04:50 2012 -0700

    drm/i915: add L3 bank clock gating disable on VLV

Comment 2 Daniel Vetter 2012-06-18 09:41:41 UTC

Patch merged to dinq:

commit 6edaa7fcf287b92fb231a9e23cd6b5b0fc3dddb2
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Thu Jun 14 11:04:49 2012 -0700

    drm/i915: add TDL unit clock gating disable for VLV

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