Bug 59627

Summary: [SNB/IVB/HSW VT-d] Align sprites to 128KiB
Product: DRI Reporter: Chris Wilson <chris>
Component: DRM/IntelAssignee: Intel GFX Bugs mailing list <intel-gfx-bugs>
Status: CLOSED FIXED QA Contact: Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity: normal    
Priority: medium    
Version: XOrg git   
Hardware: Other   
OS: All   
Whiteboard:
i915 platform: i915 features:

Description Chris Wilson 2013-01-20 15:40:34 UTC
'To prevent false VT-d type 6 error, the sprites must be 128KiB aligned, and require an extra 64 PTEs of padding afterward'
Comment 1 Chris Wilson 2013-03-27 10:11:28 UTC
commit e4054a376b6c357c68215a4e2db2636a8a05e7ba
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Mar 5 14:52:39 2013 +0000

    drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

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