Bug 70605

Summary: [Gen4-5 Bisected]Piglit spec/EXT_packed_depth_stencil/fbo-blit-d24s8 fails
Product: Mesa Reporter: lu hua <huax.lu>
Component: Drivers/DRI/i965Assignee: Kenneth Graunke <kenneth>
Status: VERIFIED FIXED QA Contact: Intel 3D Bugs Mailing List <intel-3d-bugs>
Severity: major    
Priority: high CC: idr
Version: unspecified   
Hardware: All   
OS: Linux (All)   
Whiteboard:
i915 platform: i915 features:

Description lu hua 2013-10-18 09:42:58 UTC 
System Environment:
--------------------------
Platform: GM45/Ironlake
Libdrm:		(master)2.4.47
Mesa:		(master)4ef1c8fb4c0ae8d0fa2a0e4311ef63255d8485f0
Xserver:	(master)xorg-server-1.14.99.2-14-g7cf1b595c8c8f9776a39559d2878cf90af3f2859
Xf86_video_intel:(master)2.99.904-32-gec0866e86d365ae3fd9790b1b263d49fc4981220
Cairo:		(master)6f05ecf488314e4b0c6c6b0110963c449bebe7d7
Libva:		(staging)1a011ce5bb0b80506797a25a988854f3f81ce909
Libva_intel_driver:(staging)1cee858036a87837deddc87586701ed869f96261
Kernel:	(drm-intel-nightly) 164a4cb4c1431a0689f85507868356fae24da638

Bug detailed description:
-----------------------------
It fails on GM45/Ironlake with mesa master branch, and works well on 9.2 branch.

Bisect shows:4e5306453da6a1c076309e543ec92d999e02f67a is the first bad commit.
commit 4e5306453da6a1c076309e543ec92d999e02f67a
Author:     Eric Anholt <eric@anholt.net>
AuthorDate: Wed Oct 2 18:53:04 2013 -0700
Commit:     Eric Anholt <eric@anholt.net>
CommitDate: Tue Oct 15 10:18:45 2013 -0700

    i965/fs: Dynamically set up the WM binding table offsets.

    Reviewed-by: Paul Berry <stereotype441@gmail.com>


output:
Verify 1
Verify 2
Verify 3
Probe depth at (10,70)
  Expected: 0.000000
  Observed: 0.543210
Verify 4 (FBO)
Verify 5 (FBO)
Probe depth at (10,40)
  Expected: 0.000000
  Observed: 0.543210
PIGLIT: {'result': 'fail' }

Reproduce steps:
----------------------------
1. xinit&
2. bin/fbo-blit-d24s8 -auto
Comment 1 Kenneth Graunke 2013-11-26 05:00:23 UTC 
I can reproduce this on my Ironlake system; the bisect is correct.

Investigating...
Comment 2 Kenneth Graunke 2013-11-26 08:37:25 UTC 
Patch on mailing list:
http://lists.freedesktop.org/archives/mesa-dev/2013-November/049171.html

This fixes it for me on Crestline and Ironlake.
Comment 3 lu hua 2013-11-27 06:14:04 UTC 
(In reply to comment #2)
> Patch on mailing list:
> http://lists.freedesktop.org/archives/mesa-dev/2013-November/049171.html
> 
> This fixes it for me on Crestline and Ironlake.


Fixed by this patch.
Comment 4 Eric Anholt 2013-11-28 05:13:08 UTC 
commit c4815f6cd6f659acd361f1b4cf63473a46ca7de9
Author: Kenneth Graunke <kenneth@whitecape.org>
Date:   Tue Nov 26 00:30:19 2013 -0800

    i965: Always reserve binding table space for at least one render target.
Comment 5 lu hua 2013-12-02 07:27:11 UTC 
Verified.Fixed.

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