Bug 76176

Created attachment 95814 [details]
dmesg output

I forgot to mention, I saw the issue with a 3.14.0-rc3+ kernel. There are reports of the same issue with 3.12.8 and 3.13.6.

I see the same thing here, but going from untiled to a tiled flip seems to work.  Maybe the CS msg to the display block is incorrect, or the tile bit isn't getting cleared when the msg is received.  I've asked the hw guys to check into it.

We don't have a tiled->untiled->tiled pageflip testcase anywhere. No wonder this is broken and untested.

Ander, can you please convert your testcase into an igt test using the crc infrastructure to make sure we scan out the right stuff? That way we can at least validate whether this works and if needed escalate early.

The local guys in Helsinki should be able to help you out and since very recently we have neat docs for igt:

http://people.freedesktop.org/~danvet/igt/

Created attachment 96779 [details] [review]
Patch for intel-gpu-tools

Ok, I've applied the testcase with a bit of a fixup.

We're moving to mmio based flips, which should address this:
http://lists.freedesktop.org/archives/intel-gfx/2014-January/038067.html

It doesn't fix it yet...

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 97432d2..e3fba41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9763,6 +9763,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
        if (IS_VALLEYVIEW(dev)) {
                ring = &dev_priv->ring[BCS];
+               if (obj->tiling_mode != to_intel_framebuffer(old_fb)->obj->tiling_mode)
+                       ring = NULL;
+       } else if (IS_IVYBRIDGE(dev)) {
+               ring = &dev_priv->ring[BCS];
        } else if (INTEL_INFO(dev)->gen >= 7) {

I guess Chris can tilt at this windmill. :)

Another thing I don't think I tried is to write the tile reg and surf reg *after* the flip in the CS.  Writing it before didn't seem to work, probably because the tile bit got clobbered by the message from the GT side.  But writing it after, while racy, might work.

(In reply to comment #10)
> I guess Chris can tilt at this windmill. :)
> 
> Another thing I don't think I tried is to write the tile reg and surf reg
> *after* the flip in the CS.  Writing it before didn't seem to work, probably
> because the tile bit got clobbered by the message from the GT side.  But
> writing it after, while racy, might work.

Yeah mean with LRI? AFAIK LRIs targeting display registers end up in /dev/null on byt.

(In reply to comment #11)
> (In reply to comment #10)
> > I guess Chris can tilt at this windmill. :)
> > 
> > Another thing I don't think I tried is to write the tile reg and surf reg
> > *after* the flip in the CS.  Writing it before didn't seem to work, probably
> > because the tile bit got clobbered by the message from the GT side.  But
> > writing it after, while racy, might work.
> 
> Yeah mean with LRI? AFAIK LRIs targeting display registers end up in
> /dev/null on byt.

Yes. All we need to do is to make sure we do actually engage the mmio flip. Sadly the same applies for #77104

commit 8e09bf837f8c6b09784bf22c3a8c597df3c20b79
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Jul 8 10:40:30 2014 +0100

    drm/i915: Use mmio flips to change tiling mode on Baytrail
    
    For whatever reason, MI_DISPLAY_FLIP fails to change tiling mode on
    Baytrail, so just use CPU driven mmio flips instead.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76176
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>