Bug 79038

Summary:

[Regression][[i945] Crashes and bad performance on Lenovo X60 with coreboot and native graphics init

Product:

DRI

Reporter:

Paul Menzel <paulepanter>

Component:

DRM/Intel

Assignee:

Chris Wilson <chris>

Status:

CLOSED NOTOURBUG

QA Contact:

Intel GFX Bugs mailing list <intel-gfx-bugs>

Severity:

normal

Priority:

high

CC:

info, intel-gfx-bugs, paulepanter, s

Version:

XOrg git

Hardware:

Other

OS:

All

Whiteboard:

i915 platform:

i915 features:

Attachments:

Description	Flags
debugging results	none

Description Paul Menzel 2014-05-21 21:01:03 UTC

Since Linux 3.12 using the Lenovo X60 with coreboot [1] and native graphics init, meaning no VGA Option ROM, there are several crashes [2]. (The report is adapted from the coreboot Wiki [2].)

    00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03)

On 3.12 and later kernels the i915 driver became unstable. Causing broken/glitchy 3D and performance bugs.
The current suspicion is that Linux had a bug which caused it to miss stolen memory altogether on this machine and hence disable parts of code. This bug was corrected in: 17fec8a08698bcab98788e1e89f5b8e7502ababd [2],
Which was identified by `git bisect`, to be the cause of the driver crashes using coreboot native VGA init on the Lenovo X60. When reverting commit 17fec8a08 the crashes are gone.

[1] http://www.coreboot.org/
[2] http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels
[3] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd


00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub (rev 03)
00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03)
00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller (rev 03)
00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller (rev 02)
00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 02)
00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 2 (rev 02)
00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 3 (rev 02)
00:1c.3 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 4 (rev 02)
00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 02)
00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 02)
00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)
00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge (rev 02)
00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 02)
00:1f.2 SATA controller: Intel Corporation 82801GBM/GHM (ICH7 Family) SATA AHCI Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 02)
02:00.0 Ethernet controller: Intel Corporation 82573L Gigabit Ethernet Controller
03:00.0 Network controller: Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection (rev 02)
15:00.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev b4)
15:00.1 FireWire (IEEE 1394): Ricoh Co Ltd R5C552 IEEE 1394 Controller (rev 09)
15:00.2 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 18)

Comment 1 Chris Wilson 2014-05-21 21:32:35 UTC

We actually need details of the crash, glitches and poor performance. At first glance, this just looks like coreboot misconfiguring the igfx which is NOTOURBUG (and not something we can correct after the BIOS completes and locks down the PCI configuration).

Comment 2 info 2014-05-22 01:17:28 UTC

Created attachment 99547 [details]
debugging results

Note, this bug report as listed in the main description is about a regression
in linux since 3.12 and beyond which causes graphical instability (glitches/crashes)
on the ThinnkPad X60 and ThinkPad T60 when running "native graphics initialization"
in coreboot, instead of Intel's proprietary Video BIOS or VBIOS ROM.

Before linux 3.12, no issues existed, the code worked (3D worked, no instability).

Here I have some debugging results:
 - dmesg output
 - xorg log
 - kernel log
 - uname output

Distro: Trisquel 6 
http://trisquel.info/
--

linux-image-gnu-3.14.4-gnuowen_1_i386.deb
has 17fec8a (kernel git) as-is

linux-image-gnu-3e14-gnu-stolenmem-owen_1_i386.deb
has 17fec8a (kernel git) reverted

When booting with the one that has 17fec8a, gdm won't start desktop.
Restarting gdm makes desktop appear.

now see the debugging output in both directories below this one.

As per the bug report, these issues were not seen until regression
after kernel 3.12. As per above, there are two sets of debugging results:
 * with 17fec8a in kernel (as-is)
 * without (17fec8a reverted)

These kernels were shared with me, compiled for Trisquel 6.0 (distribution). Link:
 * http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_1_i386.deb
 * http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_1_i386.deb
(the 2nd one reverts 17fec8a, which removes the issues introduced in 3.12+)

--

For both kernels, I am booting with "drm.debug=0x06" kernel parameter in GRUB.

I am using coreboot as per http://libreboot.org/howto.html#x60_native_notes

How to find the code to see how coreboot is initializing the GPU:

You can see the i915 init code at http://review.coreboot.org/#/c/5320
under (using that patch):
 * src/northbridge/intel/i945/gma.c
 * src/mainboard/lenovo/x60/devicetreee.cb

Those are modified in the patch. New files are added:
 * src/northbridge/intel/i945/chip.h

To get the full source, git clone coreboot with:
$ git clone http://review.coreboot.org/coreboot
$ git fetch http://review.coreboot.org/coreboot refs/changes/20/5320/6 && git checkout FETCH_HEAD

And look at those files (patched) listed in the source, as per list at http://review.coreboot.org/#/c/5320

Comment 3 info 2014-05-22 01:18:52 UTC

Note: see attachment in last comment.

Comment 4 info 2014-05-22 01:36:23 UTC

Note: those debugging results show 3.12+ kernel (3.14.4 in this case) with and without 17fec8a. By reverting 17fec8a the issues no longer exist; as in pre-3.12. 

Should I also get the same debugging results with a kernel prior to 3.12 (such as 3.10) and 3.12 itself?

Comment 5 Chris Wilson 2014-05-22 06:05:57 UTC

Stolen memory has been set up incorrectly by coreboot.

Comment 6 Paul Menzel 2014-05-22 14:13:26 UTC

(In reply to comment #5)
> Stolen memory has been set up incorrectly by coreboot.

Chris, thank you for looking into this. As far as I understand Linux’ no regression policy, once code worked even due to bugs in the firmware it has to continue to work and everything changing that is a regression. What did I miss?

Comment 7 Paul Menzel 2014-05-22 14:15:32 UTC

Francis, thank you for attaching the log messages. Next time please attach them separately (and uncompressed) so people can use the Web interface to look at them.

Comment 8 Chris Wilson 2014-05-22 14:17:33 UTC

The BIOS is lying entirely about the layout of memory. Other than quirking and refusing to load on coreboot, what do you propose? It is safe to say that coreboot does not yet fulfill its function as a BIOS.

Comment 9 info 2014-05-22 14:46:56 UTC

My idea was to detect coreboot on the i945 northbridge platforms when native gfx init is in use, and patch around it.

This idea is based on Paul's idea of linux "no regression policy". commit 17fec8a as per bug report is what broke compatibility; my idea would be for linux to selectively revert those changes for i945 platform when native gfx is in use, so as to maintain previous (pre-3.12 kernel) compatibility.

(some users are already sticking to 3.10, or manually reverting 17fec8a and compiling the resulting kernel)

Comment 10 info 2014-05-22 14:48:08 UTC

(that is to say, 17fec8a would only be in effect when native gfx on i945 is not in use, whereas in the fringe/minority case of coreboot it would disable that part of code, if-elseif style).

Comment 11 Paul Menzel 2014-05-22 14:50:59 UTC

(In reply to comment #8)
> The BIOS is lying entirely about the layout of memory. Other than quirking
> and refusing to load on coreboot, what do you propose?

Can the incorrect layout be detected and the stolen memory feature be disabled in that case?

> It is safe to say that coreboot does not yet fulfill its function as a BIOS.

First, coreboot does not try to be a BIOS. :p Please keep in mind, that it works fine when running/using the VGA BIOS instead of doing native graphics init.

Comment 12 Paul Menzel 2014-05-22 15:08:33 UTC

(In reply to comment #11)
> (In reply to comment #8)
> > The BIOS is lying entirely about the layout of memory. Other than quirking
> > and refusing to load on coreboot, what do you propose?
> 
> Can the incorrect layout be detected and the stolen memory feature be
> disabled in that case?

Looking at your Linux patch again, my statement is incorrect, in that the “stolen memory” feature was used before, but now the Graphics Base of Stolen Memory is determined in a different way.

Before:

    u8 val;
    /* Stolen is immediately below Top of Low Usable DRAM */
    pci_read_config_byte(pdev, 0x9c, &val);
    base = val >> 3 << 27;
    base -= dev_priv->mm.gtt->stolen_size;

After:

    pci_read_config_dword(dev->pdev, 0x5c, &base);
    base &= ~((1<<20) - 1);

Could a switch be added which method to use, which the user can add on the command line?

I agree that it sucks, but LibreBoot already shipped laptops with that firmware, so we cannot force the users to upgrade the firmware. A module option would be a good compromise, as far as I see it.

> > It is safe to say that coreboot does not yet fulfill its function as a BIOS.
> 
> First, coreboot does not try to be a BIOS. :p Please keep in mind, that it
> works fine when running/using the VGA BIOS instead of doing native graphics
> init.

Comment 13 Paul Menzel 2014-06-01 17:43:03 UTC

(In reply to comment #8)
> The BIOS is lying entirely about the layout of memory.

Chris, could you please paste the corresponding parts from the log files, so I can see what is incorrect?


    [    0.000000] BIOS-e820: [mem 0x00000000bf800000-0x00000000bfffffff] reserved
    [    0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
    […]
    [    0.451755] [drm] Memory usable by graphics device = 256M
    [    0.451763] [drm:i915_gem_gtt_init], GMADR size = 256M
    [    0.451766] [drm:i915_gem_gtt_init], GTT stolen size = 8M
    […]
    [    0.452118] [drm:i915_gem_init_stolen], found 8388608 bytes of stolen memory at bf800000
    […]

So the 8 MB are reserved correctly, aren’t they? Could you please point me to the messages denoting that the memory is set up incorrectly?

Comment 14 info 2014-06-01 19:51:45 UTC

Paul, I've compiled a list of changes in coreboot that fix things that were missing or incorrect before, which may or may not be relevant. Here is the list: http://libreboot.org/howto.html#i945_gfx_improve

Comment 15 Paul Menzel 2014-06-02 06:37:18 UTC

Here is the content of the error file.

$ more /sys/class/drm/card0/error
Time: 1401660987 s 272232 us
Kernel: 3.14.4-gnuowen
PCI ID: 0x27a2
EIR: 0x00000010
IER: 0x00028053
PGTBL_ER: 0x00000012
FORCEWAKE: 0x00000000
DERRMR: 0x00000000
CCID: 0x00000000
Missed interrupts: 0x00000000
  fence[0] = 00000000
  fence[1] = 00000000
  fence[2] = 00000000
  fence[3] = 00000000
  fence[4] = 00000000
  fence[5] = 00000000
  fence[6] = 00000000
  fence[7] = 00000000
  fence[8] = 00000000
  fence[9] = 00000000
  fence[10] = 00000000
  fence[11] = 00000000
  fence[12] = 00000000
  fence[13] = 00000000
  fence[14] = 00000000
  fence[15] = 00000000
  INSTDONE_0: 0x7fffffc0
  INSTDONE_1: 0x00000000
  INSTDONE_2: 0x00000000
  INSTDONE_3: 0x00000000
Active [0]:
Pinned [0]:
Num Pipes: 2
Pipe [0]:
  Power: off
  SRC: 00000000
Plane [0]:
  CNTR: 00000000
  STRIDE: 00000000
  SIZE: 00000000
  POS: 00000000
  ADDR: 00000000
Cursor [0]:
  CNTR: 00000000
  POS: 00000000
  BASE: 00000000
Pipe [1]:
  Power: off
  SRC: 00000000
Plane [1]:
  CNTR: 00000000
  STRIDE: 00000000
  SIZE: 00000000
  POS: 00000000
  ADDR: 00000000
Cursor [1]:
  CNTR: 00000000
  POS: 00000000
  BASE: 00000000
CPU transcoder: A
  Power: off
  CONF: 00000000
  HTOTAL: 00000000
  HBLANK: 00000000
  HSYNC: 00000000
  VTOTAL: 00000000
  VBLANK: 00000000
  VSYNC: 00000000
CPU transcoder: A
  Power: off
  CONF: 00000000
  HTOTAL: 00000000
  HBLANK: 00000000
  HSYNC: 00000000
  VTOTAL: 00000000
  VBLANK: 00000000
  VSYNC: 00000000

Comment 16 Paul Menzel 2014-06-03 22:51:32 UTC

Difference in output of `intel_reg_dumper`. Please not that the machine below is with 1 GB of RAM. For some reason PGETBL_CTL is different.

-                    PGETBL_CTL: 0x3ffc0001
+                    PGETBL_CTL: 0x3f800001

$ diff -u x60_5893_vbios/intel_reg_dumper x60_5893_native/intel_reg_dumper
--- x60_5893_vbios/intel_reg_dumper	2014-06-01 23:20:38.000000000 +0200
+++ x60_5893_native/intel_reg_dumper	2014-06-02 00:03:11.000000000 +0200
@@ -1,20 +1,20 @@
-                    PGETBL_CTL: 0x3ffc0001
-                      PGTBL_ER: 0x00000000
+                    PGETBL_CTL: 0x3f800001
+                      PGTBL_ER: 0x00000013
                           EXCC: 0x00000000
                        HWS_PGA: 0x34aae000
                          IPEIR: 0x00000000
-                         IPEHR: 0x01000000
+                         IPEHR: 0x0badfb8c
                      INST_DONE: 0x7fffffc0
                          NOPID: 0x00000000
-                        HWSTAM: 0xffffeffe
-                         SCPD0: 0x00000200
+                        HWSTAM: 0xfffceffe
+                         SCPD0: 0x00000000
                            IER: 0x00028053
                            IIR: 0x00000000
                            IMR: 0xfffd73ae
                            ISR: 0x00000000
                            EIR: 0x00000000
-                           EMR: 0xffffffed
-                           ESR: 0x00000001
+                           EMR: 0xfffffffd
+                           ESR: 0x00000011
                        INST_PM: 0x00000800
                        ECOSKPD: 0x00000306
                  DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
@@ -31,40 +31,40 @@
              C0DRA23: 0x00000201 (0x0201)
              C1DRA01: 0x00000000 (0x0000)
              C1DRA23: 0x00000000 (0x0000)
-          PGETBL_CTL: 0x3ffc0001
+          PGETBL_CTL: 0x3f800001
    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
            DPLL_TEST: 0x00010001 ()
         CACHE_MODE_0: 0x00006820
              D_STATE: 0x0000000b
-       DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
+       DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
       RENCLK_GATE_D1: 0x00000000
       RENCLK_GATE_D2: 0x00000000
-               SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected)
-               SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
+               SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected)
+               SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
              SDVOUDI: 0x0000001b
               DSPARB: 0x00001d9c
               DSPFW1: 0x00000000
               DSPFW2: 0x00000000
               DSPFW3: 0x00000000
-                ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
+                ADPA: 0x00000000 (disabled, pipe A, -hsync, -vsync)
                 LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel)
                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
-                DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
-                DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
+                DVOB: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
+                DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
          DVOA_SRCDIM: 0x00000000
          DVOB_SRCDIM: 0x00000000
          DVOC_SRCDIM: 0x00000000
           PP_CONTROL: 0xabcd0001 (power target: on)
            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
-        PP_ON_DELAYS: 0x00fa09c4
-       PP_OFF_DELAYS: 0x00fa09c4
+        PP_ON_DELAYS: 0x019007d0
+       PP_OFF_DELAYS: 0x015e07d0
           PP_DIVISOR: 0x00270f04
         PFIT_CONTROL: 0x00000008
      PFIT_PGM_RATIOS: 0x00000000
      PORT_HOTPLUG_EN: 0x00000220
-   PORT_HOTPLUG_STAT: 0x00000000
+   PORT_HOTPLUG_STAT: 0x00000400
             DSPACNTR: 0xd9000000 (enabled, pipe B)
           DSPASTRIDE: 0x00001000 (4096 bytes)
              DSPAPOS: 0x00000000 (0, 0)
@@ -73,8 +73,8 @@
             DSPASURF: 0x00000000
          DSPATILEOFF: 0x00000000
            PIPEACONF: 0x00000000 (disabled, single-wide)
-            PIPEASRC: 0x027f01df (640, 480)
-           PIPEASTAT: 0x10000000 (status: CRC_DONE_ENABLE)
+            PIPEASRC: 0x04ff03ff (1280, 1024)
+           PIPEASTAT: 0x10000203 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
    PIPEA_GMCH_DATA_M: 0x00000000
    PIPEA_GMCH_DATA_N: 0x00000000
      PIPEA_DP_LINK_M: 0x00000000
@@ -82,35 +82,35 @@
        CURSOR_A_BASE: 0x00000000
     CURSOR_A_CONTROL: 0x00000000
    CURSOR_A_POSITION: 0x00000000
-                FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
-                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
-              DPLL_A: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
+                FPA0: 0x00020f03 (n = 2, m1 = 15, m2 = 3)
+                FPA1: 0x00020f03 (n = 2, m1 = 15, m2 = 3)
+              DPLL_A: 0x00000000 (disabled, non-dvo, VGA, default clock, unknown mode, p1 = 0, p2 = 0, SDVO mult 1)
            DPLL_A_MD: 0x00000000
-            HTOTAL_A: 0x031f027f (640 active, 800 total)
-            HBLANK_A: 0x03170287 (648 start, 792 end)
-             HSYNC_A: 0x02ef028f (656 start, 752 end)
-            VTOTAL_A: 0x020c01df (480 active, 525 total)
-            VBLANK_A: 0x020401e7 (488 start, 517 end)
-             VSYNC_A: 0x01eb01e9 (490 start, 492 end)
+            HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
+            HBLANK_A: 0x06af04ff (1280 start, 1712 end)
+             HSYNC_A: 0x05d70557 (1368 start, 1496 end)
+            VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
+            VBLANK_A: 0x044f03ff (1024 start, 1104 end)
+             VSYNC_A: 0x04090402 (1027 start, 1034 end)
            BCLRPAT_A: 0x00000000
         VSYNCSHIFT_A: 0x00000000
-            DSPBCNTR: 0x01000000 (disabled, pipe B)
-          DSPBSTRIDE: 0x00000000 (0 bytes)
+            DSPBCNTR: 0x58000000 (disabled, pipe A)
+          DSPBSTRIDE: 0x00001400 (5120 bytes)
              DSPBPOS: 0x00000000 (0, 0)
-            DSPBSIZE: 0x018f02cf (720, 400)
-            DSPBBASE: 0x00000000
+            DSPBSIZE: 0x03ff04ff (1280, 1024)
+            DSPBBASE: 0x00800000
             DSPBSURF: 0x00000000
          DSPBTILEOFF: 0x00000000
            PIPEBCONF: 0x80000000 (enabled, single-wide)
             PIPEBSRC: 0x03ff02ff (1024, 768)
-           PIPEBSTAT: 0x10000202 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS)
+           PIPEBSTAT: 0x10000242 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS)
    PIPEB_GMCH_DATA_M: 0x00000000
    PIPEB_GMCH_DATA_N: 0x00000000
      PIPEB_DP_LINK_M: 0x00000000
      PIPEB_DP_LINK_N: 0x00000000
-       CURSOR_B_BASE: 0x00000000
-    CURSOR_B_CONTROL: 0x10000000
-   CURSOR_B_POSITION: 0x01390210
+       CURSOR_B_BASE: 0x3579c000
+    CURSOR_B_CONTROL: 0x14000027
+   CURSOR_B_POSITION: 0x00bd0052
                 FPB0: 0x00020f04 (n = 2, m1 = 15, m2 = 4)
                 FPB1: 0x00020f04 (n = 2, m1 = 15, m2 = 4)
               DPLL_B: 0x98046000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14, SDVO mult 1)
@@ -127,40 +127,40 @@
    VCLK_DIVISOR_VGA1: 0x00031406
        VCLK_POST_DIV: 0x00020002
             VGACNTRL: 0x80000000 (disabled)
-              TV_CTL: 0x00000000
+              TV_CTL: 0x000c0000
               TV_DAC: 0x70000000
-            TV_CSC_Y: 0x00000000
-           TV_CSC_Y2: 0x00000000
-            TV_CSC_U: 0x00000000
-           TV_CSC_U2: 0x00000000
-            TV_CSC_V: 0x00000000
-           TV_CSC_V2: 0x00000000
-        TV_CLR_KNOBS: 0x00000000
-        TV_CLR_LEVEL: 0x00000000
-          TV_H_CTL_1: 0x00000000
-          TV_H_CTL_2: 0x00000000
-          TV_H_CTL_3: 0x00000000
-          TV_V_CTL_1: 0x00000000
-          TV_V_CTL_2: 0x00000000
-          TV_V_CTL_3: 0x00000000
-          TV_V_CTL_4: 0x00000000
-          TV_V_CTL_5: 0x00000000
-          TV_V_CTL_6: 0x00000000
-          TV_V_CTL_7: 0x00000000
-         TV_SC_CTL_1: 0x00000000
-         TV_SC_CTL_2: 0x00000000
+            TV_CSC_Y: 0x0332012d
+           TV_CSC_Y2: 0x07d30104
+            TV_CSC_U: 0x0733052d
+           TV_CSC_U2: 0x05c70200
+            TV_CSC_V: 0x0340030c
+           TV_CSC_V2: 0x06d00200
+        TV_CLR_KNOBS: 0x00606000
+        TV_CLR_LEVEL: 0x010b00e1
+          TV_H_CTL_1: 0x00400359
+          TV_H_CTL_2: 0x80480022
+          TV_H_CTL_3: 0x007c0344
+          TV_V_CTL_1: 0x00f01415
+          TV_V_CTL_2: 0x00060607
+          TV_V_CTL_3: 0x80120001
+          TV_V_CTL_4: 0x000900f0
+          TV_V_CTL_5: 0x000a00f0
+          TV_V_CTL_6: 0x000900f0
+          TV_V_CTL_7: 0x000a00f0
+         TV_SC_CTL_1: 0xc1710087
+         TV_SC_CTL_2: 0x6b405140
          TV_SC_CTL_3: 0x00000000
-          TV_WIN_POS: 0x00000000
-         TV_WIN_SIZE: 0x00000000
-     TV_FILTER_CTL_1: 0x00000000
-     TV_FILTER_CTL_2: 0x00000000
-     TV_FILTER_CTL_3: 0x00000000
+          TV_WIN_POS: 0x00360024
+         TV_WIN_SIZE: 0x02640198
+     TV_FILTER_CTL_1: 0x800010bb
+     TV_FILTER_CTL_2: 0x00028283
+     TV_FILTER_CTL_3: 0x00014141
        TV_CC_CONTROL: 0x00000000
           TV_CC_DATA: 0x00000000
-         TV_H_LUMA_0: 0x00000000
-        TV_H_LUMA_59: 0x00000000
-       TV_H_CHROMA_0: 0x00000000
-      TV_H_CHROMA_59: 0x00000000
+         TV_H_LUMA_0: 0xb1403000
+        TV_H_LUMA_59: 0x0000b060
+       TV_H_CHROMA_0: 0xb1403000
+      TV_H_CHROMA_59: 0x0000b060
         FBC_CFB_BASE: 0x00000000
          FBC_LL_BASE: 0x00000000
          FBC_CONTROL: 0x01f40000
@@ -169,7 +169,7 @@
         FBC_CONTROL2: 0x00000000
        FBC_FENCE_OFF: 0x00000000
          FBC_MOD_NUM: 0x00000000
-             MI_MODE: 0x00000200
+             MI_MODE: 0x00000000
         MI_ARB_STATE: 0x00000840
       MI_RDRET_STATE: 0x00000000
              ECOSKPD: 0x00000306
@@ -207,53 +207,54 @@
        AUD_OUT_CWCAP: 0x00000000
          AUD_GRP_CAP: 0x00000000
             FENCE  0: 0x00400231 (enabled, X tiled, 4096 pitch, 0x00400000 - 0x00800000 (4096kb))
-            FENCE  1: 0x04f00021 (enabled, X tiled, 2048 pitch, 0x04f00000 - 0x05000000 (1024kb))
-            FENCE  2: 0x03400231 (enabled, X tiled, 4096 pitch, 0x03400000 - 0x03800000 (4096kb))
-            FENCE  3: 0x05000021 (enabled, X tiled, 2048 pitch, 0x05000000 - 0x05100000 (1024kb))
-            FENCE  4: 0x02000231 (enabled, X tiled, 4096 pitch, 0x02000000 - 0x02400000 (4096kb))
+            FENCE  1: 0x00000000 (disabled)
+            FENCE  2: 0x00000000 (disabled)
+            FENCE  3: 0x00000000 (disabled)
+            FENCE  4: 0x00000000 (disabled)
             FENCE  5: 0x00000000 (disabled)
-            FENCE  6: 0x02c00231 (enabled, X tiled, 4096 pitch, 0x02c00000 - 0x03000000 (4096kb))
+            FENCE  6: 0x00000000 (disabled)
             FENCE  7: 0x00000000 (disabled)
             FENCE  8: 0x00000000 (disabled)
-            FENCE  9: 0x03c00231 (enabled, X tiled, 4096 pitch, 0x03c00000 - 0x04000000 (4096kb))
-           FENCE  10: 0x05400231 (enabled, X tiled, 4096 pitch, 0x05400000 - 0x05800000 (4096kb))
-           FENCE  11: 0x04a00021 (enabled, X tiled, 2048 pitch, 0x04a00000 - 0x04b00000 (1024kb))
+            FENCE  9: 0x00000000 (disabled)
+           FENCE  10: 0x00000000 (disabled)
+           FENCE  11: 0x00000000 (disabled)
            FENCE  12: 0x00000000 (disabled)
-           FENCE  13: 0x04c00021 (enabled, X tiled, 2048 pitch, 0x04c00000 - 0x04d00000 (1024kb))
-           FENCE  14: 0x04d00021 (enabled, X tiled, 2048 pitch, 0x04d00000 - 0x04e00000 (1024kb))
-           FENCE  15: 0x04e00021 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 0: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 0: 0x03c00231 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 1: 0x05400231 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 1: 0x04a00021 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 2: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 2: 0x04c00021 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 3: 0x04d00021 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 3: 0x04e00021 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 4: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 4: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 5: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 5: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 6: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 6: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 7: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 7: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 8: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 8: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-       FENCE START 9: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-         FENCE END 9: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-      FENCE START 10: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-        FENCE END 10: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-      FENCE START 11: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-        FENCE END 11: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-      FENCE START 12: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-        FENCE END 12: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-      FENCE START 13: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-        FENCE END 13: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-      FENCE START 14: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-        FENCE END 14: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-      FENCE START 15: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
-        FENCE END 15: 0x00000000 (enabled, X tiled, 2048 pitch, 0x04e00000 - 0x04f00000 (1024kb))
+           FENCE  13: 0x00000000 (disabled)
+           FENCE  14: 0x00000000 (disabled)
+           FENCE  15: 0x00000000 (disabled)
+       FENCE START 0: 0x00000000 (disabled)
+         FENCE END 0: 0x00000000 (disabled)
+       FENCE START 1: 0x00000000 (disabled)
+         FENCE END 1: 0x00000000 (disabled)
+       FENCE START 2: 0x00000000 (disabled)
+         FENCE END 2: 0x00000000 (disabled)
+       FENCE START 3: 0x00000000 (disabled)
+         FENCE END 3: 0x00000000 (disabled)
+       FENCE START 4: 0x00000000 (disabled)
+         FENCE END 4: 0x00000000 (disabled)
+       FENCE START 5: 0x00000000 (disabled)
+         FENCE END 5: 0x00000000 (disabled)
+       FENCE START 6: 0x00000000 (disabled)
+         FENCE END 6: 0x00000000 (disabled)
+       FENCE START 7: 0x00000000 (disabled)
+         FENCE END 7: 0x00000000 (disabled)
+       FENCE START 8: 0x00000000 (disabled)
+         FENCE END 8: 0x00000000 (disabled)
+       FENCE START 9: 0x00000000 (disabled)
+         FENCE END 9: 0x00000000 (disabled)
+      FENCE START 10: 0x00000000 (disabled)
+        FENCE END 10: 0x00000000 (disabled)
+      FENCE START 11: 0x00000000 (disabled)
+        FENCE END 11: 0x00000000 (disabled)
+      FENCE START 12: 0x00000000 (disabled)
+        FENCE END 12: 0x00000000 (disabled)
+      FENCE START 13: 0x00000000 (disabled)
+        FENCE END 13: 0x00000000 (disabled)
+      FENCE START 14: 0x00000000 (disabled)
+        FENCE END 14: 0x00000000 (disabled)
+      FENCE START 15: 0x00000000 (disabled)
+        FENCE END 15: 0x00000000 (disabled)
              INST_PM: 0x00000800
-pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
+p1 out of range
+pipe A dot 216000 n 2 m1 15 m2 3 p1 1 p2 10
 pipe B dot 54166 n 2 m1 15 m2 4 p1 3 p2 14

Comment 17 Paul Menzel 2014-06-03 23:14:25 UTC

(In reply to comment #15)
> Here is the content of the error file.

[…]

… and decoded.

$ ./tools/intel_error_decode /tmp/error
Time: 1401660987 s 272232 us
Kernel: 3.14.4-gnuowen
PCI ID: 0x27a2
Detected GEN3 chipset
EIR: 0x00000010
IER: 0x00028053
PGTBL_ER: 0x00000012
    Display A: Invalid GTT PTE
    Host Invalid PTE data
FORCEWAKE: 0x00000000
DERRMR: 0x00000000
CCID: 0x00000000
Missed interrupts: 0x00000000
  fence[0] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[1] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[2] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[3] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[4] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[5] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[6] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[7] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[8] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[9] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[10] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[11] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[12] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[13] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[14] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  fence[15] = 00000000
    invalid, x-tiled, pitch: 512, start: 0x00000000, size: 1048576
  INSTDONE_0: 0x7fffffc0
  INSTDONE_1: 0x00000000
  INSTDONE_2: 0x00000000
  INSTDONE_3: 0x00000000
Active [0]:
Pinned [0]:
Num Pipes: 2
Pipe [0]:
  Power: off
  SRC: 00000000
Plane [0]:
  CNTR: 00000000
  STRIDE: 00000000
  SIZE: 00000000
  POS: 00000000
  ADDR: 00000000
Cursor [0]:
  CNTR: 00000000
  POS: 00000000
  BASE: 00000000
Pipe [1]:
  Power: off
  SRC: 00000000
Plane [1]:
  CNTR: 00000000
  STRIDE: 00000000
  SIZE: 00000000
  POS: 00000000
  ADDR: 00000000
Cursor [1]:
  CNTR: 00000000
  POS: 00000000
  BASE: 00000000
CPU transcoder: A
  Power: off
  CONF: 00000000
  HTOTAL: 00000000
  HBLANK: 00000000
  HSYNC: 00000000
  VTOTAL: 00000000
  VBLANK: 00000000
  VSYNC: 00000000
CPU transcoder: A
  Power: off
  CONF: 00000000
  HTOTAL: 00000000
  HBLANK: 00000000
  HSYNC: 00000000
  VTOTAL: 00000000
  VBLANK: 00000000
  VSYNC: 00000000

Comment 18 Paul Menzel 2014-06-04 07:46:51 UTC

Kyösti M. pointed me to the fact, that before commit 17fec8a0 [1] `base = 0` was returned all the time [1], meaning that code was not used at all! I wish the commit message would have been clearer on that point.

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd
[2] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/i915/i915_gem_stolen.c?id=17fec8a08698bcab98788e1e89f5b8e7502ababd^#n79

Comment 19 Paul Menzel 2014-06-04 13:35:48 UTC

Setting `PGETBL_CTL` to the value, the Video BIOS sets it to, it seems to work.

No the question is, how to determine what value to set it to. `BSM`, as currently done, does not seem to be it.

Comment 20 info 2014-06-04 18:15:07 UTC

There are still errors in crashdump, but we got it to work on a version of the native graphics code in coreboot:
http://review.coreboot.org/#/c/5927/

Test results:
http://libreboot.org/dumps/5927_3.tar.gz

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