| Summary: | [BDW IPS] Pipe A FIFO underrun errors with a 4k display | ||||||
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| Product: | DRI | Reporter: | Timo Aaltonen <tjaalton> | ||||
| Component: | DRM/Intel | Assignee: | Ville Syrjala <ville.syrjala> | ||||
| Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
| Severity: | normal | ||||||
| Priority: | medium | CC: | hawara, intel-gfx-bugs, james.ausmus, joe.konno, yk | ||||
| Version: | unspecified | ||||||
| Hardware: | Other | ||||||
| OS: | All | ||||||
| Whiteboard: | |||||||
| i915 platform: | i915 features: | ||||||
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Description
Timo Aaltonen
2014-09-04 13:39:49 UTC
Huuum, a bit of a shot in the dark, but what happens if you boot with i915.enable_ips=0. There's a known corruption case with IPS when dotclock > 95% cdclock (which can happen here as you have an eDP 4k display, so IPS should be running) I wouldn't expect an underrun here given the description of the IPS problem we have, but it's an easy thing to try. yep, disabling IPS works around it (In reply to comment #1) > There's a known corruption case with IPS when dotclock > > 95% cdclock (which can happen here as you have an eDP 4k display, so IPS > should be running) Bspec says, "Do not enable IPS when the pipe pixel rate is greater than 95% of the CDCLK frequency." IOW, IPS should *not* be running in this case. I presume the missing check should be added to hsw_compute_ips_config(). this issue is blocking us from shipping. bumping the importance to high+critical . please let me know if this is not appropriate. thanks -YK Created attachment 105813 [details] [review] [PATCH] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk This patch should implement the appropriate logic to disable IPS when the pixel rate is too high. Please test and report back. (In reply to comment #5) > Created attachment 105813 [details] [review] [review] > [PATCH] drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk > > This patch should implement the appropriate logic to disable IPS when the > pixel rate is too high. Please test and report back. Ville, care to post the patch on the ml? Or waiting for tested-by first? I'll get some results tomorrow, thanks! the patch fixed the issue, thanks commit b698837d6ff579e3d5080d10fd544c408a2b0f29 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Fri Sep 12 17:01:57 2014 +0300 drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk Reopen, because the fix regressed and I had to drop it. http://mid.gmane.org/CA+gsUGTyAkga0D8HsVgrp+4dK5dsCvye8NiTrUCV_zjXqQzbpA@mail.gmail.com I had a few moments of boredom and ended up wroting a bit more code to fix this. git://gitorious.org/vsyrjala/linux.git bdw_ips_vs_cdclk Please test again to make sure I didn't fumble anything. good news, the patches worked There's an 18 patch series leading to the fix on the intel-gfx list now: http://mid.gmane.org/1416235432-16603-1-git-send-email-ville.syrjala@linux.intel.com Ville, please update the branch on gitorious for Timo to test. Thanks. What happened here? Were these patches ever merged and issue fixed? (In reply to Rodrigo Vivi from comment #15) > What happened here? Were these patches ever merged and issue fixed? They were not merged I'm afraid. Lots of changes, no proper review. :( The silver lining is that there's recent and renewed interest in the cdclk frequency change, with someone tasked to do the job, so perhaps we'll see progress in this front: http://mid.gmane.org/0E453B799E337542AA1CE4FBF7118D8B4F74A2A3@BGSMSX102.gar.corp.intel.com Fixed by commit 184e4c49484501f3061ae9b267af818c6894fea9 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Jun 3 15:45:11 2015 +0300 drm/i915: Don't enable IPS when pixel rate exceeds 95% in drm-intel-nightly. Thanks for the report, please reopen if the problem persists with that. |
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