| Summary: | [BDW/BSW Bisected]Piglit spec_ARB_shader_atomic_counters_array-indexing fails | ||
|---|---|---|---|
| Product: | Mesa | Reporter: | lu hua <huax.lu> |
| Component: | Drivers/DRI/i965 | Assignee: | Ben Widawsky <ben> |
| Status: | VERIFIED FIXED | QA Contact: | Intel 3D Bugs Mailing List <intel-3d-bugs> |
| Severity: | major | ||
| Priority: | high | CC: | ben, idr |
| Version: | unspecified | ||
| Hardware: | All | ||
| OS: | Linux (All) | ||
| Whiteboard: | |||
| i915 platform: | i915 features: | ||
| Attachments: | VS does the enables differently than ps | ||
|
Description
lu hua
2014-12-12 07:19:51 UTC
ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert fails on BSW due to the same bisect commit. Test run totals: Passed: 0/1 (0.00%) Failed: 1/1 (100.00%) Not supported: 0/1 (0.00%) Warnings: 0/1 (0.00%) Kristian, can you reproduce this? Just to confirm the failure is intermittent for me. How about you?
bwidawsk@gibson ~/intel-gfx/piglit (master)$ while [ 1 ] ; do ./bin/arb_shader_atomic_counters-array-indexing -auto -fbo | grep Vertex -A1 |tail -n1 ; done 2>/dev/null
PIGLIT: {"result": "pass" }
PIGLIT: {"result": "fail" }
PIGLIT: {"result": "fail" }
PIGLIT: {"result": "fail" }
PIGLIT: {"result": "pass" }
PIGLIT: {"result": "fail" }
PIGLIT: {"result": "fail" }
PIGLIT: {"result": "pass" }
PIGLIT: {"result": "pass" }
PIGLIT: {"result": "fail" }
PIGLIT: {"result": "pass" }
Oh, hmm.. that's only with a patch I added locally, nvm Created attachment 113516 [details] [review] VS does the enables differently than ps Please test (In reply to Ben Widawsky from comment #5) > Created attachment 113516 [details] [review] [review] > VS does the enables differently than ps > > Please test Fixed by this patch. (In reply to Ben Widawsky from comment #5) > Created attachment 113516 [details] [review] [review] > VS does the enables differently than ps > > Please test Hey, nice catch, Ben! I didn't spot this when I was looking at it a while ago. Using the CE register makes a lot of sense. A couple of suggestions on the patch: 1. Could you put a /* HSW+ */ comment after the #define BRW_ARF_CE 0x40? 2. Could we put the MESA_SHADER_VERTEX case before the uses_kill case, just to keep the two pixel shader cases together? 3. I think vstride should be 0, not 4...I honestly have no idea why brw_ip_reg is the way it is, but it's been that way forever. We should probably also drop the NOTE! and ? comments. Assuming the vstride change actually works, and you're good with those suggestions, feel free to put my R-b on it. Hey Ken. I dropped the CE register parts because on further inspection, I don't think it's useful (it's just duplicating the internal execution mask). Anyway, thanks for looking at it, hopefully the version I just pushed is at least as good as this one :-) lu hua, The patch is pushed. Closing bug. Verified.Fixed. |
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