Summary: | Spilling failure of b96 merged value | ||
---|---|---|---|
Product: | Mesa | Reporter: | Ilia Mirkin <imirkin> |
Component: | Drivers/DRI/nouveau | Assignee: | Nouveau Project <nouveau> |
Status: | RESOLVED FIXED | QA Contact: | Nouveau Project <nouveau> |
Severity: | normal | ||
Priority: | medium | CC: | r9ku1q |
Version: | git | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | |||
i915 platform: | i915 features: | ||
Attachments: | shader causing spill failure |
Description
Ilia Mirkin
2015-05-06 18:41:59 UTC
Created attachment 115607 [details]
shader causing spill failure
Compile with -a e4 to get the failure. Works on GK110 since that has 256 registers.
This is what ultimately causes the failure at emit time:
140: texfetch 2D $r0 $s0 f32 $r48t $r48q (8)
141: texbar - # $r48t (8)
142: st b96 # l[0x0] $r48t (8)
codegen/nv50_ir_emit_nvc0.cpp:1659:emitLoadStoreType: Assertion `!"invalid type"' failed.
This is a preliminary patch to resolve the issue that I wrote a while back: https://github.com/imirkin/mesa/commit/25c74a866b5b555699520552caeccb1e8426d86b.patch Note that it needs a counterpart unspill variant too (although that's not hit by this shader). And ideally it'd be smart enough to go for a 64 + 32 store rather than 3x 32, but that's probably too much -- split then re-merge. (Or can split take unevenly sized defs? That seems like asking for trouble.) I've pushed out a version of this patch. Should be included in 11.0.x and the upcoming 11.1 release. |
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