Summary: | [SKL] scaler atomic code tries to read back CDCLK while the device is suspended | ||||||
---|---|---|---|---|---|---|---|
Product: | DRI | Reporter: | Damien Lespiau <damien.lespiau> | ||||
Component: | DRM/Intel | Assignee: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
Severity: | normal | ||||||
Priority: | medium | CC: | bugs, chandra.konduru, intel-gfx-bugs | ||||
Version: | XOrg git | ||||||
Hardware: | Other | ||||||
OS: | All | ||||||
Whiteboard: | |||||||
i915 platform: | i915 features: | ||||||
Attachments: |
|
Description
Damien Lespiau
2015-06-05 16:47:35 UTC
Where's the edit button so I can remove that duplicated trace? :( Initial implementation used cached scale values which were calculated at every modeset time. But based on review feedback it was changed to use live values by calling skylake_get_display_clock_speed(). Right fix is to precompute required clock and maintain in crtc_state. Either this caller or any other caller can look into crtc_state to get the active clock or clock that is about to be set (incase of modeset). Should be fixed by commit f662af8c5c1619b91e3834fff103e7423e20df81 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Wed Jun 10 10:24:20 2015 +0200 Revert "drm/i915: Read hw state into an atomic state struct, v2." please retest current drm-intel-nightly. Should be fixed in -nightly by commit 27c329ed16ddf5540151dfa9d22c584b819e0718 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Mon Jun 15 12:33:56 2015 +0200 drm/i915: Make cdclk part of the atomic state. Please expect delayed responses. Created attachment 132936 [details]
attachment-21412-0.html
Hi,
Out of office. Please expect delays.
|
Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.