| Summary: | Tonga IH ring misaligned | ||||||
|---|---|---|---|---|---|---|---|
| Product: | DRI | Reporter: | Jay Cornwall <jay> | ||||
| Component: | DRM/AMDgpu | Assignee: | Default DRI bug account <dri-devel> | ||||
| Status: | RESOLVED FIXED | QA Contact: | |||||
| Severity: | normal | ||||||
| Priority: | medium | ||||||
| Version: | DRI git | ||||||
| Hardware: | Other | ||||||
| OS: | All | ||||||
| Whiteboard: | |||||||
| i915 platform: | i915 features: | ||||||
| Attachments: |
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Created attachment 117903 [details] [review] possible fix This should fix it. Works good, thanks. Fixed long ago. |
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From amdgpu_ih.c: adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL); if (adev->irq.ih.ring == NULL) return -ENOMEM; adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev, (void *)adev->irq.ih.ring, adev->irq.ih.ring_size, PCI_DMA_BIDIRECTIONAL); The Tonga IH_RB_BASE register requires 256B alignment. kzalloc does not guarantee this, e.g.: adev->irq.ih.ring: 0xFFFF880835B22148 adev->irq.ih.rb_dma_addr: 0x835B22148 IH_RB_BASE: 0835b221 This causes amdgpu_ih_decode_iv to read ahead of the last written IV, missing it, when this misalignment occurs.