Summary: | [BAT SKL BDW] missed interrupt in gem_storedw_loop/basic-render with *ERROR* Hangcheck timer elapsed... | ||||||
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Product: | DRI | Reporter: | Daniel Vetter <daniel> | ||||
Component: | DRM/Intel | Assignee: | Mika Kuoppala <mika.kuoppala> | ||||
Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
Severity: | normal | ||||||
Priority: | highest | CC: | intel-gfx-bugs, knikkane, mika.kuoppala | ||||
Version: | XOrg git | ||||||
Hardware: | Other | ||||||
OS: | All | ||||||
Whiteboard: | |||||||
i915 platform: | i915 features: | ||||||
Attachments: |
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Description
Daniel Vetter
2016-01-13 10:07:42 UTC
Wow, it's telling that the render ring is so slow! :) I can run this in a loop until I get bored (>10minutes) on -nightly and haven't encountered an issue yet. I'd like to see the error state to see if there are any clues there. I suspect Daniel got confused by the error message. For what I can see, the gem_store_dwloop triggers the hangcheck timer elapsed, rander ring idle errors. Created attachment 121002 [details] [review] drm/i915: Force ordering on request submission and hangcheck (In reply to Mika Kuoppala from comment #3) > Created attachment 121002 [details] [review] [review] > drm/i915: Force ordering on request submission and hangcheck You can't move the list manipulation just like that! It's time we eliminated that list_empty() check, but this does nothing to paper over the race. (In reply to Mika Kuoppala from comment #2) > I suspect Daniel got confused by the error message. For what I can see, the > gem_store_dwloop triggers the hangcheck timer elapsed, rander ring idle > errors. Yeah I screwed up the title, it's "just" that the sw tracking got out of whack with reality, the gpu is actually perfectly fine. After all the testcase does succeed (and it checks that all the CS dw stores did land). Same bug most likely in gem_sync/basic-render. commit 7c17d377374ddbcfb7873366559fc4ed8b296e11 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed Jan 20 15:43:35 2016 +0200 drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists For the record, this only happens for me when I have an output connected - suggests some interesting hilarity with memory bw/latency. |
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