Summary: | [HSW] compute indirect dispatch with 0 work groups causes gpu hang | ||
---|---|---|---|
Product: | Mesa | Reporter: | Ilia Mirkin <imirkin> |
Component: | Drivers/DRI/i965 | Assignee: | Ian Romanick <idr> |
Status: | RESOLVED FIXED | QA Contact: | Intel 3D Bugs Mailing List <intel-3d-bugs> |
Severity: | normal | ||
Priority: | medium | ||
Version: | git | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | |||
i915 platform: | i915 features: | ||
Attachments: | dirty patch to conditionally terminate batch on hsw |
Description
Ilia Mirkin
2016-02-11 19:47:59 UTC
Created attachment 121729 [details]
dirty patch to conditionally terminate batch on hsw
This very very dirty patch looks like does the trick. 0x36 is MI_CONDITIONAL_BATCH_BUFFER_END. This will need a helper to deal with RELOC64 on gen8+ of course. Or perhaps gen8 can deal with 0-sized workgroups directly.
commit 9a939ebb47a0d37a6b29e3dbb1b20bdc9538a721 i965/gen7: Use predicated rendering for indirect compute |
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