Bug 95207

Summary:

[SKL] 5k tiled display issues (dual DP)

Product:

DRI

Reporter:

Tomas Bzatek <bugs>

Component:

DRM/Intel

Assignee:

Intel GFX Bugs mailing list <intel-gfx-bugs>

Status:

CLOSED FIXED

QA Contact:

Intel GFX Bugs mailing list <intel-gfx-bugs>

Severity:

normal

Priority:

medium

CC:

airlied, bugs, intel-gfx-bugs

Version:

DRI git

Hardware:

x86-64 (AMD64)

OS:

All

Whiteboard:

i915 platform:

SKL

i915 features:

display/DP

Attachments:

Description	Flags
dmesg drm.debug=0x1e (4.6.0-rc5-g1101e5f, 2016y-04m-28d-16h-43m-10s UTC)	none
Xorg.0.log, no xorg.conf Monitor section	none
Xorg.0.log, custom modeline	none
EDID dumps (tar.gz)	none
i915_opregion	none
[PATCH 1/3] drm/displayid: Enhance version reporting	none
[PATCH 2/3] drm/displayid: Iterate over all DisplayID blocks	none
[PATCH 3/3] drm/displayid: Parse type 1 detailed timings	none
dmesg with type1 timings parsed	none
photo of the garbage	none
fglrx Xorg.log	none

Description Tomas Bzatek 2016-04-29 13:00:05 UTC

Created attachment 123345 [details]
dmesg drm.debug=0x1e (4.6.0-rc5-g1101e5f, 2016y-04m-28d-16h-43m-10s UTC)

I'm fighting to get native 5k display working, kindly asking for debugging instructions or hints. This is Dell UP2715K, connected via two native DP ports on a C236 board (SunrisePoint PCH) running Skylake E3-1275v5 CPU. Note that I can get native resolution under Windows 7 just fine, ruling out HW incompatibility.

kernel 4.6.0-rc5-g1101e5f, drm-intel-nightly branch 2016y-04m-28d-16h-43m-10s UTC
xorg-server git as of 2016-04-28
xf86-video-intel git as of 2016-04-28
libdrm git as of 2016-04-28

Presumably this is a tiled display with two 2560x2880@60 tiles, one for each DP port.


First problem: native resolution is not detected, only fallback modelines are generated. The display falls back to 2560x1440 on a first port and 848x480 on the second as parsed from EDID. Interesting parts of the drm.debug=0x1e log:

> [    0.602822] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz

> [    0.969823] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1]
> [    0.969824] [drm:intel_dp_detect] [CONNECTOR:42:DP-1]
> [    0.970368] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 00 01 83 02 02 06 00 00 00 00
> [    0.970895] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
> [    0.970897] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
> [    0.970898] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
> [    0.970903] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
> [    0.971318] [drm:intel_dp_probe_oui] Sink OUI: 000000
> [    0.971790] [drm:intel_dp_probe_oui] Branch OUI: 000000
> [    0.972192] [drm:intel_dp_probe_mst] Sink is not MST capable
> [    0.983910] [drm:drm_parse_display_id] base revision 0x12, length 121, 0 0
> [    0.983938] [drm:drm_parse_display_id] block id 18, rev 0, len 22
> [    0.983939] [drm:drm_parse_display_id] tile cap 0x82
> [    0.983939] [drm:drm_parse_display_id] tile_size 2560 x 2880
> [    0.983940] [drm:drm_parse_display_id] topo num tiles 2x1, location 1x0
> [    0.983941] [drm:drm_parse_display_id] vend DEL
> [    0.984617] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1] status updated from unknown to connected
> [    0.984809] [drm:drm_edid_to_eld] ELD monitor DELL UP2715K
> [    0.984810] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
> [    0.984813] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1] probed modes :
> [    0.984815] [drm:drm_mode_debug_printmodeline] Modeline 59:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9
> [    0.984816] [drm:drm_mode_debug_printmodeline] Modeline 60:"3840x2160" 60 533250 3840 3920 3952 4000 2160 2214 2219 2222 0x40 0xa
> [    0.984817] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
> [    0.984818] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
> [    0.984819] [drm:drm_mode_debug_printmodeline] Modeline 65:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
> [    0.984820] [drm:drm_mode_debug_printmodeline] Modeline 63:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
> [    0.984821] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
> [    0.984822] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
> [    0.984823] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
> [    0.984824] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
> [    0.984825] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
> [    0.984826] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa

> [    0.985499] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2]
> [    0.985499] [drm:intel_dp_detect] [CONNECTOR:48:DP-2]
> [    0.986218] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 00 01 83 02 02 06 00 00 00 00
> [    0.986731] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
> [    0.986732] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
> [    0.986733] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
> [    0.986734] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
> [    0.987181] [drm:intel_dp_probe_oui] Sink OUI: 000000
> [    0.987622] [drm:intel_dp_probe_oui] Branch OUI: 000000
> [    0.988100] [drm:intel_dp_probe_mst] Sink is not MST capable
> [    0.996162] [drm:drm_parse_display_id] base revision 0x12, length 121, 0 0
> [    0.996163] [drm:drm_parse_display_id] block id 18, rev 0, len 22
> [    0.996164] [drm:drm_parse_display_id] tile cap 0x80
> [    0.996165] [drm:drm_parse_display_id] tile_size 2560 x 2880
> [    0.996165] [drm:drm_parse_display_id] topo num tiles 2x1, location 0x0
> [    0.996183] [drm:drm_parse_display_id] vend DEL
> [    0.996909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2] status updated from unknown to connected
> [    0.996944] [drm:drm_edid_to_eld] ELD: no CEA Extension found
> [    0.996945] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2] probed modes :
> [    0.996947] [drm:drm_mode_debug_printmodeline] Modeline 72:"848x480" 60 29750 848 896 928 1008 480 483 488 494 0x48 0x9

This confirms tile setup and proper dimensions. Could the issue here be that the mode corresponding to the tile size is not included in the EDID data?



Second problem: trying custom modelines. Generated using `cvt` with reduced blanking, pixel clock is within limits:
> [     3.237] (II) intel(0): EDID for output DP1
> [     3.237] (II) intel(0): Max Image Size [cm]: horiz.: 60  vert.: 34
> [     3.237] (II) intel(0): Ranges: V min: 29 V max: 75 Hz, H min: 31 H max: 180 kHz, PixClock max 545 MHz
> [     3.237] (II) intel(0): Modeline "2560x2880"x60.0  483.25  2560 2608 2640 2720  2880 2883 2893 2962 +hsync -vsync (177.7 kHz UP)
...
> [     3.360] (II) intel(0): switch to mode 2560x2880@60.0 on DP1 using pipe 0, position (0, 0), rotation normal, reflection none
> [     3.360] (II) intel(0): switch to mode 2560x2880@60.0 on DP2 using pipe 1, position (0, 0), rotation normal, reflection none
> [     3.360] (II) intel(0): Setting screen physical size to 677 x 762

(^^ this is running an X login manager with cloned screen)

> [    17.940] (II) intel(0): resizing framebuffer to 5120x2917
> [    17.977] (II) intel(0): switch to mode 2560x2880@60.0 on DP1 using pipe 0, position (2560, 0), rotation normal, reflection none
> [    17.979] (II) intel(0): switch to mode 2560x2880@60.0 on DP2 using pipe 1, position (0, 37), rotation normal, reflection none

(^^ this is after manual randr correction) - the 2917 px height looks suspicious

This actually results in some image, tiles are aligned side by side. However resulting image is garbled, torn in several pieces, weird colours etc. Seems to be panel issue itself resulting from wrong timings as OSD menu is also mispositioned and broken. Note that with vanilla 4.6.0-rc5 I cannot get any image so there's something in the drm-intel-nightly branch that enables at least the garbled image. Almost there...

Could the problem be that I'm trying to push independent screens on two DP ports that are out of sync? Does the DP tiling need to be configured specially? I've tried different modelines, increasing pixel clock, blanking intervals, etc. with no difference. 



Third problem: perhaps unrelated, reported already in other bugs:
> [    1.059275] [drm:intel_enable_pipe] enabling pipe A
...
> [    1.078707] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
> [    1.078949] [drm:skylake_pfit_enable] for crtc_state = ffff880809299800
> [    1.079296] ------------[ cut here ]------------
> [    1.079298] WARNING: CPU: 1 PID: 6 at drivers/gpu/drm/i915/intel_pm.c:3647 skl_update_other_pipe_wm+0x10f/0x120
> [    1.079299] WARN_ON(!wm_changed)
...
> [    1.079310]  [<ffffffff81421f4f>] ? skl_update_other_pipe_wm+0x10f/0x120
> [    1.079311]  [<ffffffff814220a4>] ? skl_update_wm+0x144/0x590
> [    1.079313]  [<ffffffff814ab1f7>] ? intel_ddi_enable_transcoder_func+0x167/0x230
> [    1.079314]  [<ffffffff8148eb61>] ? haswell_crtc_enable+0x741/0x8c0
...


Attached is dmesg with drm.debug=0x1e, Xorg.0.log will follow.

Let me know if you want me to test any patches. Thanks!

Comment 1 Tomas Bzatek 2016-04-29 13:02:40 UTC

Created attachment 123346 [details]
Xorg.0.log, no xorg.conf Monitor section

timestamps correspond with the previous dmesg dump

Comment 2 Tomas Bzatek 2016-04-29 13:03:41 UTC

Created attachment 123347 [details]
Xorg.0.log, custom modeline

related to the second problem described, trying custom modeline.

Comment 3 Jani Nikula 2016-04-29 13:12:22 UTC

Interesting setup. I'm surprised that none of the DP outputs list the tile size as a mode.

Comment 4 Ville Syrjala 2016-04-29 13:39:12 UTC

(In reply to Jani Nikula from comment #3)
> Interesting setup. I'm surprised that none of the DP outputs list the tile
> size as a mode.

Perhaps the modes are only defined in the DisplayID? We don't seem to parse anything but the tile stuff from there.

Comment 5 Jani Nikula 2016-04-29 14:21:50 UTC

Please attach /sys/class/drm/card0-DP-1/edid and /sys/class/drm/card0-DP-2/edid.

Comment 6 Tomas Bzatek 2016-04-29 14:29:55 UTC

Created attachment 123348 [details]
EDID dumps (tar.gz)

(In reply to Jani Nikula from comment #5)
> Please attach /sys/class/drm/card0-DP-1/edid and
> /sys/class/drm/card0-DP-2/edid.

Attached. Thanks for looking into this so quickly.

Comment 7 Jani Nikula 2016-04-29 14:39:20 UTC

Oh, please also attach /sys/kernel/debug/dri/0/i915_opregion.

Comment 8 Tomas Bzatek 2016-04-29 14:45:08 UTC

Created attachment 123349 [details]
i915_opregion

(In reply to Jani Nikula from comment #7)
> Oh, please also attach /sys/kernel/debug/dri/0/i915_opregion.

Attached. Note that I'm grabbing this remotely at the moment, the display is probably sleeping in DPMS right now. In case the dump contains runtime state...

Comment 9 Dave Airlie 2016-04-29 23:27:11 UTC

It looks like we need to enhance our displayid parser. there is definitely a mode hidden in there. Will look next week.

Comment 10 Tomas Bzatek 2016-05-01 15:14:00 UTC

You were right, there are hidden modes in the DisplayID block. Googling around I found a nice DisplayID parser within EMGD DRM driver so I hacked parts of that code up in the following patches.

http://downloadmirror.intel.com/22865/eng/LIN_IEMGD_1_18_GOLD_3398.tgz

Apparently that's a GPLv2 licensed code,
Copyright (c) 2002-2010, Intel Corporation

Comment 11 Tomas Bzatek 2016-05-01 15:14:54 UTC

Created attachment 123388 [details] [review]
[PATCH 1/3] drm/displayid: Enhance version reporting

Comment 12 Tomas Bzatek 2016-05-01 15:16:56 UTC

Created attachment 123389 [details] [review]
[PATCH 2/3] drm/displayid: Iterate over all DisplayID blocks

I wonder whether the 0x12 block always comes first, otherwise the tiling information may not have been parsed previously.

Comment 13 Tomas Bzatek 2016-05-01 15:18:01 UTC

Created attachment 123390 [details] [review]
[PATCH 3/3] drm/displayid: Parse type 1 detailed timings

Hoping my modeline calculations are correct...

Comment 14 Tomas Bzatek 2016-05-01 15:27:30 UTC

Created attachment 123391 [details]
dmesg with type1 timings parsed

So with the above three patches I'm actually able to see the native resolution modes parsed. Attaching fresh dmesg, the interesting part is this one:

> [    0.969147] [drm:intel_dp_detect] [CONNECTOR:42:DP-1]
> [    0.983551] [drm:drm_parse_display_id] base revision v1.2, edid length 128, bytes 121, prod_id 0 ext_count 0
> [    0.983552] [drm:drm_parse_display_id] block id 0x12, rev 0, len 22
> [    0.983553] [drm:drm_parse_display_id] tile cap 0x82
> [    0.983553] [drm:drm_parse_display_id] tile_size 2560 x 2880
> [    0.983558] [drm:drm_parse_display_id] topo num tiles 2x1, location 1x0
> [    0.983567] [drm:drm_parse_display_id] vend DEL
> [    0.983568] [drm:drm_parse_display_id] block id 0x3, rev 0, len 60
> [    0.983594] [drm:drm_parse_display_id]    Modeline "3840x2160@60"  533240  3840 3887 3919 3999  2160 2162 2167 2221  +hsync -vsync
> [    0.983595] [drm:drm_parse_display_id]      pixel clock 533240 kHz, preferred = 1, interlaced = 0, aspect_ratio = 4, stereo_3d_support = 0
> [    0.983596] [drm:drm_parse_display_id]      hactive = 3840, hblank = 160, hsync_offset = 48, hsync_width = 32
> [    0.983597] [drm:drm_parse_display_id]      vactive = 2160, vblank = 62, vsync_offset = 3, vsync_width = 5
> [    0.983598] [drm:drm_parse_display_id]      hblank_start = 3839, width = 3840, hblank_end = 3999, hsync_start = 3887, hsync_end = htotal = 3919
> [    0.983608] [drm:drm_parse_display_id]      vblank_start = 2159, height = 2160, vblank_end = 2221, vsync_start = 2162, vsync_end = vtotal = 2167
> [    0.983609] [drm:drm_parse_display_id]    Modeline "2560x2880@30"  238240  2560 2607 2639 2719  2880 2882 2892 2920  +hsync -vsync
> [    0.983610] [drm:drm_parse_display_id]      pixel clock 238240 kHz, preferred = 0, interlaced = 0, aspect_ratio = 4, stereo_3d_support = 0
> [    0.983611] [drm:drm_parse_display_id]      hactive = 2560, hblank = 160, hsync_offset = 48, hsync_width = 32
> [    0.983611] [drm:drm_parse_display_id]      vactive = 2880, vblank = 41, vsync_offset = 3, vsync_width = 10
> [    0.983617] [drm:drm_parse_display_id]      hblank_start = 2559, width = 2560, hblank_end = 2719, hsync_start = 2607, hsync_end = htotal = 2639
> [    0.983618] [drm:drm_parse_display_id]      vblank_start = 2879, height = 2880, vblank_end = 2920, vsync_start = 2882, vsync_end = vtotal = 2892
> [    0.983619] [drm:drm_parse_display_id]    Modeline "2560x2880@60"  483240  2560 2607 2639 2719  2880 2882 2892 2961  +hsync -vsync
> [    0.983620] [drm:drm_parse_display_id]      pixel clock 483240 kHz, preferred = 0, interlaced = 0, aspect_ratio = 4, stereo_3d_support = 0
> [    0.983620] [drm:drm_parse_display_id]      hactive = 2560, hblank = 160, hsync_offset = 48, hsync_width = 32
> [    0.983625] [drm:drm_parse_display_id]      vactive = 2880, vblank = 82, vsync_offset = 3, vsync_width = 10
> [    0.983626] [drm:drm_parse_display_id]      hblank_start = 2559, width = 2560, hblank_end = 2719, hsync_start = 2607, hsync_end = htotal = 2639
> [    0.983627] [drm:drm_parse_display_id]      vblank_start = 2879, height = 2880, vblank_end = 2961, vsync_start = 2882, vsync_end = vtotal = 2892
> [    0.983628] [drm:drm_parse_display_id] block id 0x7, rev 0, len 10
> [    0.983628] [drm:drm_parse_display_id] found DisplayID tag 0x7, unhandled

The 0x07 block contains VESA timings, not expecting any special modes there. FYI, the panel marks the "3840x2160@60" mode as preferred, we wouldn't get native resolution out-of-the-box if the flag is honored.

Comment 15 Tomas Bzatek 2016-05-01 15:37:25 UTC

Created attachment 123392 [details]
photo of the garbage

So that was the good news. Unfortunately the reported modes are suspiciously similar to reduced-blanking CVT modes I've already tried before. Hooking them up in xrandr results in the same garbled image again - check the attached photo. 

This is just one example of distortion as interpreted by the panel controller (unidentified "Mstar" model). Quite often also the monitor runs out of sync and flickers.

Comment 16 Dave Airlie 2016-05-03 06:23:15 UTC

I've pushed a branch here
https://cgit.freedesktop.org/~airlied/linux/log/?h=drm-displayid-timings

git://people.freedesktop.org/~airlied/linux drm-displayid-timings

This patchset is not tested yet, but it attempts to add the modes from the displayid block to at least fix the first problem

Comment 17 Tomas Bzatek 2016-05-03 19:10:58 UTC

(In reply to Dave Airlie from comment #16)
> I've pushed a branch here
> https://cgit.freedesktop.org/~airlied/linux/log/?h=drm-displayid-timings
> 
> git://people.freedesktop.org/~airlied/linux drm-displayid-timings
> 
> This patchset is not tested yet, but it attempts to add the modes from the
> displayid block to at least fix the first problem

Confirming this works fine, all modes are properly detected now. The image corruption issue remains unchanged as expected.

> [    0.747544] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1] probed modes :
> [    0.747545] [drm:drm_mode_debug_printmodeline] Modeline 72:"3840x2160" 60 533240 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
> [    0.747546] [drm:drm_mode_debug_printmodeline] Modeline 59:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9
> [    0.747547] [drm:drm_mode_debug_printmodeline] Modeline 60:"3840x2160" 60 533250 3840 3920 3952 4000 2160 2214 2219 2222 0x40 0xa
> [    0.747548] [drm:drm_mode_debug_printmodeline] Modeline 74:"2560x2880" 60 483240 2560 2608 2640 2720 2880 2883 2893 2962 0x40 0x9
> [    0.747549] [drm:drm_mode_debug_printmodeline] Modeline 73:"2560x2880" 30 238240 2560 2608 2640 2720 2880 2883 2893 2921 0x40 0x9
> [    0.747550] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
> [    0.747551] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
> [    0.747552] [drm:drm_mode_debug_printmodeline] Modeline 65:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
> [    0.747553] [drm:drm_mode_debug_printmodeline] Modeline 63:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
> [    0.747554] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
> [    0.747555] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
> [    0.747556] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
> [    0.747557] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
> [    0.747558] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
> [    0.747559] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa

> [    0.759326] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2] probed modes :
> [    0.759327] [drm:drm_mode_debug_printmodeline] Modeline 75:"848x480" 60 29750 848 896 928 1008 480 483 488 494 0x48 0x9
> [    0.759329] [drm:drm_mode_debug_printmodeline] Modeline 77:"2560x2880" 60 483240 2560 2608 2640 2720 2880 2883 2893 2962 0x40 0x9
> [    0.759339] [drm:drm_mode_debug_printmodeline] Modeline 76:"2560x2880" 30 238240 2560 2608 2640 2720 2880 2883 2893 2921 0x40 0x9

(the 3840x2160 mode is listed twice since the panel itself reports slightly different timings in DisplayID vs. EDID)

Thanks Dave!

Comment 18 Dave Airlie 2016-05-03 20:35:06 UTC

btw can I add Signed-off-by: to the two patches I took from here for you?

Comment 19 Tomas Bzatek 2016-05-04 10:59:38 UTC

(In reply to Dave Airlie from comment #18)
> btw can I add Signed-off-by: to the two patches I took from here for you?

Sure, no problem.

Btw. I've noticed minor detail, since the detailed 1 timings live in a separate function now - the block id 0x03 is reported as unhandled:

> [    0.751759] [drm:drm_parse_display_id] block id 0x3, rev 0, len 60
> [    0.751760] [drm:drm_parse_display_id] found DisplayID tag 0x3, unhandled
> [    0.751760] [drm:drm_parse_display_id] block id 0x7, rev 0, len 10
> [    0.751761] [drm:drm_parse_display_id] found DisplayID tag 0x7, unhandled

You may probably want to add empty DATA_BLOCK_TYPE_1_DETAILED_TIMING case to the drm_parse_display_id() switch. I originally raised the printk() to DRM_DEBUG_KMS() so that we know there's something more reported by the panel that we don't parse. This doesn't affect functionality though.

Comment 20 Tomas Bzatek 2016-05-07 14:19:12 UTC

I have a AMD FirePro W2100 here for testing. Using radeon drm driver results in EXACTLY the same kind of image corruption as with i915. Modelines are detected properly with the drm-displayid-timings branch. However, proprietary fglrx driver works nicely (being just utterly slow in 2D). Modelines reported by fglrx are basically equal to my previous findings. Xorg.log attached for inspiration.

So what are we missing? Is the panel expecting perfectly synchronized both outputs? (meaning the particular frame data being sent at the exact moment on both outputs) Is there a driver option to force that? Is it some extra flag in the DP protocol? Anything else to try?

Comment 21 Tomas Bzatek 2016-05-07 14:25:39 UTC

Created attachment 123535 [details]
fglrx Xorg.log

Comment 22 Tomas Bzatek 2016-07-13 20:25:25 UTC

Ping - the synchronization issues (attachment 123392 [details]) are still a problem, preventing the monitor to be used at its native resolution. Do you want me to open separate bugreport for that? Or can you give me some hints for debugging?

(just re-tested on drm-intel-nightly 2016y-07m-13d-14h-43m-27s)

Comment 23 Jurriaan 2016-07-22 15:08:17 UTC

And a ping from me, since I'm about to get a mini-computer with an i5-6400T (with intel HD 530), 2 displayports and a Dell UP2715K.

Comment 24 Tomas Bzatek 2016-08-08 14:29:15 UTC

Tested on vanilla 4.7.0 kernel, modeline detection works fine now.

Filed bug 97244 for the sync issues, closing this one as fixed.

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.