| Summary: | Trying to set mode 3840x2160 at 60 Hz results in a crash | ||||||||||
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| Product: | DRI | Reporter: | Oli <b52> | ||||||||
| Component: | DRM/Intel | Assignee: | Ville Syrjala <ville.syrjala> | ||||||||
| Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||||||
| Severity: | normal | ||||||||||
| Priority: | medium | CC: | intel-gfx-bugs, jared.dominguez, matthew.d.roper | ||||||||
| Version: | DRI git | ||||||||||
| Hardware: | x86-64 (AMD64) | ||||||||||
| OS: | Linux (All) | ||||||||||
| Whiteboard: | |||||||||||
| i915 platform: | SKL | i915 features: | display/DP | ||||||||
| Attachments: |
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Description
Oli
2016-05-13 20:38:23 UTC
Please add drm.debug=14 module parameter, reproduce the problem, and attach the dmesg to bugzilla. Created attachment 123819 [details]
dmesg with drm.debug=14
The bug reproduced with kernel option 'drm.debug=14'
[ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 Your cdclk is too low for that mode. I have a branch which has the required bits to adjust cdclk dynamically on SKL: git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2 Can you test with that branch? (In reply to Ville Syrjala from comment #3) > [ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz > [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > Your cdclk is too low for that mode. Why didn't we reject the mode? (In reply to Jani Nikula from comment #4) > (In reply to Ville Syrjala from comment #3) > > [ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz > > [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > > > Your cdclk is too low for that mode. > > Why didn't we reject the mode? The current upstream SKL cdclk code is bad. It sets the max cdclk to something != current cdclk even though we don't actually support changing the frequency. Created attachment 123848 [details]
dmesg of the kernel from the alternative branch
(In reply to Ville Syrjala from comment #3) > [ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz > [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > Your cdclk is too low for that mode. I have a branch which has the required > bits to adjust cdclk dynamically on SKL: > git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2 > > Can you test with that branch? I did and it seems to works, at least the display didn't blank and xrandr reports 60 Hz. Though, I have no way to tell if this is really the case, because my display won't show this information. See the attached dmesg output for more information. I used the same drm.debug settings as before. PS: Is this fix going upstream some time? (In reply to Oli from comment #7) > (In reply to Ville Syrjala from comment #3) > > [ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz > > [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > > > Your cdclk is too low for that mode. I have a branch which has the required > > bits to adjust cdclk dynamically on SKL: > > git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2 > > > > Can you test with that branch? > > I did and it seems to works, at least the display didn't blank and xrandr > reports 60 Hz. Though, I have no way to tell if this is really the case, > because my display won't show this information. > > See the attached dmesg output for more information. I used the same > drm.debug settings as before. [ 9.195675] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz [ 9.195677] [drm:intel_update_max_cdclk] Max CD clock rate: 675000 kHz [ 9.195678] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz [ 70.790172] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 [ 70.790188] [drm:intel_modeset_checks] New cdclk calculated to be atomic 540000, actual 540000 [ 71.866294] [drm:skl_set_cdclk] Changing CDCLK to 540000 kHz (VCO 8100000 kHz) [ 71.872408] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz So everything is looking good. > > PS: Is this fix going upstream some time? It's being reviewed now, so should land soonish, I hope. (In reply to Ville Syrjala from comment #8) > (In reply to Oli from comment #7) > > (In reply to Ville Syrjala from comment #3) > > > [ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz > > > [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > > > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > > > > > Your cdclk is too low for that mode. I have a branch which has the required > > > bits to adjust cdclk dynamically on SKL: > > > git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2 > > > > > > Can you test with that branch? > > > > I did and it seems to works, at least the display didn't blank and xrandr > > reports 60 Hz. Though, I have no way to tell if this is really the case, > > because my display won't show this information. > > > > See the attached dmesg output for more information. I used the same > > drm.debug settings as before. > > > [ 9.195675] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, > VCO: 8100000 kHz, ref: 24000 kHz > [ 9.195677] [drm:intel_update_max_cdclk] Max CD clock rate: 675000 kHz > [ 9.195678] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz > [ 70.790172] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > [ 70.790188] [drm:intel_modeset_checks] New cdclk calculated to be atomic > 540000, actual 540000 > [ 71.866294] [drm:skl_set_cdclk] Changing CDCLK to 540000 kHz (VCO 8100000 > kHz) > [ 71.872408] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz, > VCO: 8100000 kHz, ref: 24000 kHz > > So everything is looking good. > > > > > PS: Is this fix going upstream some time? > > It's being reviewed now, so should land soonish, I hope. This has not really something to do with the bug, but how are these numbers to interpret? I mean, shouldn't there be something like a '60' somewhere? (In reply to Oli from comment #9) > (In reply to Ville Syrjala from comment #8) > > (In reply to Oli from comment #7) > > > (In reply to Ville Syrjala from comment #3) > > > > [ 12.914535] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz > > > > [ 91.861529] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > > > > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > > > > > > > Your cdclk is too low for that mode. I have a branch which has the required > > > > bits to adjust cdclk dynamically on SKL: > > > > git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2 > > > > > > > > Can you test with that branch? > > > > > > I did and it seems to works, at least the display didn't blank and xrandr > > > reports 60 Hz. Though, I have no way to tell if this is really the case, > > > because my display won't show this information. > > > > > > See the attached dmesg output for more information. I used the same > > > drm.debug settings as before. > > > > > > [ 9.195675] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, > > VCO: 8100000 kHz, ref: 24000 kHz > > [ 9.195677] [drm:intel_update_max_cdclk] Max CD clock rate: 675000 kHz > > [ 9.195678] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz > > [ 70.790172] [drm:intel_dump_crtc_timings] crtc timings: 533280 3840 3848 > > 3992 4000 2160 2214 2219 2222, type: 0x0 flags: 0x9 > > [ 70.790188] [drm:intel_modeset_checks] New cdclk calculated to be atomic > > 540000, actual 540000 > > [ 71.866294] [drm:skl_set_cdclk] Changing CDCLK to 540000 kHz (VCO 8100000 > > kHz) > > [ 71.872408] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz, > > VCO: 8100000 kHz, ref: 24000 kHz > > > > So everything is looking good. > > > > > > > > PS: Is this fix going upstream some time? > > > > It's being reviewed now, so should land soonish, I hope. > > This has not really something to do with the bug, but how are these numbers > to interpret? I mean, shouldn't there be something like a '60' somewhere? For the refresh rate? That'd be 'dotclock/htotal/vtotal' so in this case 533280*1000/4000/2222 = 60. Any progress on this one? An ETA when it will be merged into upstream? (In reply to Oli from comment #11) > Any progress on this one? An ETA when it will be merged into upstream? We seem to have pushed this a while back http://mid.gmane.org/20160523182136.GY4329@intel.com So it's all in drm-intel-nightly branch of http://cgit.freedesktop.org/drm-intel, headed to v4.8. Thanks for the report, closing. Please reopen if the problem persists with those. |
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