After drm commit 71adbfc874517efbba8b9f7c3f90baad0d7fb707 nouveau no longer works on my nv25, even with the fix in commit 5f15f317fb304f6a2321c033d401f603b365f2d0 it still doesn't work. Commenting out: NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); makes it work. 03:00.0 VGA Compatible controller [0300]: nVidia Corporation NV25 [GeForce4 Ti 4400] [10de:0251] (rev a2)
Does changing NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); to NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffffeff); make it work?
(In reply to comment #1) > Does changing NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); to > NV_WRITE(NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffffeff); make it work? > Nope, still the same problem.
Any change by doing either or both of these blocks of changes? diff --git a/shared-core/nv04_mc.c b/shared-core/nv04_mc.c index 766f3a3..43131f1 100644 --- a/shared-core/nv04_mc.c +++ b/shared-core/nv04_mc.c @@ -12,6 +12,10 @@ nv04_mc_init(struct drm_device *dev) saved_pci_nv_1 = NV_READ(NV04_PBUS_PCI_NV_1); saved_pci_nv_19 = NV_READ(NV04_PBUS_PCI_NV_19); + NV_WRITE(0x108c, 0x51); + NV_WRITE(0x1830, 0); + NV_WRITE(0x180c, 0xf800); + /* clear busmaster bit */ NV_WRITE(NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~(0x00000001 << 2)); /* clear SBA and AGP bits */ @@ -20,6 +24,8 @@ nv04_mc_init(struct drm_device *dev) /* Power up everything, resetting each individual unit will * be done later if needed. */ + NV_WRITE(NV03_PMC_ENABLE, 0xFFFF0FFF); + udelay(400); NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF); /* and restore (gives effect of resetting AGP) */
Created attachment 15020 [details] [review] Move AGP reset, and cycle PGRAPH Can you check it still works in this form please
Also worth testing with the udelay replaced with a read of PMC_ENABLE
Still works, also works without the udelay and with udelay replaced with a PMC_ENABLE read.
Pushed
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