Attachment 119338 Details for Bug 92738 – winsys/radeon: Use CPU page size instead of hardcoding 4096

[patch] winsys/radeon: Use CPU page size instead of hardcoding 4096

winsys-radeon-cpu-page-size.diff (text/plain), 3.87 KB, created by Michel Dänzer on 2015-11-02 09:55:42 UTC

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Creator: Michel Dänzer

Created: 2015-11-02 09:55:42 UTC

Size: 3.87 KB

patch

obsolete

>commit 8317ba8f08eb54de2990f881fc25df355dfe0e8b
>Author: Michel DÃ¤nzer <michel.daenzer@amd.com>
>Date:   Thu Aug 21 18:30:44 2014 +0900
>
>    winsys/radeon: Use CPU page size instead of hardcoding 4096
>
>diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>index 2878c8f..7507ba4 100644
>--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>@@ -76,6 +76,9 @@ struct radeon_bomgr {
>     bool va;
>     uint64_t va_offset;
>     struct list_head va_holes;
>+
>+    /* CPU page size, used for aligning BO sizes */
>+    long cpu_page_size;
> };
> 
> static inline struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
>@@ -188,8 +191,8 @@ static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, ui
>     struct radeon_bo_va_hole *hole, *n;
>     uint64_t offset = 0, waste = 0;
> 
>-    alignment = MAX2(alignment, 4096);
>-    size = align(size, 4096);
>+    alignment = MAX2(alignment, mgr->cpu_page_size);
>+    size = align(size, mgr->cpu_page_size);
> 
>     pipe_mutex_lock(mgr->bo_va_mutex);
>     /* first look for a hole */
>@@ -246,7 +249,7 @@ static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t
> {
>     struct radeon_bo_va_hole *hole;
> 
>-    size = align(size, 4096);
>+    size = align(size, mgr->cpu_page_size);
> 
>     pipe_mutex_lock(mgr->bo_va_mutex);
>     if ((va + size) == mgr->va_offset) {
>@@ -357,9 +360,9 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
>     pipe_mutex_destroy(bo->map_mutex);
> 
>     if (bo->initial_domain & RADEON_DOMAIN_VRAM)
>-        bo->rws->allocated_vram -= align(bo->base.size, 4096);
>+        bo->rws->allocated_vram -= align(bo->base.size, mgr->cpu_page_size);
>     else if (bo->initial_domain & RADEON_DOMAIN_GTT)
>-        bo->rws->allocated_gtt -= align(bo->base.size, 4096);
>+        bo->rws->allocated_gtt -= align(bo->base.size, mgr->cpu_page_size);
>     FREE(bo);
> }
> 
>@@ -644,9 +647,9 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
>     }
> 
>     if (rdesc->initial_domains & RADEON_DOMAIN_VRAM)
>-        rws->allocated_vram += align(size, 4096);
>+        rws->allocated_vram += align(size, mgr->cpu_page_size);
>     else if (rdesc->initial_domains & RADEON_DOMAIN_GTT)
>-        rws->allocated_gtt += align(size, 4096);
>+        rws->allocated_gtt += align(size, mgr->cpu_page_size);
> 
>     return &bo->base;
> }
>@@ -720,6 +723,8 @@ struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
>     mgr->va_offset = rws->va_start;
>     list_inithead(&mgr->va_holes);
> 
>+    mgr->cpu_page_size = sysconf(_SC_PAGESIZE);
>+
>     return &mgr->base;
> }
> 
>@@ -882,7 +887,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
>      * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
>      * like constant/uniform buffers, can benefit from better and more reuse.
>      */
>-    size = align(size, 4096);
>+    size = align(size, mgr->cpu_page_size);
> 
>     /* Only set one usage bit each for domains and flags, or the cache manager
>      * might consider different sets of domains / flags compatible
>@@ -993,7 +998,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
>         pipe_mutex_unlock(mgr->bo_handles_mutex);
>     }
> 
>-    ws->allocated_gtt += align(bo->base.size, 4096);
>+    ws->allocated_gtt += align(bo->base.size, mgr->cpu_page_size);
> 
>     return (struct pb_buffer*)bo;
> }
>@@ -1130,9 +1135,9 @@ done:
>     bo->initial_domain = radeon_bo_get_initial_domain((void*)bo);
> 
>     if (bo->initial_domain & RADEON_DOMAIN_VRAM)
>-        ws->allocated_vram += align(bo->base.size, 4096);
>+        ws->allocated_vram += align(bo->base.size, mgr->cpu_page_size);
>     else if (bo->initial_domain & RADEON_DOMAIN_GTT)
>-        ws->allocated_gtt += align(bo->base.size, 4096);
>+        ws->allocated_gtt += align(bo->base.size, mgr->cpu_page_size);
> 
>     return (struct pb_buffer*)bo;
>

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