Bug 92738 - Randon R7 240 doesn't work on 16KiB page size platform
Summary: Randon R7 240 doesn't work on 16KiB page size platform
Status: RESOLVED FIXED
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/Gallium/r600 (show other bugs)
Version: git
Hardware: Other Linux (All)
: medium normal
Assignee: Default DRI bug account
QA Contact: Default DRI bug account
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2015-10-30 16:12 UTC by Heiher
Modified: 2015-11-20 03:21 UTC (History)
0 users

See Also:
i915 platform:
i915 features:


Attachments
winsys/radeon: Use CPU page size instead of hardcoding 4096 (3.87 KB, patch)
2015-11-02 09:55 UTC, Michel Dänzer
Details | Splinter Review
winsys/radeon: Use CPU page size instead of hardcoding 4096 (3.94 KB, patch)
2015-11-02 10:00 UTC, Michel Dänzer
Details | Splinter Review

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Description Heiher 2015-10-30 16:12:04 UTC
The radeon gpu that with VM supported doesn't work on >= 4KiB page size platforms. (e.g. Loongson 16k)

It seems we assume that the maximum page size is 4096 in radeon_bomgr_find_va and radeon_bomgr_free_va. I think dynmamic get system page size here would better.
Comment 1 Alex Deucher 2015-10-30 17:22:22 UTC
GPU pages are 4k.  These functions are dealing with the GPU's virtual address space, not the CPU's.  What sort of problem are you seeing?
Comment 2 Michel Dänzer 2015-11-02 09:55:42 UTC
Created attachment 119338 [details] [review]
winsys/radeon: Use CPU page size instead of hardcoding 4096

Does this patch fix it?
Comment 3 Michel Dänzer 2015-11-02 10:00:57 UTC
Created attachment 119339 [details] [review]
winsys/radeon: Use CPU page size instead of hardcoding 4096

Updated patch which leaves the 4K alignment for the VM range start address.
Comment 4 Heiher 2015-11-03 01:10:25 UTC
(In reply to Alex Deucher from comment #1)
> GPU pages are 4k.  These functions are dealing with the GPU's virtual
> address space, not the CPU's.  What sort of problem are you seeing?

dmesg outputs when X server starting:
[ 1071.083005] radeon 0000:02:00.0: bo 98000001e5d76000 va 0x0000000802 conflict with (bo 98000001e5d76800 0x0000000800 0x0000000803)
[ 1071.095425] radeon 0000:02:00.0: bo 98000001e5d76000 va 0x0000000802 conflict with (bo 98000001e5d76800 0x0000000800 0x0000000803)
[ 1073.201289] radeon 0000:02:00.0: bo 98000001e5dfac00 va 0x0000000802 conflict with (bo 98000001e5dfbc00 0x0000000800 0x0000000803)
[ 1073.213795] radeon 0000:02:00.0: bo 98000001e5dfac00 va 0x0000000802 conflict with (bo 98000001e5dfbc00 0x0000000800 0x0000000803)
[ 1074.413274] radeon 0000:02:00.0: bo 98000001e5d76800 va 0x0000000802 conflict with (bo 98000001e5d74000 0x0000000800 0x0000000803)
[ 1074.425699] radeon 0000:02:00.0: bo 98000001e5d76800 va 0x0000000802 conflict with (bo 98000001e5d74000 0x0000000800 0x0000000803)
[ 1075.634164] radeon 0000:02:00.0: bo 98000001fad14c00 va 0x0000000802 conflict with (bo 98000001fad16c00 0x0000000800 0x0000000803)
[ 1075.646623] radeon 0000:02:00.0: bo 98000001fad14c00 va 0x0000000802 conflict with (bo 98000001fad16c00 0x0000000800 0x0000000803)
[ 1076.867784] radeon 0000:02:00.0: bo 98000001e5dfbc00 va 0x0000000802 conflict with (bo 98000001e5dfb800 0x0000000800 0x0000000803)
[ 1076.880201] radeon 0000:02:00.0: bo 98000001e5dfbc00 va 0x0000000802 conflict with (bo 98000001e5dfb800 0x0000000800 0x0000000803)
[ 1078.747714] radeon 0000:02:00.0: bo 98000001e5df9400 va 0x0000000802 conflict with (bo 98000001e5df8c00 0x0000000800 0x0000000803)
[ 1078.760208] radeon 0000:02:00.0: bo 98000001e5df9400 va 0x0000000802 conflict with (bo 98000001e5df8c00 0x0000000800 0x0000000803)
Comment 5 Heiher 2015-11-03 01:33:04 UTC
(In reply to Michel Dänzer from comment #3)
> Created attachment 119339 [details] [review] [review]
> winsys/radeon: Use CPU page size instead of hardcoding 4096
> 
> Updated patch which leaves the 4K alignment for the VM range start address.

I have backport this patch to mesa 10.4.0 and fixed. but i'm not sure the changes in radeon_winsys_bo_from_ptr isn't ok? because buffer_from_ptr missing in mesa 10.4.0. Thanks!
Comment 6 Michel Dänzer 2015-11-20 03:21:12 UTC
Module: Mesa
Branch: master
Commit: 24abbaff9ad177624c2b4906c7d94f5d91ac3cc0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=24abbaff9ad177624c2b4906c7d94f5d91ac3cc0

Author: Michel Dänzer <michel.daenzer@amd.com>
Date:   Thu Aug 21 18:30:44 2014 +0900

winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3


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