Attachment 120329 Details for Bug 93244 – [Patch] Preserving PCI Burst Write Wait State Select Bit

[Patch] Preserving PCI Burst Write Wait State Select Bit

0008-Preserving-PCI-Burst-Write-Wait-State-Select-Bit.-In.patch (text/plain), 3.33 KB, created by Kevin Brace on 2015-12-04 07:17:43 UTC

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Creator: Kevin Brace

Created: 2015-12-04 07:17:43 UTC

Size: 3.33 KB

patch

obsolete

>From a153b03b0506353e3695ddc36ec9c755961b893d Mon Sep 17 00:00:00 2001
>From: Kevin Brace <kevinbrace@gmx.com>
>Date: Mon, 30 Nov 2015 04:22:08 -0800
>Subject: [PATCH 08/10] Preserving PCI Burst Write Wait State Select Bit. In
> the process of trying to debug ACPI S3 State resume
> bug when an LVDS-based DFP is used, it was discovered
> that OpenChrome is tinkering with PCI Burst Write
> Wait State Select bit (0x3c5.0x1a[2]) on its own for
> no good reasons. Typically, the option to enable 1
> wait state PCI transaction in many VIA Technologies
> chipset-based computers is provided in the BIOS
> setup, therefore, it is prudent for OpenChrome not to
> tinker with this bit. Any code references that alter
> this bit were removed.
>
>---
> src/via_display.c |   16 ++++++++--------
> src/via_outputs.c |   19 ++++---------------
> 2 files changed, 12 insertions(+), 23 deletions(-)
>
>diff --git a/src/via_display.c b/src/via_display.c
>index ff51eb0..4514505 100644
>--- a/src/via_display.c
>+++ b/src/via_display.c
>@@ -366,10 +366,10 @@ ViaFirstCRTCSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode)
>         case VIA_VX900:
>             break;
>         default:
>-            ViaSeqMask(hwp, 0x16, 0x08, 0xBF);
>-            ViaSeqMask(hwp, 0x17, 0x1F, 0xFF);
>-            ViaSeqMask(hwp, 0x18, 0x4E, 0xFF);
>-            ViaSeqMask(hwp, 0x1A, 0x08, 0xFD);
>+            ViaSeqMask(hwp, 0x16, 0x08, 0xbf);
>+            ViaSeqMask(hwp, 0x17, 0x1f, 0xff);
>+            ViaSeqMask(hwp, 0x18, 0x4e, 0xff);
>+            ViaSeqMask(hwp, 0x1a, 0x08, 0xf9);
>             break;
>     }
> 
>@@ -636,10 +636,10 @@ ViaSecondCRTCSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode)
>         case VIA_VX900:
>             break;
>         default:
>-            ViaSeqMask(hwp, 0x16, 0x08, 0xBF);
>-            ViaSeqMask(hwp, 0x17, 0x1F, 0xFF);
>-            ViaSeqMask(hwp, 0x18, 0x4E, 0xFF);
>-            ViaSeqMask(hwp, 0x1A, 0x08, 0xFD);
>+            ViaSeqMask(hwp, 0x16, 0x08, 0xbf);
>+            ViaSeqMask(hwp, 0x17, 0x1f, 0xff);
>+            ViaSeqMask(hwp, 0x18, 0x4e, 0xff);
>+            ViaSeqMask(hwp, 0x1a, 0x08, 0xf9);
>             break;
>     }
> 
>diff --git a/src/via_outputs.c b/src/via_outputs.c
>index 0946f7f..f2fd428 100644
>--- a/src/via_outputs.c
>+++ b/src/via_outputs.c
>@@ -1405,8 +1405,8 @@ ViaModePrimaryLegacy(xf86CrtcPtr crtc, DisplayModePtr mode)
>     pBIOSInfo->Clock = ViaModeDotClockTranslate(pScrn, mode);
>     pBIOSInfo->ClockExternal = FALSE;
> 
>-    /* Enable MMIO & PCI burst (1 wait state) */
>-    ViaSeqMask(hwp, 0x1A, 0x06, 0x06);
>+/* Enable Extended Mode Memory Access. */
>+    ViaSeqMask(hwp, 0x1a, 0x08, 0x08);
> 
>     if (pBIOSInfo->analog->status == XF86OutputStatusConnected)
>         ViaCrtcMask(hwp, 0x36, 0x30, 0x30);
>@@ -1524,19 +1524,8 @@ ViaModeFirstCRTC(ScrnInfoPtr pScrn, DisplayModePtr mode)
>     pBIOSInfo->Clock = ViaModeDotClockTranslate(pScrn, mode);
>     pBIOSInfo->ClockExternal = FALSE;
> 
>-    /* Enable MMIO & PCI burst (1 wait state) */
>-    switch (pVia->Chipset) {
>-        case VIA_CLE266:
>-        case VIA_KM400:
>-        case VIA_K8M800:
>-        case VIA_PM800:
>-        case VIA_P4M800PRO:
>-            ViaSeqMask(hwp, 0x1A, 0x06, 0x06);
>-            break;
>-        default:
>-            ViaSeqMask(hwp, 0x1A, 0x0C, 0x0C);
>-            break;
>-    }
>+/* Enable Extended Mode Memory Access. */
>+    ViaSeqMask(hwp, 0x1a, 0x08, 0x08);
> 
>     ViaSetPrimaryFIFO(pScrn, mode);
> 
>-- 
>1.7.9.5
>

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