Attachment 12967 Details for Bug 13434 – radeontool regmatch '*' with fglrx driver

radeontool regmatch '*' with fglrx driver

output.radeontool_regmatch.fglrx.txt (text/plain), 14.71 KB, created by Eric Callier on 2007-12-05 14:53:04 UTC

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Description:

Filename:

MIME Type:

Creator: Eric Callier

Created: 2007-12-05 14:53:04 UTC

Size: 14.71 KB

patch

obsolete

>ADAPTER_ID (0f2c)	0x00000000
>AGP_BASE (0170)	0x00000000
>AGP_CNTL (0174)	0x00000000
>AGP_COMMAND (0f60)	0x04060101
>AGP_STATUS (0f5c)	0x00000000
>AMCGPIO_A_REG (01a0)	0x04060101
>AMCGPIO_EN_REG (01a8)	0x00000010
>AMCGPIO_MASK (0194)	0x00000000
>AMCGPIO_Y_REG (01a4)	0x332a5000
>ATTRDR (03c1)	0x00040601
>ATTRDW (03c0)	0x04060101
>ATTRX (03c0)	0x04060101
>AUX_SC_CNTL (1660)	0xffffffff
>AUX1_SC_BOTTOM (1670)	0xffffffff
>AUX1_SC_LEFT (1664)	0xffffffff
>AUX1_SC_RIGHT (1668)	0xffffffff
>AUX1_SC_TOP (166c)	0xffffffff
>AUX2_SC_BOTTOM (1680)	0xffffffff
>AUX2_SC_LEFT (1674)	0xffffffff
>AUX2_SC_RIGHT (1678)	0xffffffff
>AUX2_SC_TOP (167c)	0xffffffff
>AUX3_SC_BOTTOM (1690)	0xffffffff
>AUX3_SC_LEFT (1684)	0xffffffff
>AUX3_SC_RIGHT (1688)	0xffffffff
>AUX3_SC_TOP (168c)	0xffffffff
>AUX_WINDOW_HORZ_CNTL (02d8)	0x00000000
>AUX_WINDOW_VERT_CNTL (02dc)	0x00000000
>BASE_CODE (0f0b)	0x00000000
>BIOS_0_SCRATCH (0010)	0x00000000
>BIOS_1_SCRATCH (0014)	0x00000000
>BIOS_2_SCRATCH (0018)	0x00000000
>BIOS_3_SCRATCH (001c)	0x00000000
>BIOS_4_SCRATCH (0020)	0x04060101
>BIOS_5_SCRATCH (0024)	0x332a5000
>BIOS_6_SCRATCH (0028)	0x00000010
>BIOS_7_SCRATCH (002c)	0x00000000
>BIOS_ROM (0f30)	0x00000000
>BIST (0f0f)	0x00000000
>BUS_CNTL (0030)	0x00000000
>BUS_CNTL1 (0034)	0x00000000
>CACHE_CNTL (1724)	0xffffffff
>CACHE_LINE (0f0c)	0x00000000
>CAP0_TRIG_CNTL (0950)	0x00000000
>CAP1_TRIG_CNTL (09c0)	0x04060101
>CAPABILITIES_ID (0f50)	0x00000000
>CAPABILITIES_PTR (0f34)	0x00000000
>CLOCK_CNTL_DATA (000c)	0x00000000
>CLOCK_CNTL_INDEX (0008)	0x00000010
>CLR_CMP_CLR_3D (1a24)	0xffffffff
>CLR_CMP_CLR_DST (15c8)	0xffffffff
>CLR_CMP_CLR_SRC (15c4)	0xffffffff
>CLR_CMP_CNTL (15c0)	0xffffffff
>CLR_CMP_MASK (15cc)	0xffffffff
>CLR_CMP_MASK_3D (1a28)	0xffffffff
>COMMAND (0f04)	0x332a5000
>COMPOSITE_SHADOW_ID (1a0c)	0xffffffff
>CONFIG_APER_0_BASE (0100)	0x04060101
>CONFIG_APER_1_BASE (0104)	0x332a5000
>CONFIG_APER_SIZE (0108)	0x00000010
>CONFIG_BONDS (00e8)	0x00000010
>CONFIG_CNTL (00e0)	0x04060101
>CONFIG_MEMSIZE (00f8)	0x00000000
>CONFIG_MEMSIZE_EMBEDDED (0114)	0x00000000
>CONFIG_REG_1_BASE (010c)	0x00000000
>CONFIG_REG_APER_SIZE (0110)	0x00000000
>CONFIG_XSTRAP (00e4)	0x332a5000
>CONSTANT_COLOR_C (1d34)	0xffffffff
>CRC_CMDFIFO_ADDR (0740)	0x04060101
>CRC_CMDFIFO_DOUT (0744)	0x332a5000
>CRTC_CRNT_FRAME (0214)	0x00000000
>CRTC_DEBUG (021c)	0x00000000
>CRTC_EXT_CNTL (0054)	0x00000000
>CRTC_EXT_CNTL_DPMS_BYTE (0055)	0x00000000
>CRTC_GEN_CNTL (0050)	0x00000000
>CRTC2_GEN_CNTL (03f8)	0x00000000
>CRTC_GUI_TRIG_VLINE (0218)	0x00000000
>CRTC_H_SYNC_STRT_WID (0204)	0x332a5000
>CRTC2_H_SYNC_STRT_WID (0304)	0x332a5000
>CRTC_H_TOTAL_DISP (0200)	0x04060101
>CRTC2_H_TOTAL_DISP (0300)	0x04060101
>CRTC_OFFSET (0224)	0x332a5000
>CRTC2_OFFSET (0324)	0x332a5000
>CRTC_OFFSET_CNTL (0228)	0x00000010
>CRTC2_OFFSET_CNTL (0328)	0x00000010
>CRTC_PITCH (022c)	0x00000000
>CRTC2_PITCH (032c)	0x00000000
>CRTC_STATUS (005c)	0x00000000
>CRTC_V_SYNC_STRT_WID (020c)	0x00000000
>CRTC2_V_SYNC_STRT_WID (030c)	0x00000000
>CRTC_V_TOTAL_DISP (0208)	0x00000010
>CRTC2_V_TOTAL_DISP (0308)	0x00000010
>CRTC_VLINE_CRNT_VLINE (0210)	0x00000000
>CRTC2_CRNT_FRAME (0314)	0x00000000
>CRTC2_DEBUG (031c)	0x00000000
>CRTC2_GUI_TRIG_VLINE (0318)	0x00000000
>CRTC2_STATUS (03fc)	0x00000000
>CRTC2_VLINE_CRNT_VLINE (0310)	0x00000000
>CRTC8_DATA (03d5)	0x00000000
>CRTC8_IDX (03d4)	0x00000000
>CUR_CLR0 (026c)	0x00000000
>CUR_CLR1 (0270)	0x00000000
>CUR_HORZ_VERT_OFF (0268)	0x00000010
>CUR_HORZ_VERT_POSN (0264)	0x332a5000
>CUR_OFFSET (0260)	0x04060101
>CUR2_CLR0 (036c)	0x00000000
>CUR2_CLR1 (0370)	0x00000000
>CUR2_HORZ_VERT_OFF (0368)	0x00000010
>CUR2_HORZ_VERT_POSN (0364)	0x332a5000
>CUR2_OFFSET (0360)	0x04060101
>DAC_CNTL (0058)	0x00000000
>DAC_CNTL2 (007c)	0x00000000
>DAC_EXT_CNTL (0280)	0x04060101
>DAC_MACRO_CNTL (0d04)	0x332a5000
>TV_DAC_CNTL (088c)	0x00000000
>DISP_OUTPUT_CNTL (0d64)	0x332a5000
>DAC_CRC_SIG (02cc)	0x00000000
>DAC_DATA (03c9)	0x00000000
>DAC_MASK (03c6)	0x0010332a
>DAC_R_INDEX (03c7)	0x00001033
>DAC_W_INDEX (03c8)	0x00000010
>DDA_CONFIG (02e0)	0x04060101
>DDA_ON_OFF (02e4)	0x332a5000
>DEFAULT_OFFSET (16e0)	0xffffffff
>DEFAULT_PITCH (16e4)	0xffffffff
>DEFAULT_SC_BOTTOM_RIGHT (16e8)	0xffffffff
>DESTINATION_3D_CLR_CMP_VAL (1820)	0xffffffff
>DESTINATION_3D_CLR_CMP_MSK (1824)	0xffffffff
>DEVICE_ID (0f02)	0x50000406
>DISP_MISC_CNTL (0d00)	0x04060101
>DP_BRUSH_BKGD_CLR (1478)	0xffffffff
>DP_BRUSH_FRGD_CLR (147c)	0xffffffff
>DP_CNTL (16c0)	0xffffffff
>DP_CNTL_XDIR_YDIR_YMAJOR (16d0)	0xffffffff
>DP_DATATYPE (16c4)	0xffffffff
>DP_GUI_MASTER_CNTL (146c)	0xffffffff
>DP_GUI_MASTER_CNTL_C (1c84)	0xffffffff
>DP_MIX (16c8)	0xffffffff
>DP_SRC_BKGD_CLR (15dc)	0xffffffff
>DP_SRC_FRGD_CLR (15d8)	0xffffffff
>DP_WRITE_MASK (16cc)	0xffffffff
>DST_BRES_DEC (1630)	0xffffffff
>DST_BRES_ERR (1628)	0xffffffff
>DST_BRES_INC (162c)	0xffffffff
>DST_BRES_LNTH (1634)	0xffffffff
>DST_BRES_LNTH_SUB (1638)	0xffffffff
>DST_HEIGHT (1410)	0xffffffff
>DST_HEIGHT_WIDTH (143c)	0xffffffff
>DST_HEIGHT_WIDTH_8 (158c)	0xffffffff
>DST_HEIGHT_WIDTH_BW (15b4)	0xffffffff
>DST_HEIGHT_Y (15a0)	0xffffffff
>DST_LINE_START (1600)	0xffffffff
>DST_LINE_END (1604)	0xffffffff
>DST_LINE_PATCOUNT (1608)	0xffffffff
>DST_OFFSET (1404)	0xffffffff
>DST_PITCH (1408)	0xffffffff
>DST_PITCH_OFFSET (142c)	0xffffffff
>DST_PITCH_OFFSET_C (1c80)	0xffffffff
>DST_WIDTH (140c)	0xffffffff
>DST_WIDTH_HEIGHT (1598)	0xffffffff
>DST_WIDTH_X (1588)	0xffffffff
>DST_WIDTH_X_INCY (159c)	0xffffffff
>DST_X (141c)	0xffffffff
>DST_X_SUB (15a4)	0xffffffff
>DST_X_Y (1594)	0xffffffff
>DST_Y (1420)	0xffffffff
>DST_Y_SUB (15a8)	0xffffffff
>DST_Y_X (1438)	0xffffffff
>FLUSH_1 (1704)	0xffffffff
>FLUSH_2 (1708)	0xffffffff
>FLUSH_3 (170c)	0xffffffff
>FLUSH_4 (1710)	0xffffffff
>FLUSH_5 (1714)	0xffffffff
>FLUSH_6 (1718)	0xffffffff
>FLUSH_7 (171c)	0xffffffff
>FOG_3D_TABLE_START (1810)	0xffffffff
>FOG_3D_TABLE_END (1814)	0xffffffff
>FOG_3D_TABLE_DENSITY (181c)	0xffffffff
>FOG_TABLE_INDEX (1a14)	0xffffffff
>FOG_TABLE_DATA (1a18)	0xffffffff
>FP_CRTC_H_TOTAL_DISP (0250)	0x00000000
>FP_CRTC_V_TOTAL_DISP (0254)	0x00000000
>FP_CRTC2_H_TOTAL_DISP (0350)	0x00000000
>FP_CRTC2_V_TOTAL_DISP (0354)	0x00000000
>FP_GEN_CNTL (0284)	0x332a5000
>FP2_GEN_CNTL (0288)	0x00000010
>FP_H_SYNC_STRT_WID (02c4)	0x332a5000
>FP_H2_SYNC_STRT_WID (03c4)	0x332a5000
>FP_HORZ_STRETCH (028c)	0x00000000
>FP_HORZ2_STRETCH (038c)	0x00000000
>FP_V_SYNC_STRT_WID (02c8)	0x00000010
>FP_VERT_STRETCH (0290)	0x00000000
>FP_V2_SYNC_STRT_WID (03c8)	0x00000010
>FP_VERT2_STRETCH (0390)	0x00000000
>FW_CNTL (0118)	0x00000000
>FW_STATUS (011c)	0x00000000
>GEN_INT_CNTL (0040)	0x04060101
>GEN_INT_STATUS (0044)	0x332a5000
>GENENB (03c3)	0x2a500004
>GENFC_RD (03ca)	0x00000000
>GENFC_WT (03da)	0x00000000
>GENMO_RD (03cc)	0x00000000
>GENMO_WT (03c2)	0x50000406
>GENS0 (03c2)	0x50000406
>GENS1 (03da)	0x00000000
>GPIO_MONID (0068)	0x00000010
>GPIO_MONIDB (006c)	0x00000000
>GPIO_CRT2_DDC (006c)	0x00000000
>GPIO_DVI_DDC (0064)	0x332a5000
>GPIO_VGA_DDC (0060)	0x04060101
>GRPH8_DATA (03cf)	0x00000000
>GRPH8_IDX (03ce)	0x00000000
>GUI_DEBUG0 (16a0)	0xffffffff
>GUI_DEBUG1 (16a4)	0xffffffff
>GUI_DEBUG2 (16a8)	0xffffffff
>GUI_DEBUG3 (16ac)	0xffffffff
>GUI_DEBUG4 (16b0)	0xffffffff
>GUI_DEBUG5 (16b4)	0xffffffff
>GUI_DEBUG6 (16b8)	0xffffffff
>GUI_SCRATCH_REG0 (15e0)	0xffffffff
>GUI_SCRATCH_REG1 (15e4)	0xffffffff
>GUI_SCRATCH_REG2 (15e8)	0xffffffff
>GUI_SCRATCH_REG3 (15ec)	0xffffffff
>GUI_SCRATCH_REG4 (15f0)	0xffffffff
>GUI_SCRATCH_REG5 (15f4)	0xffffffff
>HEADER (0f0e)	0x00000000
>HOST_DATA0 (17c0)	0xffffffff
>HOST_DATA1 (17c4)	0xffffffff
>HOST_DATA2 (17c8)	0xffffffff
>HOST_DATA3 (17cc)	0xffffffff
>HOST_DATA4 (17d0)	0xffffffff
>HOST_DATA5 (17d4)	0xffffffff
>HOST_DATA6 (17d8)	0xffffffff
>HOST_DATA7 (17dc)	0xffffffff
>HOST_DATA_LAST (17e0)	0xffffffff
>HOST_PATH_CNTL (0130)	0x00000000
>HW_DEBUG (0128)	0x00000010
>HW_DEBUG2 (011c)	0x00000000
>I2C_CNTL_1 (0094)	0x00000000
>DVI_I2C_CNTL_1 (02e4)	0x332a5000
>INTERRUPT_LINE (0f3c)	0x00000000
>INTERRUPT_PIN (0f3d)	0x01000000
>IO_BASE (0f14)	0x00000000
>LATENCY (0f0d)	0x00000000
>LEAD_BRES_DEC (1608)	0xffffffff
>LEAD_BRES_LNTH (161c)	0xffffffff
>LEAD_BRES_LNTH_SUB (1624)	0xffffffff
>LVDS_GEN_CNTL (02d0)	0x00000000
>MAX_LATENCY (0f3f)	0x06010100
>MC_AGP_LOCATION (014c)	0x00000000
>MC_FB_LOCATION (0148)	0x00000010
>MC_STATUS (0150)	0x00000000
>MDGPIO_A_REG (01ac)	0x00000000
>MDGPIO_EN_REG (01b0)	0x00000000
>MDGPIO_MASK (0198)	0x00000000
>MDGPIO_Y_REG (01b4)	0x00000000
>MEM_ADDR_CONFIG (0148)	0x00000010
>MEM_BASE (0f10)	0x00000000
>MEM_CNTL (0140)	0x04060101
>MEM_INIT_LAT_TIMER (0154)	0x00000000
>MEM_INTF_CNTL (014c)	0x00000000
>MEM_SDRAM_MODE_REG (0158)	0x00000000
>MEM_STR_CNTL (0150)	0x00000000
>MEM_VGA_RP_SEL (003c)	0x00000000
>MEM_VGA_WP_SEL (0038)	0x00000000
>MIN_GRANT (0f3e)	0x01010000
>MM_DATA (0004)	0x332a5000
>MM_INDEX (0000)	0x04060101
>MPP_TB_CONFIG (01c0)	0x04060101
>MPP_GP_CONFIG (01c8)	0x00000010
>N_VIF_COUNT (0248)	0x00000010
>OV0_SCALE_CNTL (0420)	0x04060101
>OVR_CLR (0230)	0x00000000
>OVR_WID_LEFT_RIGHT (0234)	0x00000000
>OVR_WID_TOP_BOTTOM (0238)	0x00000000
>OV0_Y_X_START (0400)	0x04060101
>OV0_Y_X_END (0404)	0x332a5000
>OV0_EXCLUSIVE_HORZ (0408)	0x00000010
>OV0_EXCLUSIVE_VERT (040c)	0x00000000
>OV0_REG_LOAD_CNTL (0410)	0x00000000
>OV0_SCALE_CNTL (0420)	0x04060101
>OV0_V_INC (0424)	0x332a5000
>OV0_P1_V_ACCUM_INIT (0428)	0x00000010
>OV0_P23_V_ACCUM_INIT (042c)	0x00000000
>OV0_P1_BLANK_LINES_AT_TOP (0430)	0x00000000
>OV0_P23_BLANK_LINES_AT_TOP (0434)	0x00000000
>OV0_VID_BUF0_BASE_ADRS (0440)	0x04060101
>OV0_VID_BUF1_BASE_ADRS (0444)	0x332a5000
>OV0_VID_BUF2_BASE_ADRS (0448)	0x00000010
>OV0_VID_BUF3_BASE_ADRS (044c)	0x00000000
>OV0_VID_BUF4_BASE_ADRS (0450)	0x00000000
>OV0_VID_BUF5_BASE_ADRS (0454)	0x00000000
>OV0_VID_BUF_PITCH0_VALUE (0460)	0x04060101
>OV0_VID_BUF_PITCH1_VALUE (0464)	0x332a5000
>OV0_AUTO_FLIP_CNTL (0470)	0x00000000
>OV0_DEINTERLACE_PATTERN (0474)	0x00000000
>OV0_H_INC (0480)	0x04060101
>OV0_STEP_BY (0484)	0x332a5000
>OV0_P1_H_ACCUM_INIT (0488)	0x00000010
>OV0_P23_H_ACCUM_INIT (048c)	0x00000000
>OV0_P1_X_START_END (0494)	0x00000000
>OV0_P2_X_START_END (0498)	0x00000000
>OV0_P3_X_START_END (049c)	0x00000000
>OV0_FILTER_CNTL (04a0)	0x04060101
>OV0_FOUR_TAP_COEF_0 (04b0)	0x00000000
>OV0_FOUR_TAP_COEF_1 (04b4)	0x00000000
>OV0_FOUR_TAP_COEF_2 (04b8)	0x00000000
>OV0_FOUR_TAP_COEF_3 (04bc)	0x00000000
>OV0_FOUR_TAP_COEF_4 (04c0)	0x04060101
>OV0_COLOUR_CNTL (04e0)	0x04060101
>OV0_VIDEO_KEY_CLR (04e4)	0x332a5000
>OV0_VIDEO_KEY_MSK (04e8)	0x00000010
>OV0_GRAPHICS_KEY_CLR (04ec)	0x00000000
>OV0_GRAPHICS_KEY_MSK (04f0)	0x00000000
>OV0_KEY_CNTL (04f4)	0x00000000
>OV0_TEST (04f8)	0x00000000
>PALETTE_DATA (00b4)	0x00000000
>PALETTE_30_DATA (00b8)	0x00000000
>PALETTE_INDEX (00b0)	0x00000000
>PCI_GART_PAGE (017c)	0x00000000
>PIXCLKS_CNTL (002d)	0x00000000
>PLANE_3D_MASK_C (1d44)	0xffffffff
>PMI_CAP_ID (0f5c)	0x00000000
>PMI_DATA (0f63)	0x2a500004
>PMI_NXT_CAP_PTR (0f5d)	0x01000000
>PMI_PMC_REG (0f5e)	0x01010000
>PMI_PMCSR_REG (0f60)	0x04060101
>PMI_REGISTER (0f5c)	0x00000000
>PWR_MNGMT_CNTL_STATUS (0f60)	0x04060101
>DSTCACHE_MODE (1710)	0xffffffff
>RBBM_SOFT_RESET (00f0)	0x00000000
>RBBM_STATUS (0e40)	0x04060101
>RB2D_DSTCACHE_CTLSTAT (342c)	0xffffffff
>RB2D_DSTCACHE_MODE (3428)	0xffffffff
>REG_BASE (0f18)	0x00000000
>REGPROG_INF (0f09)	0x00000000
>REVISION_ID (0f08)	0x00000010
>SC_BOTTOM (164c)	0xffffffff
>SC_BOTTOM_RIGHT (16f0)	0xffffffff
>SC_BOTTOM_RIGHT_C (1c8c)	0xffffffff
>SC_LEFT (1640)	0xffffffff
>SC_RIGHT (1644)	0xffffffff
>SC_TOP (1648)	0xffffffff
>SC_TOP_LEFT (16ec)	0xffffffff
>SC_TOP_LEFT_C (1c88)	0xffffffff
>SDRAM_MODE_REG (0158)	0x00000000
>SEQ8_DATA (03c5)	0x10332a50
>SEQ8_IDX (03c4)	0x332a5000
>SNAPSHOT_F_COUNT (0244)	0x332a5000
>SNAPSHOT_VH_COUNTS (0240)	0x04060101
>SNAPSHOT_VIF_COUNT (024c)	0x00000000
>SRC_OFFSET (15ac)	0xffffffff
>SRC_PITCH (15b0)	0xffffffff
>SRC_PITCH_OFFSET (1428)	0xffffffff
>SRC_SC_BOTTOM (165c)	0xffffffff
>SRC_SC_BOTTOM_RIGHT (16f4)	0xffffffff
>SRC_SC_RIGHT (1654)	0xffffffff
>SRC_X (1414)	0xffffffff
>SRC_X_Y (1590)	0xffffffff
>SRC_Y (1418)	0xffffffff
>SRC_Y_X (1434)	0xffffffff
>STATUS (0f06)	0x0010332a
>SUBPIC_CNTL (0540)	0x04060101
>SUB_CLASS (0f0a)	0x00000000
>SURFACE_CNTL (0b00)	0x04060101
>SURFACE0_INFO (0b0c)	0x00000000
>SURFACE0_LOWER_BOUND (0b04)	0x332a5000
>SURFACE0_UPPER_BOUND (0b08)	0x00000010
>SURFACE1_INFO (0b1c)	0x00000000
>SURFACE1_LOWER_BOUND (0b14)	0x00000000
>SURFACE1_UPPER_BOUND (0b18)	0x00000000
>SURFACE2_INFO (0b2c)	0x00000000
>SURFACE2_LOWER_BOUND (0b24)	0x332a5000
>SURFACE2_UPPER_BOUND (0b28)	0x00000010
>SURFACE3_INFO (0b3c)	0x00000000
>SURFACE3_LOWER_BOUND (0b34)	0x00000000
>SURFACE3_UPPER_BOUND (0b38)	0x00000000
>SURFACE4_INFO (0b4c)	0x00000000
>SURFACE4_LOWER_BOUND (0b44)	0x332a5000
>SURFACE4_UPPER_BOUND (0b48)	0x00000010
>SURFACE5_INFO (0b5c)	0x00000000
>SURFACE5_LOWER_BOUND (0b54)	0x00000000
>SURFACE5_UPPER_BOUND (0b58)	0x00000000
>SURFACE6_INFO (0b6c)	0x00000000
>SURFACE6_LOWER_BOUND (0b64)	0x332a5000
>SURFACE6_UPPER_BOUND (0b68)	0x00000010
>SURFACE7_INFO (0b7c)	0x00000000
>SURFACE7_LOWER_BOUND (0b74)	0x00000000
>SURFACE7_UPPER_BOUND (0b78)	0x00000000
>SW_SEMAPHORE (013c)	0x00000000
>TEST_DEBUG_CNTL (0120)	0x04060101
>TEST_DEBUG_MUX (0124)	0x332a5000
>TEST_DEBUG_OUT (012c)	0x00000000
>TMDS_CRC (02a0)	0x04060101
>TRAIL_BRES_DEC (1614)	0xffffffff
>TRAIL_BRES_ERR (160c)	0xffffffff
>TRAIL_BRES_INC (1610)	0xffffffff
>TRAIL_X (1618)	0xffffffff
>TRAIL_X_SUB (1620)	0xffffffff
>PIXCLKS_CNTL (002d)	0x00000000
>VENDOR_ID (0f00)	0x04060101
>VGA_DDA_CONFIG (02e8)	0x00000010
>VGA_DDA_ON_OFF (02ec)	0x00000000
>VID_BUFFER_CONTROL (0900)	0x04060101
>VIDEOMUX_CNTL (0190)	0x00000000
>VIPH_CONTROL (0c40)	0x04060101
>WAIT_UNTIL (1720)	0xffffffff
>RB3D_BLENDCNTL (1c20)	0xffffffff
>RB3D_CNTL (1c3c)	0xffffffff
>RB3D_COLOROFFSET (1c40)	0xffffffff
>RB3D_COLORPITCH (1c48)	0xffffffff
>RB3D_DEPTHOFFSET (1c24)	0xffffffff
>RB3D_DEPTHPITCH (1c28)	0xffffffff
>RB3D_PLANEMASK (1d84)	0xffffffff
>RB3D_ROPCNTL (1d80)	0xffffffff
>RB3D_STENCILREFMASK (1d7c)	0xffffffff
>RB3D_ZSTENCILCNTL (1c2c)	0xffffffff
>RB3D_DSTCACHE_MODE (3258)	0xffffffff
>RE_LINE_PATTERN (1cd0)	0xffffffff
>RE_LINE_STATE (1cd4)	0xffffffff
>RE_MISC (26c4)	0xffffffff
>RE_SOLID_COLOR (1c1c)	0xffffffff
>RE_TOP_LEFT (26c0)	0xffffffff
>RE_WIDTH_HEIGHT (1c44)	0xffffffff
>SE_CNTL_STATUS (2140)	0xffffffff
>LVDS_PLL_CNTL (02d4)	0x00000000
>TMDS_PLL_CNTL (02a8)	0x00000010
>TMDS_TRANSMITTER_CNTL (02a4)	0x332a5000
>ISYNC_CNTL (1724)	0xffffffff
>TV_MASTER_CNTL (0800)	0x04060101
>TV_PRE_DAC_MUX_CNTL (0888)	0x00000010
>TV_RGB_CNTL (0804)	0x332a5000
>TV_SYNC_CNTL (0808)	0x00000010
>TV_HTOTAL (080c)	0x00000000
>TV_HDISP (0810)	0x00000000
>TV_HSTART (0818)	0x00000000
>TV_HCOUNT (081c)	0x00000000
>TV_VTOTAL (0820)	0x04060101
>TV_VDISP (0824)	0x332a5000
>TV_VCOUNT (0828)	0x00000010
>TV_FTOTAL (082c)	0x00000000
>TV_FCOUNT (0830)	0x00000000
>TV_FRESTART (0834)	0x00000000
>TV_HRESTART (0838)	0x00000000
>TV_VRESTART (083c)	0x00000000
>TV_VSCALER_CNTL1 (084c)	0x00000000
>TV_TIMING_CNTL (0850)	0x00000000
>TV_VSCALER_CNTL2 (0854)	0x00000000
>TV_Y_FALL_CNTL (0858)	0x00000000
>TV_Y_RISE_CNTL (085c)	0x00000000
>TV_Y_SAW_TOOTH_CNTL (0860)	0x04060101
>TV_UPSAMP_AND_GAIN_CNTL (0864)	0x332a5000
>TV_GAIN_LIMIT_SETTINGS (0868)	0x00000010
>TV_LINEAR_GAIN_SETTINGS (086c)	0x00000000
>TV_MODULATOR_CNTL1 (0870)	0x00000000
>TV_MODULATOR_CNTL2 (0874)	0x00000000
>TV_CRC_CNTL (0890)	0x00000000
>TV_UV_ADR (08ac)	0x00000000
>GPIOPAD_A (019c)	0x00000000
>RS480_UNK_e30 (0e30)	0x00000000
>RS480_UNK_e34 (0e34)	0x00000000
>RS480_UNK_e38 (0e38)	0x00000000
>RS480_UNK_e3c (0e3c)	0x00000000

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Attachments on bug 13434: 12804 | 12805 | 12806 | 12837 | 12909 | 12967 | 12996

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