Attachment 143063 Details for Bug 109296 – Link layer test result.

Link layer test result.

Chroma_Book_LLCTS_all_R9.html (text/html), 143.16 KB, created by Abhay Kumar on 2019-01-10 22:46:25 UTC

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Creator: Abhay Kumar

Created: 2019-01-10 22:46:25 UTC

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> TABLE.DOCUMENT{width: 100%;}
> P.CONTENTS{font-weight: bold;font-family: "Arial";font-size: 11pt;margin-left: 0.3cm;margin-top: 10;margin-bottom: 0.3cm;color: #000000;}
> P.HEADING{background-color: #BBC3FF;margin-top: 0;margin-bottom: 0.5cm;margin-left: 0cm;font-weight: bold;font-family: "Arial";font-size: 16pt;color: #000000;}
> P.SUBHEADING{background-color: #BBC3FF;margin-top: 1.25cm;margin-bottom: 0.5cm;margin-left: 0.5cm;margin-right: 0;font-weight: bold;font-family: "Arial";font-size: 12pt;color: #000000;text-transform: uppercase;}
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> P.BODYTEXT{margin-top: 0;margin-bottom: 0;margin-left: 1.0cm;font-weight: medium;font-family: "Arial";font-size: 11pt;color: #000000;}
> P.BODYDETAILTEXT{margin-top: 0;margin-bottom: 0;margin-left: 1.4cm;font-weight: medium;font-family: "Arial";font-size: 9pt;color: #000000;}
> P.CONTENTS SELECT{font-weight: normal;font-family: "Arial";font-size: 11pt;width: 98%;margin-top: 0;text-align: left;}
> P.TABLE_HEADERS{background-color: #DCFABC;margin-top: 0;margin-bottom: 0;margin-left: 1.0cm;font-weight: medium;font-family: "Arial";font-size: 12pt;color: #000000;}
> P.TABLE_LINKS{margin-top: 0;margin-bottom: 0;margin-left: 1.0cm;font-weight: medium;font-family: "Arial";font-size: 11pt;}
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> P.SKIP{margin-top: 0;margin-bottom: 0;background-color: #BCBCBC; font-weight: bold;font-family: "Arial";font-size: 11pt;color: #000000;}
> P.LOGBODYTEXT{margin-top: 0;margin-bottom: 0;margin-left: 1.0cm;font-weight: medium;font-family: "Courier";font-size: 11pt;color: #000000;}
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>	<div>&nbsp;&nbsp;Unigraf DPR-120 CTS Test Report</div>
>	<div>
>		<table class="DOCUMENT" cellpadding="0" cellspacing="0">
>			<colgroup>
>				<col width="200">
>				<col width="*">
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>			<td>Select item to display</td>	
>			<td><select id="testlist" onclick="ListHandler (document.getElementById ('testlist').value)" onkeyup="ListHandler (document.getElementById ('testlist').value)">
><option value="0">Report Summary</option>
><option value="1">Test Summary</option>
><option value="2">(400.3.1.1) (FAILED)</option>
><option value="3">(400.3.1.2) (FAILED)</option>
><option value="4">(400.3.1.3) (PASSED)</option>
><option value="5">(400.3.1.4) (PASSED)</option>
><option value="6">(400.3.1.5) (FAILED)</option>
><option value="7">(400.3.1.6) (FAILED)</option>
><option value="8">(400.3.1.7) (PASSED)</option>
><option value="9">(400.3.1.8) (PASSED)</option>
><option value="10">(400.3.1.9) (PASSED)</option>
><option value="11">(700.1.1.1) (PASSED)</option>
><option value="12">(700.1.1.2) (PASSED)</option>
><option value="13">(400.3.1.12) (FAILED)</option>
><option value="14">(400.3.1.13) (FAILED)</option>
><option value="15">(400.3.1.14) (FAILED)</option>
><option value="16">(400.3.1.15) (FAILED)</option>
><option value="17">(400.3.2.1) (FAILED)</option>
><option value="18">(400.3.2.2) (FAILED)</option>
><option value="19">(400.3.2.3) (FAILED)</option>
><option value="20">(400.3.3.1) (FAILED)</option>
><option value="21">(4.2.1.1) (PASSED)</option>
><option value="22">(4.2.1.2) (PASSED)</option>
><option value="23">(4.2.2.1) (PASSED)</option>
><option value="24">(4.2.2.2) (PASSED)</option>
><option value="25">(4.2.2.3) (PASSED)</option>
><option value="26">(4.2.2.4) (PASSED)</option>
><option value="27">(4.2.2.5) (PASSED)</option>
><option value="28">(4.2.2.6) (FAILED)</option>
><option value="29">(4.2.2.7) (PASSED)</option>
><option value="30">(4.2.2.8) (PASSED)</option>
><option value="31">(4.2.2.9) (PASSED)</option>
><option value="32">(4.3.2.4) (FAILED)</option>
><option value="33">(4.3.2.5) (FAILED)</option>
><option value="34">(4.3.2.6) (FAILED)</option>
><option value="35">(4.4.1.1) (FAILED)</option>
><option value="36">(4.4.1.2) (FAILED)</option>
><option value="37">(4.4.1.3) (FAILED)</option>
><option value="38">(4.4.2) (SKIPPED)</option>
><option value="39">(4.4.3) (FAILED)</option>
>		 	 <option value="-1">Show everything</option>
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><div id="ID0">
>&nbsp;&nbsp;&nbsp;Report summary
>&nbsp;&nbsp;&nbsp;DPR-120
>
>Serial Number: 1317C322
> Firmware Release Package: Firmware package version 1.11 [R9]
> Detailed version data: [F1.3.0_N1.2.2_A1.4.6_V1.1.4]
> DPR-120 Debug and Test Controller version: 1.11.9
> Report generated: 12:57, 10-1-2019 
>&nbsp;&nbsp;&nbsp;DUT
>Device/Model name: 
> HW Revision: 
> Serial number: 
> Firmware version: 
> Driver version: 
> Testing conducted by: 
> Remarks:
>
>
>&nbsp;&nbsp;&nbsp;Test results summary
>Total number of test runs: 38 Passed test runs: 17 Failed test runs: 20 Skipped test runs: 1 Aborted test runs: 0
> </div>
><div id="ID1">
>
>&nbsp;&nbsp;&nbsp;Summary of individual test runs
><table width="80%"><colgroup><col span="1" style="width: 90%;"><col span="1" style="width: 10%;"></colgroup>
><tr><th>Test name</th><th>Result</th></tr>
><tr><td><a href="javascript:ListHandler(2)">(400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(3)">(400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(4)">(400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(5)">(400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(6)">(400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(7)">(400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(8)">(400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(9)">(400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(10)">(400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(11)">(700.1.1.1) Additional DPCD Handling Test 1</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(12)">(700.1.1.2) Additional DPCD Handling Test 2</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(13)">(400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(14)">(400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(15)">(400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(16)">(400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(17)">(400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(18)">(400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(19)">(400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(20)">(400.3.3.1) Video Time Stamp Generation</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(21)">(4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(22)">(4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(23)">(4.2.2.1) EDID Read upon HPD Plug Event</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(24)">(4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(25)">(4.2.2.3) EDID Read</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(26)">(4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(27)">(4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(28)">(4.2.2.6) EDID Corruption Detection</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(29)">(4.2.2.7) Branch Device Detection upon HPD Plug Event</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(30)">(4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(31)">(4.2.2.9) E-DDC Four Block EDID Read</a></td><td>&nbsp;PASSED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(32)">(4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(33)">(4.3.2.5) Lane Count Reduction</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(34)">(4.3.2.6) Lane Count Increase</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(35)">(4.4.1.1) Data Packing and Steering</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(36)">(4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(37)">(4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(38)">(4.4.2) Main Video Stream Format Change Handling</a></td><td>&nbsp;SKIPPED&nbsp;</td></tr>
><tr><td><a href="javascript:ListHandler(39)">(4.4.3) Power Management</a></td><td>&nbsp;FAILED&nbsp;</td></tr>
></table></div><div id="ID2">
>&nbsp;&nbsp;&nbsp;Test Details, Test 1
>&nbsp;&nbsp;&nbsp;(400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.1 Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension
> 
> 0000.000.451: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1
> 0000.000.474: Long HPD Pulse (2000 ms)
> 0002.001.379: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0002.001.457:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 02
> 0003.822.050:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.822.818:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.822.837: Source DUT sets LANE_COUNT_SET = 1
> 0003.822.846: Source DUT sets LINK_BW_SET = 06h
> 0003.823.165:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.823.179: Source DUT starts Link Training
> 0003.823.202: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0003.823.257: _CR LT iter_, 1 lane(s)
> 0003.823.365: CR lock succeeded on all active lanes
> 0003.823.624:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.823.843:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00
> 0003.823.856: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0003.823.913: _EQ LT iter_, 1 lane(s)
> 0003.824.588:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.825.136:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.825.153: Equalization succeeded on all active lanes
> 0003.825.162: Symbol lock succeeded on all active lanes
> 0003.825.200: Source DUT completes Link Training
> 0003.825.218: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0003.825.225: Link Training OK
> 0003.828.315: -------------------------------------------------------------
> 
> 0003.828.331: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2
> 0003.828.352: Long HPD Pulse (2000 ms)
> 0005.828.381: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0007.253.977:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0007.254.740:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
> 0007.254.758: Source DUT sets LANE_COUNT_SET = 2
> 0007.254.767: Source DUT sets LINK_BW_SET = 06h
> 0007.255.107:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
> 0007.255.121: Source DUT starts Link Training
> 0007.255.144: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0007.255.201: _CR LT iter_, 2 lane(s)
> 0007.255.318: CR lock succeeded on all active lanes
> 0007.255.573:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
> 0007.255.796:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00
> 0007.255.809: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0007.255.864: _EQ LT iter_, 2 lane(s)
> 0007.256.533:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
> 0007.257.065:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0007.257.082: Equalization succeeded on all active lanes
> 0007.257.092: Symbol lock succeeded on all active lanes
> 0007.257.098: All lanes are properly skewed
> 0007.257.135: Source DUT completes Link Training
> 0007.257.152: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0007.257.159: Link Training OK
> 0007.260.323: -------------------------------------------------------------
> 
> 0007.260.339: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0007.260.360: Long HPD Pulse (2000 ms)
> 0009.260.405: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0010.702.292:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0010.703.053:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0010.703.072: Source DUT sets LANE_COUNT_SET = 4
> 0010.703.081: Source DUT sets LINK_BW_SET = 06h
> 0010.703.411:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0010.703.427: Source DUT starts Link Training
> 0010.703.451: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0010.703.510: _CR LT iter_, 4 lane(s)
> 0010.703.624: CR lock succeeded on all active lanes
> 0010.703.880:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0010.704.117:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0010.704.130: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0010.704.185: _EQ LT iter_, 4 lane(s)
> 0010.704.846:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0010.705.369:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0010.705.386: Equalization succeeded on all active lanes
> 0010.705.395: Symbol lock succeeded on all active lanes
> 0010.705.402: All lanes are properly skewed
> 0010.705.439: Source DUT completes Link Training
> 0010.705.456: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0010.705.463: Link Training OK
> 0010.708.815: -------------------------------------------------------------
> 
> 0010.708.831: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 1
> 0010.708.851: Long HPD Pulse (2000 ms)
> 0012.709.381: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0014.134.336:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0014.135.120:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 81
> 0014.135.139: Source DUT sets LANE_COUNT_SET = 1
> 0014.135.148: Source DUT sets LINK_BW_SET = 0Ah
> 0014.135.480:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0014.135.493: Source DUT starts Link Training
> 0014.135.516: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0014.135.571: _CR LT iter_, 1 lane(s)
> 0014.135.680: CR lock succeeded on all active lanes
> 0014.135.948:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0014.136.171:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00
> 0014.136.184: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0014.136.241: _EQ LT iter_, 1 lane(s)
> 0014.136.929:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0014.137.319:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0014.137.336: Equalization succeeded on all active lanes
> 0014.137.345: Symbol lock succeeded on all active lanes
> 0014.137.382: Source DUT completes Link Training
> 0014.137.400: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0014.137.407: Link Training OK
> 0014.140.660: -------------------------------------------------------------
> 
> 0014.140.675: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 2
> 0014.140.696: Long HPD Pulse (2000 ms)
> 0016.141.380: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0017.582.663:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0017.583.437:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 82
> 0017.583.456: Source DUT sets LANE_COUNT_SET = 2
> 0017.583.464: Source DUT sets LINK_BW_SET = 0Ah
> 0017.583.798:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
> 0017.583.813: Source DUT starts Link Training
> 0017.583.836: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0017.583.893: _CR LT iter_, 2 lane(s)
> 0017.584.005: CR lock succeeded on all active lanes
> 0017.584.270:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
> 0017.584.497:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00
> 0017.584.510: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0017.584.565: _EQ LT iter_, 2 lane(s)
> 0017.585.244:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
> 0017.585.621:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0017.585.638: Equalization succeeded on all active lanes
> 0017.585.647: Symbol lock succeeded on all active lanes
> 0017.585.653: All lanes are properly skewed
> 0017.585.690: Source DUT completes Link Training
> 0017.585.707: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0017.585.715: Link Training OK
> 0017.589.036: -------------------------------------------------------------
> 
> 0017.589.052: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0017.589.073: Long HPD Pulse (2000 ms)
> 0019.589.387: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0021.030.981:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0021.031.752:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0021.031.771: Source DUT sets LANE_COUNT_SET = 4
> 0021.031.780: Source DUT sets LINK_BW_SET = 0Ah
> 0021.032.136:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0021.032.152: Source DUT starts Link Training
> 0021.032.176: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0021.032.235: _CR LT iter_, 4 lane(s)
> 0021.032.359: CR lock succeeded on all active lanes
> 0021.032.621:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0021.032.869:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0021.032.882: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0021.032.937: _EQ LT iter_, 4 lane(s)
> 0021.033.616:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0021.033.987:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0021.034.004: Equalization succeeded on all active lanes
> 0021.034.013: Symbol lock succeeded on all active lanes
> 0021.034.020: All lanes are properly skewed
> 0021.034.056: Source DUT completes Link Training
> 0021.034.074: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0021.034.081: Link Training OK
> 0021.037.462: -------------------------------------------------------------
> 
> 0021.037.478: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 1
> 0021.037.499: Long HPD Pulse (2000 ms)
> 0023.038.398: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0024.479.402:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0024.480.250:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 14 81
> 0024.480.269: Source DUT sets LANE_COUNT_SET = 1
> 0024.480.278: Source DUT sets LINK_BW_SET = 14h
> 0024.480.604:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0024.480.618: Source DUT starts Link Training
> 0024.480.641: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0024.480.695: _CR LT iter_, 1 lane(s)
> 0024.480.804: CR lock succeeded on all active lanes
> 0024.481.067:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0024.481.285:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00
> 0024.481.298: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0024.481.356: _EQ LT iter_, 1 lane(s)
> 0024.482.033:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0024.482.334:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0024.482.351: Equalization succeeded on all active lanes
> 0024.482.361: Symbol lock succeeded on all active lanes
> 0024.482.398: Source DUT completes Link Training
> 0024.482.415: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0024.482.423: Link Training OK
> 0024.485.757: -------------------------------------------------------------
> 
> 0024.485.773: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 2
> 0024.485.793: Long HPD Pulse (2000 ms)
> 0026.486.389: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0027.927.720:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0027.928.477:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 14 82
> 0027.928.496: Source DUT sets LANE_COUNT_SET = 2
> 0027.928.505: Source DUT sets LINK_BW_SET = 14h
> 0027.928.810:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
> 0027.928.824: Source DUT starts Link Training
> 0027.928.847: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0027.928.904: _CR LT iter_, 2 lane(s)
> 0027.929.015: CR lock succeeded on all active lanes
> 0027.929.265:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
> 0027.929.483:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00
> 0027.929.496: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0027.929.551: _EQ LT iter_, 2 lane(s)
> 0027.930.206:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
> 0027.930.563:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0027.930.580: Equalization succeeded on all active lanes
> 0027.930.589: Symbol lock succeeded on all active lanes
> 0027.930.596: All lanes are properly skewed
> 0027.930.633: Source DUT completes Link Training
> 0027.930.651: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0027.930.658: Link Training OK
> 0027.934.057: -------------------------------------------------------------
> 
> 0027.934.072: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0027.934.094: Long HPD Pulse (2000 ms)
> GUk Training OK
> 0027.934.057: ----------------------------------------------------------0031.376.260:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0031.377.017:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0031.377.036: Source DUT sets LANE_COUNT_SET = 4
> 0031.377.045: Source DUT sets LINK_BW_SET = 0Ah
> 0031.377.052: Expected LINK_BW_SET = 14h
> 0031.377.083: Source DUT supports TEST_LINK_TRAINING
> 0031.377.091: Source DUT is ready to accept test requests at any time after plug
> 0031.377.377:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0031.377.393: Source DUT starts Link Training
> 0031.377.442: _CR LT iter_, 4 lane(s)
> 0031.377.800:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0031.378.036:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0031.378.101: _EQ LT iter_, 4 lane(s)
> 0031.378.757:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0031.379.113:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0031.379.127: Source DUT completes Link Training
> 0031.382.545: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0031.382.564: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0031.382.572: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0031.382.596: Short HPD pulse (0.75 ms)
> 0031.383.384: Wait for a write to TEST_RESPONSE
> 0031.388.707: TEST_RESPONSE.TEST_ACK is set
> 0031.388.741: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0031.389.030:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0032.396.087:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0046.389.337: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0046.390.162: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID3">
>&nbsp;&nbsp;&nbsp;Test Details, Test 2
>&nbsp;&nbsp;&nbsp;(400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.2 Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension
> 
> 0000.000.461: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.485: Long HPD Pulse (2000 ms)
> 0002.001.127: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.441.654:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.442.416:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.442.436: Source DUT sets LANE_COUNT_SET = 4
> 0003.442.445: Source DUT sets LINK_BW_SET = 0Ah
> 0003.442.451: Expected LINK_BW_SET = 14h
> 0003.442.483: Source DUT supports TEST_LINK_TRAINING
> 0003.442.491: Source DUT is ready to accept test requests at any time after plug
> 0003.442.775:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.442.792: Source DUT starts Link Training
> 0003.442.840: _CR LT iter_, 4 lane(s)
> 0003.443.206:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.443.443:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.443.508: _EQ LT iter_, 4 lane(s)
> 0003.444.172:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.444.532:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.444.546: Source DUT completes Link Training
> 0003.447.977: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.447.995: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.448.003: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.448.027: Short HPD pulse (0.75 ms)
> 0003.448.820: Wait for a write to TEST_RESPONSE
> 0003.454.220: TEST_RESPONSE.TEST_ACK is set
> 0003.454.255: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.454.540:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.461.884:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.455.056: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.455.880: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID4">
>&nbsp;&nbsp;&nbsp;Test Details, Test 3
>&nbsp;&nbsp;&nbsp;(400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.3 Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
> 
> 0000.000.471: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.494: Long HPD Pulse (2000 ms)
> GUHPD Pulse (2000 ms)
> test: 400.3.1.3 Successful LT to a Lower Link Rate #1: Iterate at0003.423.583:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.424.343:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.424.363: Source DUT sets LANE_COUNT_SET = 4
> 0003.424.372: Source DUT sets LINK_BW_SET = 0Ah
> 0003.424.699:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.424.715: Source DUT starts Link Training
> 0003.424.739: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0003.424.832: _CR LT iter_, 4 lane(s)
> 0003.424.921: Adjust request - voltage swing level 1
> 0003.424.941: Clear LANEx_x_STATUS
> 0003.425.187:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11
> 0003.425.416:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 01 01 01 01
> 0003.425.478: _CR LT iter_, 4 lane(s)
> 0003.425.568: Adjust request - voltage swing level 2
> 0003.425.588: Clear LANEx_x_STATUS
> 0003.425.840:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
> 0003.426.070:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 06 06 06 06
> 0003.426.133: _CR LT iter_, 4 lane(s)
> 0003.426.231: Adjust request - voltage swing level 2
> 0003.426.252: Clear LANEx_x_STATUS
> 0003.426.264: Set iteration counter to 1
> 0003.426.505:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
> 0003.426.712:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0004.497.811:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 00 00 22 22
> 0004.665.778:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 02
> 0004.666.155:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0004.666.922:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0004.666.935: Source DUT sets LINK_BW_SET = 06h
> 0004.667.307:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0004.667.324: Source DUT starts Link Training
> 0004.667.373: _CR LT iter_, 4 lane(s)
> 0004.667.486: CR lock succeeded on all active lanes
> 0004.667.762:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0004.668.010:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0004.668.022: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0004.668.077: _EQ LT iter_, 4 lane(s)
> 0004.668.756:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0004.669.313:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0004.669.331: Equalization succeeded on all active lanes
> 0004.669.340: Symbol lock succeeded on all active lanes
> 0004.669.346: All lanes are properly skewed
> 0004.669.383: Source DUT completes Link Training
> 0004.669.402: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0004.669.410: Link Training OK
> 0004.675.595: Test PASSED
> 
> 
> </div><div id="ID5">
>&nbsp;&nbsp;&nbsp;Test Details, Test 4
>&nbsp;&nbsp;&nbsp;(400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.4 Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
> 
> 0000.000.472: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.496: Long HPD Pulse (2000 ms)
> GUong HPD Pulse (2000 ms)
> t: 400.3.1.4 Successful LT to a Lower Link Rate #2: Iterate at0003.414.806:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.415.560:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.415.580: Source DUT sets LANE_COUNT_SET = 4
> 0003.415.589: Source DUT sets LINK_BW_SET = 0Ah
> 0003.415.910:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.415.926: Source DUT starts Link Training
> 0003.415.951: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0003.416.043: _CR LT iter_, 4 lane(s)
> 0003.416.135: Clear LANEx_x_STATUS
> 0003.416.150: Set iteration counter to 1
> 0003.416.391:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 00 00 00 00
> 0003.416.617:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.416.644: Increment iteration counter to 2
> 0003.416.679: _CR LT iter_, 4 lane(s)
> 0003.416.772: Adjust request - voltage swing level 0
> 0003.416.792: Clear LANEx_x_STATUS
> 0003.417.037:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.417.262:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.417.290: Increment iteration counter to 3
> 0003.417.324: _CR LT iter_, 4 lane(s)
> 0003.417.416: Adjust request - voltage swing level 0
> 0003.417.437: Clear LANEx_x_STATUS
> 0003.417.679:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.417.904:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.417.932: Increment iteration counter to 4
> 0003.417.966: _CR LT iter_, 4 lane(s)
> 0003.418.059: Adjust request - voltage swing level 0
> 0003.418.079: Clear LANEx_x_STATUS
> 0003.418.320:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.418.545:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.418.573: Increment iteration counter to 5
> 0003.418.606: _CR LT iter_, 4 lane(s)
> 0003.418.700: Adjust request - voltage swing level 0
> 0003.418.720: Clear LANEx_x_STATUS
> 0003.418.963:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.419.169:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0004.488.581:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 00 00 00 00
> 0004.659.192:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 02
> 0004.659.528:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0004.660.295:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0004.660.310: Source DUT sets LINK_BW_SET = 06h
> 0004.660.672:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0004.660.688: Source DUT starts Link Training
> 0004.660.737: _CR LT iter_, 4 lane(s)
> 0004.660.853: CR lock succeeded on all active lanes
> 0004.661.121:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0004.661.365:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 22 00 00 00 00
> 0004.661.378: Source DUT writes TRAINING_PATTERN_SET = 22h
> 0004.661.431: _EQ LT iter_, 4 lane(s)
> 0004.662.120:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0004.662.680:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0004.662.698: Equalization succeeded on all active lanes
> 0004.662.708: Symbol lock succeeded on all active lanes
> 0004.662.714: All lanes are properly skewed
> 0004.662.752: Source DUT completes Link Training
> 0004.662.771: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0004.662.779: Link Training OK
> 0004.669.063: Test PASSED
> 
> 
> </div><div id="ID6">
>&nbsp;&nbsp;&nbsp;Test Details, Test 5
>&nbsp;&nbsp;&nbsp;(400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.5 Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence
> 
> 0000.000.467: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.490: Long HPD Pulse (2000 ms)
> 0002.000.645: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> GU02.000.645: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> is and Post Cursor 2 Setting During Channel Equalization Sequence
> 
> 0000.000.467: Set MAX_LINK_RATE = 14h, MAX_Lcted LINK_BW_SET = 14h
> 0003.427.394: Source DUT supports TEST_LINK_TRAINING
> 0003.427.402: Source DUT is ready to accept test requests at any time after plug
> 0003.427.699:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.427.716: Source DUT starts Link Training
> 0003.427.764: _CR LT iter_, 4 lane(s)
> 0003.428.126:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.428.362:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.428.427: _EQ LT iter_, 4 lane(s)
> 0003.429.090:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.429.448:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.429.463: Source DUT completes Link Training
> 0003.432.930: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.432.948: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.432.957: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.432.980: Short HPD pulse (0.75 ms)
> 0003.433.769: Wait for a write to TEST_RESPONSE
> 0003.438.987: TEST_RESPONSE.TEST_ACK is set
> 0003.439.021: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.439.304:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.446.393:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.439.555: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.440.386: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID7">
>&nbsp;&nbsp;&nbsp;Test Details, Test 6
>&nbsp;&nbsp;&nbsp;(400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 400.3.1.6 Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension
> 
> 0000.000.475: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.499: Long HPD Pulse (2000 ms)
> GUCOUNT = 4
> 0000.000.499: Long HPD Pulse (2000 ms)
> T at Lower Link Rate Due to Loss of S0003.432.388:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.433.148:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.433.168: Source DUT sets LANE_COUNT_SET = 4
> 0003.433.177: Source DUT sets LINK_BW_SET = 0Ah
> 0003.433.184: Expected LINK_BW_SET = 14h
> 0003.433.216: Source DUT supports TEST_LINK_TRAINING
> 0003.433.224: Source DUT is ready to accept test requests at any time after plug
> 0003.433.507:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.433.524: Source DUT starts Link Training
> 0003.433.573: _CR LT iter_, 4 lane(s)
> 0003.433.935:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.434.174:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.434.239: _EQ LT iter_, 4 lane(s)
> 0003.434.902:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.435.411:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.435.426: Source DUT completes Link Training
> 0003.438.672: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.438.691: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.438.699: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.438.723: Short HPD pulse (0.75 ms)
> 0003.439.512: Wait for a write to TEST_RESPONSE
> 0003.444.794: TEST_RESPONSE.TEST_ACK is set
> 0003.444.829: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.445.119:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.452.185:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.445.158: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.445.987: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID8">
>&nbsp;&nbsp;&nbsp;Test Details, Test 7
>&nbsp;&nbsp;&nbsp;(400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 400.3.1.7 Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
> 
> 0000.000.466: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.000.490: Long HPD Pulse (2000 ms)
> GUHPD Pulse (2000 ms)
> test: 400.3.1.7 Unsuccessful LT at Lower Link Rate #1: Iterate at0003.427.468:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.428.221:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0003.428.240: Source DUT sets LANE_COUNT_SET = 4
> 0003.428.249: Source DUT sets LINK_BW_SET = 06h
> 0003.428.568:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.428.584: Source DUT starts Link Training
> 0003.428.610: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0003.428.701: _CR LT iter_, 4 lane(s)
> 0003.428.792: Adjust request - voltage swing level 1
> 0003.428.812: Clear LANEx_x_STATUS
> 0003.429.056:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11
> 0003.429.291:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 01 01 01 01
> 0003.429.354: _CR LT iter_, 4 lane(s)
> 0003.429.444: Adjust request - voltage swing level 2
> 0003.429.465: Clear LANEx_x_STATUS
> 0003.429.714:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
> 0003.429.941:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 06 06 06 06
> 0003.430.003: _CR LT iter_, 4 lane(s)
> 0003.430.094: Adjust request - voltage swing level 2
> 0003.430.114: Clear LANEx_x_STATUS
> 0003.430.126: Set iteration counter to 1
> 0003.430.364:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
> 0003.430.562:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.430.582: Source DUT writes TRAINING_PATTERN_SET = 0h
> 0003.438.628: Test PASSED
> 
> 
> </div><div id="ID9">
>&nbsp;&nbsp;&nbsp;Test Details, Test 8
>&nbsp;&nbsp;&nbsp;(400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.8 Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
> 
> 0000.000.469: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.000.494: Long HPD Pulse (2000 ms)
> 0002.001.159: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.445.444:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.446.208:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0003.446.228: Source DUT sets LANE_COUNT_SET = 4
> 0003.446.237: Source DUT sets LINK_BW_SET = 06h
> 0003.446.577:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.446.593: Source DUT starts Link Training
> 0003.446.619: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0003.446.710: _CR LT iter_, 4 lane(s)
> 0003.446.800: Adjust request - voltage swing level 0
> 0003.446.820: Clear LANEx_x_STATUS
> 0003.446.833: Set iteration counter to 1
> 0003.447.084:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.447.322:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.447.351: Increment iteration counter to 2
> 0003.447.384: _CR LT iter_, 4 lane(s)
> 0003.447.475: Adjust request - voltage swing level 0
> 0003.447.495: Clear LANEx_x_STATUS
> 0003.447.758:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.447.994:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.448.023: Increment iteration counter to 3
> 0003.448.057: _CR LT iter_, 4 lane(s)
> 0003.448.149: Adjust request - voltage swing level 0
> 0003.448.168: Clear LANEx_x_STATUS
> 0003.448.428:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.448.666:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.448.695: Increment iteration counter to 4
> 0003.448.727: _CR LT iter_, 4 lane(s)
> 0003.448.819: Adjust request - voltage swing level 0
> 0003.448.839: Clear LANEx_x_STATUS
> 0003.449.105:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.449.341:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
> 0003.449.368: Increment iteration counter to 5
> 0003.449.403: _CR LT iter_, 4 lane(s)
> 0003.449.493: Adjust request - voltage swing level 0
> 0003.449.513: Clear LANEx_x_STATUS
> 0003.449.776:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
> 0003.449.996:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.450.016: Source DUT writes TRAINING_PATRN_SET = 00h
> 0003.450.055: Source DUT terminates link training after 5 iterations
> 0003.457.365: Test PASSED
> 
> 
> </div><div id="ID10">
>&nbsp;&nbsp;&nbsp;Test Details, Test 9
>&nbsp;&nbsp;&nbsp;(400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 400.3.1.9 Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension
> 
> 0000.000.473: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.000.496: Long HPD Pulse (2000 ms)
> 0002.001.239: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.440.766:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.441.527:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0003.441.546: Source DUT sets LANE_COUNT_SET = 4
> 0003.441.555: Source DUT sets LINK_BW_SET = 06h
> 0003.441.890:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.441.906: Source DUT starts Link Training
> 0003.441.930: Source DUT writes TRAINING_PATTERN_SET = 21h
> 0003.441.993: _CR LT iter_, 4 lane(s)
> 0003.442.106: CR lock succeeded on all active lanes
> 0003.442.368:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.442.609:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.442.622: Source DUT writes TRAINING_PATTERN_SET = 23h
> 0003.442.708: _EQ LT iter_, 4 lane(s)
> 0003.442.888: Set LANEx_x_STATUS = 1111h
> 0003.443.344:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 44 44
> 0003.443.579:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 08 08 08 08
> 0003.443.659: _EQ LT iter_, 4 lane(s)
> 0003.443.788: Set LANEx_x_STATUS = 1111h
> 0003.444.306:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 88 88
> 0003.444.540:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 10 10 10 10
> 0003.444.558: Set iteration counter to 2
> 0003.444.660: _EQ LT iter_, 4 lane(s)
> 0003.444.786: Set LANEx_x_STATUS = 1111h
> 0003.445.268:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 CC CC
> 0003.445.503:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 38 38 38 38
> 0003.445.520: Set iteration counter to 3
> 0003.445.573: _EQ LT iter_, 4 lane(s)
> 0003.445.700: Set LANEx_x_STATUS = 1111h
> 0003.446.230:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 CC CC
> 0003.446.464:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 38 38 38 38
> 0003.446.492: Increment iteration counter to 4
> 0003.446.527: _EQ LT iter_, 4 lane(s)
> 0003.446.655: Set LANEx_x_STATUS = 1111h
> 0003.447.207:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 CC CC
> 0003.447.441:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 38 38 38 38
> 0003.447.469: Increment iteration counter to 5
> 0003.447.502: _EQ LT iter_, 4 lane(s)
> 0003.447.629: Set LANEx_x_STATUS = 1111h
> 0003.447.938:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.447.952: Source DUT completes Link Training
> 0003.447.967: Source DUT writes TRAINING_PATRN_SET = 00h
> 0003.448.006: Source DUT terminates link training after 5 iterations
> 0003.453.582: Test PASSED
> 
> 
> </div><div id="ID11">
>&nbsp;&nbsp;&nbsp;Test Details, Test 10
>&nbsp;&nbsp;&nbsp;(700.1.1.1) Additional DPCD Handling Test 1
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 700.1.1.1 Additional DPCD Handling Test 1
> 
> 0000.000.509: Set DPCD_REV = 12h
> 0000.000.520: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.537: Set DOWNSTREAMPORT_PRESENT = 11h
> 0000.000.543: Set DOWN_STREAM_PORT_COUNT = 01h
> 0000.000.549: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
> 0000.000.581: Long HPD Pulse (2000 ms)
> 0002.001.267: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
> 0003.415.141:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.415.893:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.416.234:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.416.250: Source DUT starts Link Training
> 0003.416.299: _CR LT iter_, 4 lane(s)
> 0003.416.650:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.416.881:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.416.945: _EQ LT iter_, 4 lane(s)
> 0003.417.593:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.417.939:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.417.957: Equalization succeeded on all active lanes
> 0003.417.966: Symbol lock succeeded on all active lanes
> 0003.417.972: All lanes are properly skewed
> 0003.417.988: Source DUT completes Link Training
> 0003.668.467: Source DUT reads EDID, performs Link Training and transmits video stream
> 0003.670.342: Test PASSED
> 
> 
> </div><div id="ID12">
>&nbsp;&nbsp;&nbsp;Test Details, Test 11
>&nbsp;&nbsp;&nbsp;(700.1.1.2) Additional DPCD Handling Test 2
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 700.1.1.2 Additional DPCD Handling Test 2
> 
> 0000.000.509: Set DPCD_REV = 13h
> 0000.000.525: Set MAX_LINK_RATE = 1Eh, MAX_LANE_COUNT = 4
> 0000.000.548: Set DOWNSTREAMPORT_PRESENT = 11h
> 0000.000.554: Set DOWN_STREAM_PORT_COUNT = 01h
> 0000.000.560: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
> 0000.000.591: Long HPD Pulse (2000 ms)
> 0002.001.408: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
> 0003.417.610:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.418.365:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.418.713:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.418.730: Source DUT starts Link Training
> 0003.418.778: _CR LT iter_, 4 lane(s)
> 0003.419.133:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.419.364:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.419.429: _EQ LT iter_, 4 lane(s)
> 0003.420.080:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.420.429:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.420.448: Equalization succeeded on all active lanes
> 0003.420.457: Symbol lock succeeded on all active lanes
> 0003.420.464: All lanes are properly skewed
> 0003.420.478: Source DUT completes Link Training
> 0003.637.614: Source DUT reads EDID, performs Link Training and transmits video stream
> 0003.639.181: -------------------------------------------------------------
> 
> 0003.639.773: Set DPCD_REV = 20h
> 0003.639.790: Set MAX_LINK_RATE = 20h, MAX_LANE_COUNT = 4
> 0003.639.814: Set DOWNSTREAMPORT_PRESENT = 11h
> 0003.639.820: Set DOWN_STREAM_PORT_COUNT = 01h
> 0003.639.825: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
> 0003.639.856: Long HPD Pulse (2000 ms)
> 0005.640.416: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
> 0007.080.473:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0007.081.234:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0007.081.593:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0007.081.609: Source DUT starts Link Training
> 0007.081.658: _CR LT iter_, 4 lane(s)
> 0007.082.026:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0007.082.268:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0007.082.333: _EQ LT iter_, 4 lane(s)
> 0007.082.991:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0007.083.506:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0007.083.524: Equalization succeeded on all active lanes
> 0007.083.533: Symbol lock succeeded on all active lanes
> 0007.083.540: All lanes are properly skewed
> 0007.083.555: Source DUT completes Link Training
> 0007.317.652: Source DUT reads EDID, performs Link Training and transmits video stream
> 0007.319.211: -------------------------------------------------------------
> 
> 0007.319.808: Set DPCD_REV = 21h
> 0007.319.825: Set MAX_LINK_RATE = 28h, MAX_LANE_COUNT = 4
> 0007.319.847: Set DOWNSTREAMPORT_PRESENT = 11h
> 0007.319.853: Set DOWN_STREAM_PORT_COUNT = 01h
> 0007.319.859: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
> 0007.319.890: Long HPD Pulse (2000 ms)
> 0009.320.399: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
> 0010.759.835:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0010.760.598:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0010.760.960:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0010.760.976: Source DUT starts Link Training
> 0010.761.027: _CR LT iter_, 4 lane(s)
> 0010.761.388:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0010.761.626:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0010.761.692: _EQ LT iter_, 4 lane(s)
> 0010.762.351:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0010.762.863:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0010.762.880: Equalization succeeded on all active lanes
> 0010.762.889: Symbol lock succeeded on all active lanes
> 0010.762.896: All lanes are properly skewed
> 0010.762.910: Source DUT completes Link Training
> 0010.980.629: Source DUT reads EDID, performs Link Training and transmits video stream
> 0010.982.212: -------------------------------------------------------------
> 
> 0010.982.815: Set DPCD_REV = 17h
> 0010.982.832: Set MAX_LINK_RATE = 15h, MAX_LANE_COUNT = 4
> 0010.982.854: Set DOWNSTREAMPORT_PRESENT = 11h
> 0010.982.860: Set DOWN_STREAM_PORT_COUNT = 01h
> 0010.982.865: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
> 0010.982.896: Long HPD Pulse (2000 ms)
> 0012.983.410: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
> 0014.406.215:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0014.406.962:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0014.407.299:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0014.407.316: Source DUT starts Link Training
> 0014.407.365: _CR LT iter_, 4 lane(s)
> 0014.407.715:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0014.407.942:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0014.408.010: _EQ LT iter_, 4 lane(s)
> 0014.408.652:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0014.409.153:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0014.409.171: Equalization succeeded on all active lanes
> 0014.409.180: Symbol lock succeeded on all active lanes
> 0014.409.187: All lanes are properly skewed
> 0014.409.203: Source DUT completes Link Training
> 0014.642.652: Source DUT reads EDID, performs Link Training and transmits video stream
> 0014.644.803: Test PASSED
> 
> 
> </div><div id="ID13">
>&nbsp;&nbsp;&nbsp;Test Details, Test 12
>&nbsp;&nbsp;&nbsp;(400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.12 Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing
> 
> 0000.000.475: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.499: Long HPD Pulse (2000 ms)
> 0002.001.039: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.421.173:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.421.926:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.421.957: Source DUT sets LANE_COUNT_SET = 4
> 0003.421.966: Source DUT sets LINK_BW_SET = 0Ah
> 0003.421.972: Expected LINK_BW_SET = 14h
> 0003.422.005: Source DUT supports TEST_LINK_TRAINING
> 0003.422.013: Source DUT is ready to accept test requests at any time after plug
> 0003.422.276:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.422.292: Source DUT starts Link Training
> 0003.422.341: _CR LT iter_, 4 lane(s)
> 0003.422.700:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.422.935:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.423.001: _EQ LT iter_, 4 lane(s)
> 0003.423.655:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.424.009:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.424.024: Source DUT completes Link Training
> 0003.427.510: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.427.529: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.427.537: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.427.561: Short HPD pulse (0.75 ms)
> 0003.428.349: Wait for a write to TEST_RESPONSE
> 0003.433.631: TEST_RESPONSE.TEST_ACK is set
> 0003.433.666: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.433.946:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.440.691:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.433.991: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.434.828: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID14">
>&nbsp;&nbsp;&nbsp;Test Details, Test 13
>&nbsp;&nbsp;&nbsp;(400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 400.3.1.13 Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing
> 
> 0000.000.476: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.500: Long HPD Pulse (2000 ms)
> 0002.000.809: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.427.724:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.428.471:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.428.491: Source DUT sets LANE_COUNT_SET = 4
> 0003.428.499: Source DUT sets LINK_BW_SET = 0Ah
> 0003.428.506: Expected LINK_BW_SET = 14h
> 0003.428.538: Source DUT supports TEST_LINK_TRAINING
> 0003.428.546: Source DUT is ready to accept test requests at any time after plug
> 0003.428.814:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.428.830: Source DUT starts Link Training
> 0003.428.880: _CR LT iter_, 4 lane(s)
> 0003.429.232:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.429.465:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.429.530: _EQ LT iter_, 4 lane(s)
> 0003.430.178:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.430.532:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.430.547: Source DUT completes Link Training
> 0003.433.981: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.434.000: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.434.008: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.434.032: Short HPD pulse (0.75 ms)
> 0003.434.820: Wait for a write to TEST_RESPONSE
> 0003.440.176: TEST_RESPONSE.TEST_ACK is set
> 0003.440.210: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.440.525:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.448.080:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.440.764: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.441.596: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID15">
>&nbsp;&nbsp;&nbsp;Test Details, Test 14
>&nbsp;&nbsp;&nbsp;(400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.1.14 Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR
> 
> 0000.000.485: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.508: Long HPD Pulse (2000 ms)
> 0002.001.287: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.429.627:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.430.396:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.430.415: Source DUT sets LANE_COUNT_SET = 4
> 0003.430.423: Source DUT sets LINK_BW_SET = 0Ah
> 0003.430.430: Expected LINK_BW_SET = 14h
> 0003.430.462: Source DUT supports TEST_LINK_TRAINING
> 0003.430.470: Source DUT is ready to accept test requests at any time after plug
> 0003.430.754:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.430.771: Source DUT starts Link Training
> 0003.430.820: _CR LT iter_, 4 lane(s)
> 0003.431.179:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.431.416:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.431.482: _EQ LT iter_, 4 lane(s)
> 0003.432.141:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.432.502:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.432.517: Source DUT completes Link Training
> 0003.436.737: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.436.756: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.436.764: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.436.788: Short HPD pulse (0.75 ms)
> 0003.437.576: Wait for a write to TEST_RESPONSE
> 0003.443.015: TEST_RESPONSE.TEST_ACK is set
> 0003.443.049: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.443.335:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.449.745:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.443.238: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.444.067: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID16">
>&nbsp;&nbsp;&nbsp;Test Details, Test 15
>&nbsp;&nbsp;&nbsp;(400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 400.3.1.15 Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences
> 
> 0000.000.486: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.510: Long HPD Pulse (2000 ms)
> 0002.001.377: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.423.990:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.424.749:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.424.770: Source DUT sets LANE_COUNT_SET = 4
> 0003.424.778: Source DUT sets LINK_BW_SET = 0Ah
> 0003.424.785: Expected LINK_BW_SET = 14h
> 0003.424.817: Source DUT supports TEST_LINK_TRAINING
> 0003.424.825: Source DUT is ready to accept test requests at any time after plug
> 0003.425.118:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.425.135: Source DUT starts Link Training
> 0003.425.184: _CR LT iter_, 4 lane(s)
> 0003.425.550:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.425.786:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.425.851: _EQ LT iter_, 4 lane(s)
> 0003.426.513:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.426.874:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.426.888: Source DUT completes Link Training
> 0003.430.362: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.430.380: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.430.389: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.430.412: Short HPD pulse (0.75 ms)
> 0003.431.203: Wait for a write to TEST_RESPONSE
> 0003.436.479: TEST_RESPONSE.TEST_ACK is set
> 0003.436.514: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.436.793:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.443.446:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.437.291: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.438.123: Test FAILED, step 6, error 2: Test timeout
> 
> 
> </div><div id="ID17">
>&nbsp;&nbsp;&nbsp;Test Details, Test 16
>&nbsp;&nbsp;&nbsp;(400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.2.1 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension
> 
> 0000.000.479: Test lane 1
> 0000.000.549: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.573: Long HPD Pulse (2000 ms)
> 0002.001.392: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.425.349:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.426.104:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.426.124: Source DUT sets LANE_COUNT_SET = 4
> 0003.426.134: Source DUT sets LINK_BW_SET = 0Ah
> 0003.426.140: Expected LINK_BW_SET = 14h
> 0003.426.172: Source DUT supports TEST_LINK_TRAINING
> 0003.426.180: Source DUT is ready to accept test requests at any time after plug
> 0003.426.451:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.426.467: Source DUT starts Link Training
> 0003.426.516: _CR LT iter_, 4 lane(s)
> 0003.426.870:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.427.105:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.427.170: _EQ LT iter_, 4 lane(s)
> 0003.427.826:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.428.176:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.428.191: Source DUT completes Link Training
> 0003.432.463: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.432.482: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.432.490: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.432.514: Short HPD pulse (0.75 ms)
> 0003.433.302: Wait for a write to TEST_RESPONSE
> 0003.438.451: TEST_RESPONSE.TEST_ACK is set
> 0003.438.485: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.438.765:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.444.895:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.439.386: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.440.576: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID18">
>&nbsp;&nbsp;&nbsp;Test Details, Test 17
>&nbsp;&nbsp;&nbsp;(400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 400.3.2.2 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension
> 
> 0000.000.481: Test lane 1
> 0000.000.551: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.574: Long HPD Pulse (2000 ms)
> 0002.001.297: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.427.022:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.427.777:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.427.799: Source DUT sets LANE_COUNT_SET = 4
> 0003.427.808: Source DUT sets LINK_BW_SET = 0Ah
> 0003.427.815: Expected LINK_BW_SET = 14h
> 0003.427.846: Source DUT supports TEST_LINK_TRAINING
> 0003.427.854: Source DUT is ready to accept test requests at any time after plug
> 0003.428.129:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.428.146: Source DUT starts Link Training
> 0003.428.194: _CR LT iter_, 4 lane(s)
> 0003.428.553:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.428.788:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.428.853: _EQ LT iter_, 4 lane(s)
> 0003.429.509:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.429.860:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.429.874: Source DUT completes Link Training
> 0003.434.130: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.434.148: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.434.157: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.434.180: Short HPD pulse (0.75 ms)
> 0003.434.969: Wait for a write to TEST_RESPONSE
> 0003.440.253: TEST_RESPONSE.TEST_ACK is set
> 0003.440.287: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.440.574:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.446.860:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.441.275: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.442.466: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID19">
>&nbsp;&nbsp;&nbsp;Test Details, Test 18
>&nbsp;&nbsp;&nbsp;(400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 400.3.2.3 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension
> 
> 0000.000.484: Test lane 1
> 0000.000.554: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
> 0000.000.577: Long HPD Pulse (2000 ms)
> 0002.001.206: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.424.318:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.425.075:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.425.097: Source DUT sets LANE_COUNT_SET = 4
> 0003.425.106: Source DUT sets LINK_BW_SET = 0Ah
> 0003.425.118: Expected LINK_BW_SET = 14h
> 0003.425.149: Source DUT supports TEST_LINK_TRAINING
> 0003.425.157: Source DUT is ready to accept test requests at any time after plug
> 0003.425.430:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.425.447: Source DUT starts Link Training
> 0003.425.495: _CR LT iter_, 4 lane(s)
> 0003.425.856:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.426.090:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.426.155: _EQ LT iter_, 4 lane(s)
> 0003.426.809:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.427.163:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.427.178: Source DUT completes Link Training
> 0003.430.584: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
> 0003.430.602: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.430.611: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.430.634: Short HPD pulse (0.75 ms)
> 0003.431.423: Wait for a write to TEST_RESPONSE
> 0003.436.633: TEST_RESPONSE.TEST_ACK is set
> 0003.436.667: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.436.949:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.443.301:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.437.149: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.438.333: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID20">
>&nbsp;&nbsp;&nbsp;Test Details, Test 19
>&nbsp;&nbsp;&nbsp;(400.3.3.1) Video Time Stamp Generation
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 400.3.3.1 Video Time Stamp Generation
> 
> 0000.000.511: Configure EDID for the test
> 0000.000.520: Setup EDID with one block of data (128 bytes)
> 0000.000.528: Configure EDID for video mode 1920x1080@60Hz 24 bpp
> 0000.000.589: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.000.612: Long HPD Pulse (2000 ms)
> 0002.000.880: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.407.806:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.408.571:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
> 0003.408.592: Source DUT sets LANE_COUNT_SET = 4
> 0003.408.601: Source DUT sets LINK_BW_SET = 06h
> 0003.408.634: Source DUT supports TEST_LINK_TRAINING
> 0003.408.642: Source DUT is ready to accept test requests at any time after plug
> 0003.408.951:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.408.967: Source DUT starts Link Training
> 0003.409.016: _CR LT iter_, 4 lane(s)
> 0003.409.401:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.409.647:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
> 0003.409.712: _EQ LT iter_, 4 lane(s)
> 0003.410.392:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.410.935:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.410.950: Source DUT completes Link Training
> 0003.414.279: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
> 0003.414.297: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.414.305: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.414.329: Short HPD pulse (0.75 ms)
> 0003.415.117: Wait for a write to TEST_RESPONSE
> 0003.420.452: TEST_RESPONSE.TEST_ACK is set
> 0003.420.486: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.420.777:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.427.516:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.420.844: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.519.825: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID21">
>&nbsp;&nbsp;&nbsp;Test Details, Test 20
>&nbsp;&nbsp;&nbsp;(4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.1.1 Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
> 
> 0000.000.486: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.509: Long HPD Pulse (2000 ms)
> 0002.001.343: Reference Sink is set not to respond to any AUX request
> 0002.001.387: Waiting for AUX request ...
> 0002.103.809: First AUX request received
> 0002.103.815: Reference Sink does not send any reply to AUX request
> 0002.103.842: Waiting for 1ms to simulate the Sink device wake-up timeout period ...
> 0002.105.113: 1ms timeout elapsed
> 0002.105.129: Reference Sink is set to respond to AUX requests normally
> 0002.105.156: Waiting for another AUX request ...
> 0002.105.469: AUX request received after 1ms wake-up timeout
> 0002.107.387: Test PASSED
> 
> 
> </div><div id="ID22">
>&nbsp;&nbsp;&nbsp;Test Details, Test 21
>&nbsp;&nbsp;&nbsp;(4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.1.2 Source Retry on Invalid Reply During AUX Read after HPD Plug Event
> 
> 0000.000.479: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.503: Long HPD Pulse (2000 ms)
> 0002.001.009: Reference Sink is set to send partial reply to AUX request
> 0002.001.052: Waiting for AUX request ...
> 0002.103.784: First AUX request received
> 0002.103.799: Reference Sink is set to respond to AUX requests normally
> 0002.103.809: Reference Sink sends a partial AUX reply
> 0002.103.829: Waiting for another AUX request ...
> 0002.104.405: New AUX request received
> 0002.106.597: Test PASSED
> 
> 
> </div><div id="ID23">
>&nbsp;&nbsp;&nbsp;Test Details, Test 22
>&nbsp;&nbsp;&nbsp;(4.2.2.1) EDID Read upon HPD Plug Event
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.2.1 EDID Read upon HPD Plug Event
> 
> 0000.000.505: Setup EDID with one block of data (128 bytes)
> 0000.098.541: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.098.565: Long HPD Pulse (2000 ms)
> 0002.098.901: Source DUT does not disable main link transmission, ignore and continue
> 0002.098.969: Waiting for Source DUT to read entire EDID block ...
> 0002.206.142: Source DUT reads EDID
> 0002.305.071: Test PASSED
> 
> 
> </div><div id="ID24">
>&nbsp;&nbsp;&nbsp;Test Details, Test 23
>&nbsp;&nbsp;&nbsp;(4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
> 
> 0000.000.482: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.506: Long HPD Pulse (2000 ms)
> GU00.000.011: Starting test: 4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
> 
> 0000.000.482: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.506: Long 0002.103.148: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
> 0002.104.175: Test PASSED
> 
> 
> </div><div id="ID25">
>&nbsp;&nbsp;&nbsp;Test Details, Test 24
>&nbsp;&nbsp;&nbsp;(4.2.2.3) EDID Read
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.2.3 EDID Read
> 
> 0000.000.515: Setup EDID with one block of data (128 bytes, single timing)
> 0000.000.633: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.656: Long HPD Pulse (2000 ms)
> 0002.001.269: Source DUT does not disable main link transmission, ignore and continue
> 0002.001.346: Set TEST_REQUEST.TEST_EDID_READ = 1
> 0002.001.356: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0002.001.392: Waiting for Source DUT to read entire EDID block ...
> 0002.108.311: Source DUT reads EDID
> 0002.108.342: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
> 0002.109.680: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
> 0002.109.692: TEST_EDID_CHECKSUM field matches expected checksum
> 0002.109.723: Waiting for requested video ...
> 0003.416.414:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.417.189:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.417.543:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.417.557: Source DUT starts Link Training
> 0003.417.613: _CR LT iter_, 1 lane(s)
> 0003.418.000:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.418.218:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
> 0003.418.285: _EQ LT iter_, 1 lane(s)
> 0003.418.971:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.419.499:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.419.514: Source DUT completes Link Training
> 0003.671.603: Source DUT transmits requested video timing or fail-safe mode
> 0003.771.609: Test PASSED
> 
> 
> </div><div id="ID26">
>&nbsp;&nbsp;&nbsp;Test Details, Test 25
>&nbsp;&nbsp;&nbsp;(4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.010: Starting test: 4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK
> 
> 0000.000.498: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.521: Long HPD Pulse (2000 ms)
> GU00.000.010: Starting test: 4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK
> 
> 0000.000.498: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.521: Long HPD Pulse (2000 ms)
> 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00002.000.778: Set TEST_REQUEST.TEST_EDID_READ = 1
> 0002.000.788: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0002.000.842: Waiting for fail-safe mode ...
> 0002.103.930: Source DUT attempts to read EDID
> 0003.400.236:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.401.010:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
> 0003.401.369:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
> 0003.401.383: Source DUT starts Link Training
> 0003.401.437: _CR LT iter_, 2 lane(s)
> 0003.401.822:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
> 0003.402.049:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00
> 0003.402.117: _EQ LT iter_, 2 lane(s)
> 0003.402.798:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
> 0003.403.340:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.403.354: Source DUT completes Link Training
> 0007.001.877:&nbsp&nbsp Received 1344 Htotal differs from fail-safe 800
> 0007.001.882:&nbsp&nbsp Received 1024 Hactive differs from fail-safe 640
> 0007.001.888:&nbsp&nbsp Received 296 Hstart differs from fail-safe 144
> 0007.001.895:&nbsp&nbsp Received 136 Hsync width differs from fail-safe 96
> 0007.001.901:&nbsp&nbsp Received 806 Vtotal differs from fail-safe 525
> 0007.001.908:&nbsp&nbsp Received 768 Vactive differs from fail-safe 480
> 0007.001.914:&nbsp&nbsp Received 6 Vsync width differs from fail-safe 2
> 0007.001.920: WARNING: Source DUT does not transmit fail-safe video mode
> 0007.006.314: Reference Sink is set to respond normally to I2C over AUX requests
> 0007.006.866: Test PASSED
> 
> 
> </div><div id="ID27">
>&nbsp;&nbsp;&nbsp;Test Details, Test 26
>&nbsp;&nbsp;&nbsp;(4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.2.5 EDID Read Failure #2: I2C-Over-AUX DEFER
> 
> 0000.000.501: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.524: Long HPD Pulse (2000 ms)
> 0002.000.781: Source DUT does not disable main link transmission, ignore and continue
> 0002.000.817: Reference Sink is set to respond with I2C over AUX DEFER to requests with 0x60 and 0xA0 I2C address
> 0002.000.868: Set TEST_REQUEST.TEST_EDID_READ = 1
> 0002.000.879: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0002.000.933: Waiting for fail-safe mode ...
> 0002.104.532: Source DUT attempts to read EDID
> 0003.627.417:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.628.181:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
> 0003.628.530:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
> 0003.628.545: Source DUT starts Link Training
> 0003.628.597: _CR LT iter_, 2 lane(s)
> 0003.628.975:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
> 0003.629.199:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00
> 0003.629.267: _EQ LT iter_, 2 lane(s)
> 0003.629.946:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
> 0003.630.484:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.630.499: Source DUT completes Link Training
> 0007.001.898:&nbsp&nbsp Received 1344 Htotal differs from fail-safe 800
> 0007.001.904:&nbsp&nbsp Received 1024 Hactive differs from fail-safe 640
> 0007.001.913:&nbsp&nbsp Received 296 Hstart differs from fail-safe 144
> 0007.001.920:&nbsp&nbsp Received 136 Hsync width differs from fail-safe 96
> 0007.001.926:&nbsp&nbsp Received 806 Vtotal differs from fail-safe 525
> 0007.001.933:&nbsp&nbsp Received 768 Vactive differs from fail-safe 480
> 0007.001.939:&nbsp&nbsp Received 6 Vsync width differs from fail-safe 2
> 0007.001.945: WARNING: Source DUT does not transmit fail-safe video mode
> 0007.006.386: Reference Sink is set to respond normally to I2C over AUX requests
> 0007.006.946: Test PASSED
> 
> 
> </div><div id="ID28">
>&nbsp;&nbsp;&nbsp;Test Details, Test 27
>&nbsp;&nbsp;&nbsp;(4.2.2.6) EDID Corruption Detection
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 4.2.2.6 EDID Corruption Detection
> 
> 0000.000.520: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.543: Long HPD Pulse (2000 ms)
> 0000.000.572: Reference Sink sets up EDID with incorrect checksum
> 0002.000.611: Source DUT does not disable main link, ignore and continue
> 0002.000.687: Set TEST_REQUEST.TEST_EDID_READ = 1
> 0002.000.697: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0002.000.732: Waiting for Source DUT to read entire EDID block ...
> 0002.106.934: Source DUT reads EDID
> 0002.106.966: Waiting for fail-safe video ...
> 0003.407.013:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.407.799:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
> 0003.408.152:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
> 0003.408.166: Source DUT starts Link Training
> 0003.408.221: _CR LT iter_, 2 lane(s)
> 0003.408.608:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
> 0003.408.837:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00
> 0003.408.905: _EQ LT iter_, 2 lane(s)
> 0003.409.585:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
> 0003.410.125:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.410.139: Source DUT completes Link Training
> 0003.660.870: Source DUT starts video stream
> 0008.661.741:&nbsp&nbsp Received 1344 Htotal differs from fail-safe 800
> 0008.661.747:&nbsp&nbsp Received 1024 Hactive differs from fail-safe 640
> 0008.661.753:&nbsp&nbsp Received 296 Hstart differs from fail-safe 144
> 0008.661.760:&nbsp&nbsp Received 136 Hsync width differs from fail-safe 96
> 0008.661.766:&nbsp&nbsp Received 806 Vtotal differs from fail-safe 525
> 0008.661.772:&nbsp&nbsp Received 768 Vactive differs from fail-safe 480
> 0008.661.778:&nbsp&nbsp Received 6 Vsync width differs from fail-safe 2
> 0008.661.785: Source DUT does not transmit fail-safe video mode
> 0008.666.275: Reference Sink restores EDID checksum
> 0008.667.014: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID29">
>&nbsp;&nbsp;&nbsp;Test Details, Test 28
>&nbsp;&nbsp;&nbsp;(4.2.2.7) Branch Device Detection upon HPD Plug Event
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 4.2.2.7 Branch Device Detection upon HPD Plug Event
> 
> 0000.000.495: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.519: Long HPD Pulse (2000 ms)
> GU00.000.012: Starting test: 4.2.2.7 Branch Device Detection upon HPD Plug Event
> 
> 0000.000.495: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.519: Long HPD Pulse (2000 ms)
> Test FAILED, step 7,ets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
> 0002.001.301: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
> 0002.001.307: Reference Sink sets SINK_COUNT.SINK_COUNT = 01h
> 0002.001.376: Waiting for Source DUT to read DPCD Receiver Capability field ...
> 0002.104.175: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
> 0002.104.210: Start five second timer
> 0002.104.643: Source DUT reads Link Sink Status field SINK_COUNT (DPCD:00200h)
> 0002.105.933: Test PASSED
> 
> 
> </div><div id="ID30">
>&nbsp;&nbsp;&nbsp;Test Details, Test 29
>&nbsp;&nbsp;&nbsp;(4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.2.8 EDID Read on IRQ HPD Event after Branch Device Detection
> 
> 0000.000.491: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.514: Long HPD Pulse (2000 ms)
> 0002.000.698: Source DUT does not disable main link transmission, ignore and continue
> 0002.000.731: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_PRESENT = 1b
> 0002.000.738: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
> 0002.000.745: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
> 0002.000.750: Reference Sink sets SINK_COUNT.SINK_COUNT = 0h
> 0002.000.820: Waiting for Source DUT to read DPCD Receiver Capability field ...
> 0002.103.477: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
> 0002.103.514: Waiting for two seconds ...
> 0004.103.753: Reference Sink sets SINK_COUNT.SINK_COUNT = 1h
> 0004.103.760: Reference Sink sets LANE_ALIGN_STATUS_UPDATED.DOWNSTREAM_PORT_STATUS_CHANGED = 1h
> 0004.104.718: Short HPD pulse (0.75 ms)
> 0004.105.506: Waiting for Source DUT to read EDID ...
> 0004.115.258: Source DUT starts reading EDID
> 0004.116.220: Test PASSED
> 
> 
> </div><div id="ID31">
>&nbsp;&nbsp;&nbsp;Test Details, Test 30
>&nbsp;&nbsp;&nbsp;(4.2.2.9) E-DDC Four Block EDID Read
>
>Test Result: PASSED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.2.2.9 E-DDC Four Block EDID Read
> 
> 0000.000.513: Setup EDID with four block of data (512 bytes)
> 0000.098.606: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.098.629: Long HPD Pulse (2000 ms)
> 0002.098.935: Source DUT does not disable main link transmission, ignore and continue
> 0002.099.006: Set TEST_REQUEST.TEST_EDID_READ = 1
> 0002.099.016: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0002.099.051: Waiting for Source DUT to read entire EDID block ...
> 0002.214.388: Source DUT reads EDID
> 0002.214.418: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
> 0002.215.737: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
> 0002.215.749: TEST_EDID_CHECKSUM field matches expected checksum
> 0002.314.892: Test PASSED
> 
> 
> </div><div id="ID32">
>&nbsp;&nbsp;&nbsp;Test Details, Test 31
>&nbsp;&nbsp;&nbsp;(4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.3.2.4 Handling of IRQ HPD Pulse with No Error Status Bits Set
> 
> 0000.000.533: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.556: Long HPD Pulse (2000 ms)
> GU00.000.011: Starting test: 4.3.2.4 Handling of IRQ HPD Pulse with No Error Status Bits0003.441.625:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.442.392:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.442.410: Source DUT sets LANE_COUNT_SET = 4
> 0003.442.419: Source DUT sets LINK_BW_SET = 0Ah
> 0003.442.452: Source DUT supports TEST_LINK_TRAINING
> 0003.442.460: Source DUT is ready to accept test requests at any time after plug
> 0003.442.762:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.442.778: Source DUT starts Link Training
> 0003.442.827: _CR LT iter_, 4 lane(s)
> 0003.443.203:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.443.446:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 22 00 00 00 00
> 0003.443.511: _EQ LT iter_, 4 lane(s)
> 0003.444.180:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.444.549:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.444.563: Source DUT completes Link Training
> 0003.448.492: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h 
> 0003.448.511: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.448.519: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.448.543: Short HPD pulse (0.75 ms)
> 0003.449.331: Wait for a write to TEST_RESPONSE
> 0003.454.723: TEST_RESPONSE.TEST_ACK is set
> 0003.454.758: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.455.047:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.461.701:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.455.700: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.456.892: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID33">
>&nbsp;&nbsp;&nbsp;Test Details, Test 32
>&nbsp;&nbsp;&nbsp;(4.3.2.5) Lane Count Reduction
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.012: Starting test: 4.3.2.5 Lane Count Reduction
> 
> 0000.001.727: Configure EDID for the test
> 0000.001.737: Setup EDID with one block of data (128 bytes)
> 0000.001.745: Configure EDID for video mode 640x480@60Hz 18 bpp
> 0000.001.807: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.001.830: Long HPD Pulse (2000 ms)
> 0002.002.037: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.391.315:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.392.078:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.392.100: Source DUT sets LANE_COUNT_SET = 1
> 0003.392.108: Expected LANE_COUNT_SET = 4
> 0003.392.115: Source DUT sets LINK_BW_SET = 06h
> 0003.392.147: Source DUT supports TEST_LINK_TRAINING
> 0003.392.155: Source DUT is ready to accept test requests at any time after plug
> 0003.392.434:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.392.448: Source DUT starts Link Training
> 0003.392.503: _CR LT iter_, 1 lane(s)
> 0003.392.878:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.393.093:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
> 0003.393.162: _EQ LT iter_, 1 lane(s)
> 0003.393.831:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.394.369:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.394.383: Source DUT completes Link Training
> 0003.397.469: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
> 0003.397.488: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.397.496: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.397.520: Short HPD pulse (0.75 ms)
> 0003.398.308: Wait for a write to TEST_RESPONSE
> 0003.403.702: TEST_RESPONSE.TEST_ACK is set
> 0003.403.737: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.404.031:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
> 0004.411.126:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
> 0018.403.999: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.502.941: Test FAILED, step 8, error 2: Test timeout
> 
> 
> </div><div id="ID34">
>&nbsp;&nbsp;&nbsp;Test Details, Test 33
>&nbsp;&nbsp;&nbsp;(4.3.2.6) Lane Count Increase
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.3.2.6 Lane Count Increase
> 
> 0000.001.704: Configure EDID for the test
> 0000.001.713: Setup EDID with one block of data (128 bytes)
> 0000.001.721: Configure EDID for video mode 640x480@60Hz 18 bpp
> 0000.001.781: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.001.804: Long HPD Pulse (2000 ms)
> 0002.002.467: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.401.586:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.402.360:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.402.379: Source DUT sets LANE_COUNT_SET = 1
> 0003.402.392: Expected LANE_COUNT_SET = 4
> 0003.402.398: Source DUT sets LINK_BW_SET = 06h
> 0003.402.430: Source DUT supports TEST_LINK_TRAINING
> 0003.402.438: Source DUT is ready to accept test requests at any time after plug
> 0003.402.708:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.402.722: Source DUT starts Link Training
> 0003.402.777: _CR LT iter_, 1 lane(s)
> 0003.403.160:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.403.379:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
> 0003.403.448: _EQ LT iter_, 1 lane(s)
> 0003.404.127:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.404.671:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.404.685: Source DUT completes Link Training
> 0003.407.677: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
> 0003.407.696: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.407.704: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.407.728: Short HPD pulse (0.75 ms)
> 0003.408.515: Wait for a write to TEST_RESPONSE
> 0003.413.912: TEST_RESPONSE.TEST_ACK is set
> 0003.413.947: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.414.249:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
> 0004.421.922:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
> 0018.414.414: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.513.355: Test FAILED, step 8, error 2: Test timeout
> 
> 
> </div><div id="ID35">
>&nbsp;&nbsp;&nbsp;Test Details, Test 34
>&nbsp;&nbsp;&nbsp;(4.4.1.1) Data Packing and Steering
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.4.1.1 Data Packing and Steering
> 
> 0000.000.525: Setup EDID with one block of data (128 bytes)
> 0000.000.536: Configure EDID for video mode 640x480@60Hz 18 bpp
> 0000.000.688: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
> 0000.000.712: Long HPD Pulse (2000 ms)
> 0002.001.228: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.400.676:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.401.449:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.401.469: Source DUT sets LANE_COUNT_SET = 1
> 0003.401.477: Expected LANE_COUNT_SET = 4
> 0003.401.484: Source DUT sets LINK_BW_SET = 06h
> 0003.401.516: Source DUT supports TEST_LINK_TRAINING
> 0003.401.523: Source DUT is ready to accept test requests at any time after plug
> 0003.401.800:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.401.814: Source DUT starts Link Training
> 0003.401.869: _CR LT iter_, 1 lane(s)
> 0003.402.249:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.402.469:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
> 0003.402.538: _EQ LT iter_, 1 lane(s)
> 0003.403.218:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.403.761:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.403.774: Source DUT completes Link Training
> 0003.406.766: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
> 0003.406.785: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.406.793: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.406.818: Short HPD pulse (0.75 ms)
> 0003.407.606: Wait for a write to TEST_RESPONSE
> 0003.412.967: TEST_RESPONSE.TEST_ACK is set
> 0003.413.001: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.413.301:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
> 0004.420.206:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
> 0018.413.174: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.512.129: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID36">
>&nbsp;&nbsp;&nbsp;Test Details, Test 35
>&nbsp;&nbsp;&nbsp;(4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.4.1.2 Main Stream Data Packing and Stuffing - Least Packed TU
> 
> 0000.000.523: Setup EDID with one block of data (128 bytes)
> 0000.000.534: Configure EDID for video mode 640x480@60Hz 18 bpp
> 0000.000.686: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.709: Long HPD Pulse (2000 ms)
> 0002.001.027: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.404.275:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.405.049:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.405.068: Source DUT sets LANE_COUNT_SET = 1
> 0003.405.077: Expected LANE_COUNT_SET = 4
> 0003.405.083: Source DUT sets LINK_BW_SET = 06h
> 0003.405.090: Expected LINK_BW_SET = 0Ah
> 0003.405.121: Source DUT supports TEST_LINK_TRAINING
> 0003.405.129: Source DUT is ready to accept test requests at any time after plug
> 0003.405.399:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.405.413: Source DUT starts Link Training
> 0003.405.468: _CR LT iter_, 1 lane(s)
> 0003.405.855:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.406.073:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
> 0003.406.141: _EQ LT iter_, 1 lane(s)
> 0003.406.832:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.407.372:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.407.387: Source DUT completes Link Training
> 0003.410.308: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h 
> 0003.410.326: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.410.334: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.410.358: Short HPD pulse (0.75 ms)
> 0003.411.145: Wait for a write to TEST_RESPONSE
> 0003.416.556: TEST_RESPONSE.TEST_ACK is set
> 0003.416.590: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.416.896:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
> 0004.424.073:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
> 0018.416.986: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.515.932: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID37">
>&nbsp;&nbsp;&nbsp;Test Details, Test 36
>&nbsp;&nbsp;&nbsp;(4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.4.1.3 Main Stream Data Packing and Stuffing - Most Packed TU
> 
> 0000.000.528: Configure EDID for the test
> 0000.000.538: Setup EDID with one block of data (128 bytes)
> 0000.000.546: Configure EDID for video mode 1280x800@60Hz 18 bpp
> 0000.000.606: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1
> 0000.000.629: Long HPD Pulse (2000 ms)
> 0002.001.335: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.405.422:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.406.193:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
> 0003.406.212: Source DUT sets LANE_COUNT_SET = 1
> 0003.406.220: Source DUT sets LINK_BW_SET = 06h
> 0003.406.254: Source DUT supports TEST_LINK_TRAINING
> 0003.406.262: Source DUT is ready to accept test requests at any time after plug
> 0003.406.540:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
> 0003.406.554: Source DUT starts Link Training
> 0003.406.609: _CR LT iter_, 1 lane(s)
> 0003.406.992:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
> 0003.407.210:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
> 0003.407.279: _EQ LT iter_, 1 lane(s)
> 0003.407.957:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
> 0003.408.479:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.408.493: Source DUT completes Link Training
> 0003.411.678: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 1h 
> 0003.411.697: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.411.705: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.411.729: Short HPD pulse (0.75 ms)
> 0003.412.518: Wait for a write to TEST_RESPONSE
> 0003.417.997: TEST_RESPONSE.TEST_ACK is set
> 0003.418.032: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.418.329:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
> 0004.425.370:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
> 0018.418.302: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.517.271: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div><div id="ID38">
>&nbsp;&nbsp;&nbsp;Test Details, Test 37
>&nbsp;&nbsp;&nbsp;(4.4.2) Main Video Stream Format Change Handling
>
>Test Result: SKIPPED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.013: Starting test: 4.4.2 Main Video Stream Format Change Handling
> 
> 0000.000.523: Skip test. Source DUT does not support video format change without re-training
> 0000.002.618: Test SKIPED
> 
> 
> </div><div id="ID39">
>&nbsp;&nbsp;&nbsp;Test Details, Test 38
>&nbsp;&nbsp;&nbsp;(4.4.3) Power Management
>
>Test Result: FAILED
> Test Settings:
>
>DUT Capabilities:
> &emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
> &emsp;Video format change without LT: Not supported
> &emsp;Link count reduction without LT: Not supported
> &emsp;Driver level 3 (1.2V): Not supported
> &emsp;Pre-Emphasis level 3 (9.5dB): Supported
> &emsp;Fixed timing DUT: No
> &emsp;E-DDC: Supported
> &emsp;HPD Unplug timeout: 2000 ms
> 
> Test automation:
> &emsp;LLCTS_TEST_LINK_TRAINING: Supported
> &emsp;LLCTS_TEST_PATTERN: Not supported
> &emsp;LLCTS_TEST_EDID_READ: Supported
> &emsp;Event indicating DUT ready = None.
> 
>&nbsp;&nbsp;&nbsp;Test Log0000.000.011: Starting test: 4.4.3 Power Management
> 
> 0000.000.546: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
> 0000.000.569: Long HPD Pulse (2000 ms)
> GU00.000.011: Starting test: 4.4.3 Power Management
> 
> 0000.000.546: Set MAX_LINK_RATE = 0003.412.277:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
> 0003.413.028:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
> 0003.413.048: Source DUT sets LANE_COUNT_SET = 4
> 0003.413.057: Source DUT sets LINK_BW_SET = 0Ah
> 0003.413.091: Source DUT supports TEST_LINK_TRAINING
> 0003.413.099: Source DUT is ready to accept test requests at any time after plug
> 0003.413.367:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
> 0003.413.384: Source DUT starts Link Training
> 0003.413.438: _CR LT iter_, 4 lane(s)
> 0003.413.784:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
> 0003.414.012:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 22 00 00 00 00
> 0003.414.077: _EQ LT iter_, 4 lane(s)
> 0003.414.724:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
> 0003.415.067:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
> 0003.415.081: Source DUT completes Link Training
> 0003.418.673: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h 
> 0003.418.692: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
> 0003.418.700: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
> 0003.418.724: Short HPD pulse (0.75 ms)
> 0003.419.513: Wait for a write to TEST_RESPONSE
> 0003.424.683: TEST_RESPONSE.TEST_ACK is set
> 0003.424.718: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
> 0003.424.990:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
> 0004.431.058:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
> 0018.425.447: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
> 0018.426.281: Test FAILED, step 7, error 2: Test timeout
> 
> 
> </div>	</div>
>	<hr>
>	
>		Unigraf Oy | Piispantilankuja 4 | 02240 Espoo | Finland | +358-9-859 550 
>		E-mail: <a href="mailto:info@unigraf.fi">info@unigraf.fi</a> | Web site: <a href="http://www.unigraf.fi">www.unigraf.fi</a>
>	
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	<div><p class="HEADING" id="top">&nbsp;&nbsp;Unigraf DPR-120 CTS Test Report</p></div>
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<option value="0">Report Summary</option>
<option value="1">Test Summary</option>
<option value="2">(400.3.1.1)  (FAILED)</option>
<option value="3">(400.3.1.2)  (FAILED)</option>
<option value="4">(400.3.1.3)  (PASSED)</option>
<option value="5">(400.3.1.4)  (PASSED)</option>
<option value="6">(400.3.1.5)  (FAILED)</option>
<option value="7">(400.3.1.6)  (FAILED)</option>
<option value="8">(400.3.1.7)  (PASSED)</option>
<option value="9">(400.3.1.8)  (PASSED)</option>
<option value="10">(400.3.1.9)  (PASSED)</option>
<option value="11">(700.1.1.1)  (PASSED)</option>
<option value="12">(700.1.1.2)  (PASSED)</option>
<option value="13">(400.3.1.12)  (FAILED)</option>
<option value="14">(400.3.1.13)  (FAILED)</option>
<option value="15">(400.3.1.14)  (FAILED)</option>
<option value="16">(400.3.1.15)  (FAILED)</option>
<option value="17">(400.3.2.1)  (FAILED)</option>
<option value="18">(400.3.2.2)  (FAILED)</option>
<option value="19">(400.3.2.3)  (FAILED)</option>
<option value="20">(400.3.3.1)  (FAILED)</option>
<option value="21">(4.2.1.1)  (PASSED)</option>
<option value="22">(4.2.1.2)  (PASSED)</option>
<option value="23">(4.2.2.1)  (PASSED)</option>
<option value="24">(4.2.2.2)  (PASSED)</option>
<option value="25">(4.2.2.3)  (PASSED)</option>
<option value="26">(4.2.2.4)  (PASSED)</option>
<option value="27">(4.2.2.5)  (PASSED)</option>
<option value="28">(4.2.2.6)  (FAILED)</option>
<option value="29">(4.2.2.7)  (PASSED)</option>
<option value="30">(4.2.2.8)  (PASSED)</option>
<option value="31">(4.2.2.9)  (PASSED)</option>
<option value="32">(4.3.2.4)  (FAILED)</option>
<option value="33">(4.3.2.5)  (FAILED)</option>
<option value="34">(4.3.2.6)  (FAILED)</option>
<option value="35">(4.4.1.1)  (FAILED)</option>
<option value="36">(4.4.1.2)  (FAILED)</option>
<option value="37">(4.4.1.3)  (FAILED)</option>
<option value="38">(4.4.2)  (SKIPPED)</option>
<option value="39">(4.4.3)  (FAILED)</option>
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<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Report summary</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;DPR-120
<p class="BODYTEXT">
Serial Number: 1317C322
<br>Firmware Release Package: Firmware package version 1.11 [R9]
<br>Detailed version data: [F1.3.0_N1.2.2_A1.4.6_V1.1.4]
<br><br>DPR-120 Debug and Test Controller version: 1.11.9
<br><br>Report generated: 12:57, 10-1-2019<br>
</p></p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;DUT<p class="BODYTEXT">
Device/Model name: 
<br>HW Revision: 
<br>Serial number: 
<br>Firmware version: 
<br>Driver version: 
<br><br>Testing conducted by: 
<br><br>Remarks:
<p class="BODYDETAILTEXT">

</p></p></p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test results summary<p class="BODYTEXT">
Total number of test runs: 38<br>Passed test runs: 17<br>Failed test runs: 20<br>Skipped test runs: 1<br>Aborted test runs: 0
<br></p></p></div>
<div id="ID1">
<p class="BODYTEXT">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Summary of individual test runs</p>
<table width="80%"><colgroup><col span="1" style="width: 90%;"><col span="1" style="width: 10%;"></colgroup>
<tr><th><p class="TABLE_HEADERS">Test name</p></th><th><p class="TABLE_HEADERS" style="margin-left: 0;">Result</p></th></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(2)">(400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(3)">(400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(4)">(400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(5)">(400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(6)">(400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(7)">(400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(8)">(400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(9)">(400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(10)">(400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(11)">(700.1.1.1) Additional DPCD Handling Test 1</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(12)">(700.1.1.2) Additional DPCD Handling Test 2</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(13)">(400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(14)">(400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(15)">(400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(16)">(400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(17)">(400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(18)">(400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(19)">(400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(20)">(400.3.3.1) Video Time Stamp Generation</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(21)">(4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(22)">(4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(23)">(4.2.2.1) EDID Read upon HPD Plug Event</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(24)">(4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(25)">(4.2.2.3) EDID Read</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(26)">(4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(27)">(4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(28)">(4.2.2.6) EDID Corruption Detection</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(29)">(4.2.2.7) Branch Device Detection upon HPD Plug Event</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(30)">(4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(31)">(4.2.2.9) E-DDC Four Block EDID Read</a></p></td><td><p class="SKIP">&nbsp;PASSED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(32)">(4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(33)">(4.3.2.5) Lane Count Reduction</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(34)">(4.3.2.6) Lane Count Increase</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(35)">(4.4.1.1) Data Packing and Steering</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(36)">(4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(37)">(4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(38)">(4.4.2) Main Video Stream Format Change Handling</a></p></td><td><p class="SKIP">&nbsp;SKIPPED&nbsp;</p></td></tr>
<tr><td><p class="TABLE_LINKS"><a href="javascript:ListHandler(39)">(4.4.3) Power Management</a></p></td><td><p class="SKIP">&nbsp;FAILED&nbsp;</p></td></tr>
</table></p></div><div id="ID2">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 1</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.1 Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension
<br> 
<br>0000.000.451: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1
<br>0000.000.474: Long HPD Pulse (2000 ms)
<br>0002.001.379: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0002.001.457:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 02
<br>0003.822.050:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.822.818:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.822.837: Source DUT sets LANE_COUNT_SET = 1
<br>0003.822.846: Source DUT sets LINK_BW_SET = 06h
<br>0003.823.165:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.823.179: Source DUT starts Link Training
<br>0003.823.202: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0003.823.257: _CR LT iter_, 1 lane(s)
<br>0003.823.365: CR lock succeeded on all active lanes
<br>0003.823.624:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.823.843:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00
<br>0003.823.856: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0003.823.913: _EQ LT iter_, 1 lane(s)
<br>0003.824.588:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.825.136:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.825.153: Equalization succeeded on all active lanes
<br>0003.825.162: Symbol lock succeeded on all active lanes
<br>0003.825.200: Source DUT completes Link Training
<br>0003.825.218: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0003.825.225: Link Training OK
<br>0003.828.315: -------------------------------------------------------------
<br> 
<br>0003.828.331: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2
<br>0003.828.352: Long HPD Pulse (2000 ms)
<br>0005.828.381: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0007.253.977:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0007.254.740:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
<br>0007.254.758: Source DUT sets LANE_COUNT_SET = 2
<br>0007.254.767: Source DUT sets LINK_BW_SET = 06h
<br>0007.255.107:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
<br>0007.255.121: Source DUT starts Link Training
<br>0007.255.144: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0007.255.201: _CR LT iter_, 2 lane(s)
<br>0007.255.318: CR lock succeeded on all active lanes
<br>0007.255.573:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
<br>0007.255.796:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00
<br>0007.255.809: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0007.255.864: _EQ LT iter_, 2 lane(s)
<br>0007.256.533:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
<br>0007.257.065:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0007.257.082: Equalization succeeded on all active lanes
<br>0007.257.092: Symbol lock succeeded on all active lanes
<br>0007.257.098: All lanes are properly skewed
<br>0007.257.135: Source DUT completes Link Training
<br>0007.257.152: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0007.257.159: Link Training OK
<br>0007.260.323: -------------------------------------------------------------
<br> 
<br>0007.260.339: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0007.260.360: Long HPD Pulse (2000 ms)
<br>0009.260.405: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0010.702.292:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0010.703.053:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0010.703.072: Source DUT sets LANE_COUNT_SET = 4
<br>0010.703.081: Source DUT sets LINK_BW_SET = 06h
<br>0010.703.411:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0010.703.427: Source DUT starts Link Training
<br>0010.703.451: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0010.703.510: _CR LT iter_, 4 lane(s)
<br>0010.703.624: CR lock succeeded on all active lanes
<br>0010.703.880:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0010.704.117:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0010.704.130: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0010.704.185: _EQ LT iter_, 4 lane(s)
<br>0010.704.846:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0010.705.369:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0010.705.386: Equalization succeeded on all active lanes
<br>0010.705.395: Symbol lock succeeded on all active lanes
<br>0010.705.402: All lanes are properly skewed
<br>0010.705.439: Source DUT completes Link Training
<br>0010.705.456: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0010.705.463: Link Training OK
<br>0010.708.815: -------------------------------------------------------------
<br> 
<br>0010.708.831: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 1
<br>0010.708.851: Long HPD Pulse (2000 ms)
<br>0012.709.381: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0014.134.336:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0014.135.120:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 81
<br>0014.135.139: Source DUT sets LANE_COUNT_SET = 1
<br>0014.135.148: Source DUT sets LINK_BW_SET = 0Ah
<br>0014.135.480:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0014.135.493: Source DUT starts Link Training
<br>0014.135.516: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0014.135.571: _CR LT iter_, 1 lane(s)
<br>0014.135.680: CR lock succeeded on all active lanes
<br>0014.135.948:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0014.136.171:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00
<br>0014.136.184: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0014.136.241: _EQ LT iter_, 1 lane(s)
<br>0014.136.929:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0014.137.319:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0014.137.336: Equalization succeeded on all active lanes
<br>0014.137.345: Symbol lock succeeded on all active lanes
<br>0014.137.382: Source DUT completes Link Training
<br>0014.137.400: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0014.137.407: Link Training OK
<br>0014.140.660: -------------------------------------------------------------
<br> 
<br>0014.140.675: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 2
<br>0014.140.696: Long HPD Pulse (2000 ms)
<br>0016.141.380: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0017.582.663:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0017.583.437:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 82
<br>0017.583.456: Source DUT sets LANE_COUNT_SET = 2
<br>0017.583.464: Source DUT sets LINK_BW_SET = 0Ah
<br>0017.583.798:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
<br>0017.583.813: Source DUT starts Link Training
<br>0017.583.836: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0017.583.893: _CR LT iter_, 2 lane(s)
<br>0017.584.005: CR lock succeeded on all active lanes
<br>0017.584.270:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
<br>0017.584.497:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00
<br>0017.584.510: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0017.584.565: _EQ LT iter_, 2 lane(s)
<br>0017.585.244:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
<br>0017.585.621:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0017.585.638: Equalization succeeded on all active lanes
<br>0017.585.647: Symbol lock succeeded on all active lanes
<br>0017.585.653: All lanes are properly skewed
<br>0017.585.690: Source DUT completes Link Training
<br>0017.585.707: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0017.585.715: Link Training OK
<br>0017.589.036: -------------------------------------------------------------
<br> 
<br>0017.589.052: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0017.589.073: Long HPD Pulse (2000 ms)
<br>0019.589.387: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0021.030.981:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0021.031.752:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0021.031.771: Source DUT sets LANE_COUNT_SET = 4
<br>0021.031.780: Source DUT sets LINK_BW_SET = 0Ah
<br>0021.032.136:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0021.032.152: Source DUT starts Link Training
<br>0021.032.176: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0021.032.235: _CR LT iter_, 4 lane(s)
<br>0021.032.359: CR lock succeeded on all active lanes
<br>0021.032.621:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0021.032.869:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0021.032.882: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0021.032.937: _EQ LT iter_, 4 lane(s)
<br>0021.033.616:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0021.033.987:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0021.034.004: Equalization succeeded on all active lanes
<br>0021.034.013: Symbol lock succeeded on all active lanes
<br>0021.034.020: All lanes are properly skewed
<br>0021.034.056: Source DUT completes Link Training
<br>0021.034.074: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0021.034.081: Link Training OK
<br>0021.037.462: -------------------------------------------------------------
<br> 
<br>0021.037.478: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 1
<br>0021.037.499: Long HPD Pulse (2000 ms)
<br>0023.038.398: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0024.479.402:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0024.480.250:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 14 81
<br>0024.480.269: Source DUT sets LANE_COUNT_SET = 1
<br>0024.480.278: Source DUT sets LINK_BW_SET = 14h
<br>0024.480.604:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0024.480.618: Source DUT starts Link Training
<br>0024.480.641: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0024.480.695: _CR LT iter_, 1 lane(s)
<br>0024.480.804: CR lock succeeded on all active lanes
<br>0024.481.067:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0024.481.285:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00
<br>0024.481.298: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0024.481.356: _EQ LT iter_, 1 lane(s)
<br>0024.482.033:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0024.482.334:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0024.482.351: Equalization succeeded on all active lanes
<br>0024.482.361: Symbol lock succeeded on all active lanes
<br>0024.482.398: Source DUT completes Link Training
<br>0024.482.415: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0024.482.423: Link Training OK
<br>0024.485.757: -------------------------------------------------------------
<br> 
<br>0024.485.773: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 2
<br>0024.485.793: Long HPD Pulse (2000 ms)
<br>0026.486.389: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0027.927.720:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0027.928.477:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 14 82
<br>0027.928.496: Source DUT sets LANE_COUNT_SET = 2
<br>0027.928.505: Source DUT sets LINK_BW_SET = 14h
<br>0027.928.810:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
<br>0027.928.824: Source DUT starts Link Training
<br>0027.928.847: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0027.928.904: _CR LT iter_, 2 lane(s)
<br>0027.929.015: CR lock succeeded on all active lanes
<br>0027.929.265:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
<br>0027.929.483:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00
<br>0027.929.496: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0027.929.551: _EQ LT iter_, 2 lane(s)
<br>0027.930.206:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
<br>0027.930.563:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0027.930.580: Equalization succeeded on all active lanes
<br>0027.930.589: Symbol lock succeeded on all active lanes
<br>0027.930.596: All lanes are properly skewed
<br>0027.930.633: Source DUT completes Link Training
<br>0027.930.651: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0027.930.658: Link Training OK
<br>0027.934.057: -------------------------------------------------------------
<br> 
<br>0027.934.072: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0027.934.094: Long HPD Pulse (2000 ms)
<br>GUk Training OK
<br>0027.934.057: ----------------------------------------------------------0031.376.260:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0031.377.017:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0031.377.036: Source DUT sets LANE_COUNT_SET = 4
<br>0031.377.045: Source DUT sets LINK_BW_SET = 0Ah
<br>0031.377.052: Expected LINK_BW_SET = 14h
<br>0031.377.083: Source DUT supports TEST_LINK_TRAINING
<br>0031.377.091: Source DUT is ready to accept test requests at any time after plug
<br>0031.377.377:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0031.377.393: Source DUT starts Link Training
<br>0031.377.442: _CR LT iter_, 4 lane(s)
<br>0031.377.800:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0031.378.036:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0031.378.101: _EQ LT iter_, 4 lane(s)
<br>0031.378.757:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0031.379.113:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0031.379.127: Source DUT completes Link Training
<br>0031.382.545: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0031.382.564: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0031.382.572: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0031.382.596: Short HPD pulse (0.75 ms)
<br>0031.383.384: Wait for a write to TEST_RESPONSE
<br>0031.388.707: TEST_RESPONSE.TEST_ACK is set
<br>0031.388.741: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0031.389.030:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0032.396.087:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0046.389.337: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0046.390.162: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID3">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 2</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.2 Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension
<br> 
<br>0000.000.461: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.485: Long HPD Pulse (2000 ms)
<br>0002.001.127: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.441.654:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.442.416:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.442.436: Source DUT sets LANE_COUNT_SET = 4
<br>0003.442.445: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.442.451: Expected LINK_BW_SET = 14h
<br>0003.442.483: Source DUT supports TEST_LINK_TRAINING
<br>0003.442.491: Source DUT is ready to accept test requests at any time after plug
<br>0003.442.775:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.442.792: Source DUT starts Link Training
<br>0003.442.840: _CR LT iter_, 4 lane(s)
<br>0003.443.206:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.443.443:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.443.508: _EQ LT iter_, 4 lane(s)
<br>0003.444.172:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.444.532:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.444.546: Source DUT completes Link Training
<br>0003.447.977: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.447.995: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.448.003: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.448.027: Short HPD pulse (0.75 ms)
<br>0003.448.820: Wait for a write to TEST_RESPONSE
<br>0003.454.220: TEST_RESPONSE.TEST_ACK is set
<br>0003.454.255: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.454.540:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.461.884:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.455.056: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.455.880: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID4">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 3</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.3 Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
<br> 
<br>0000.000.471: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.494: Long HPD Pulse (2000 ms)
<br>GUHPD Pulse (2000 ms)
<br> test: 400.3.1.3 Successful LT to a Lower Link Rate #1: Iterate at0003.423.583:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.424.343:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.424.363: Source DUT sets LANE_COUNT_SET = 4
<br>0003.424.372: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.424.699:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.424.715: Source DUT starts Link Training
<br>0003.424.739: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0003.424.832: _CR LT iter_, 4 lane(s)
<br>0003.424.921: Adjust request - voltage swing level 1
<br>0003.424.941: Clear LANEx_x_STATUS
<br>0003.425.187:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11
<br>0003.425.416:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 01 01 01 01
<br>0003.425.478: _CR LT iter_, 4 lane(s)
<br>0003.425.568: Adjust request - voltage swing level 2
<br>0003.425.588: Clear LANEx_x_STATUS
<br>0003.425.840:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
<br>0003.426.070:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 06 06 06 06
<br>0003.426.133: _CR LT iter_, 4 lane(s)
<br>0003.426.231: Adjust request - voltage swing level 2
<br>0003.426.252: Clear LANEx_x_STATUS
<br>0003.426.264: Set iteration counter to 1
<br>0003.426.505:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
<br>0003.426.712:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0004.497.811:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 00 00 22 22
<br>0004.665.778:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 02
<br>0004.666.155:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0004.666.922:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0004.666.935: Source DUT sets LINK_BW_SET = 06h
<br>0004.667.307:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0004.667.324: Source DUT starts Link Training
<br>0004.667.373: _CR LT iter_, 4 lane(s)
<br>0004.667.486: CR lock succeeded on all active lanes
<br>0004.667.762:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0004.668.010:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0004.668.022: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0004.668.077: _EQ LT iter_, 4 lane(s)
<br>0004.668.756:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0004.669.313:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0004.669.331: Equalization succeeded on all active lanes
<br>0004.669.340: Symbol lock succeeded on all active lanes
<br>0004.669.346: All lanes are properly skewed
<br>0004.669.383: Source DUT completes Link Training
<br>0004.669.402: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0004.669.410: Link Training OK
<br>0004.675.595: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID5">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 4</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.4 Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
<br> 
<br>0000.000.472: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.496: Long HPD Pulse (2000 ms)
<br>GUong HPD Pulse (2000 ms)
<br>t: 400.3.1.4 Successful LT to a Lower Link Rate #2: Iterate at0003.414.806:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.415.560:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.415.580: Source DUT sets LANE_COUNT_SET = 4
<br>0003.415.589: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.415.910:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.415.926: Source DUT starts Link Training
<br>0003.415.951: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0003.416.043: _CR LT iter_, 4 lane(s)
<br>0003.416.135: Clear LANEx_x_STATUS
<br>0003.416.150: Set iteration counter to 1
<br>0003.416.391:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 00 00 00 00
<br>0003.416.617:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.416.644: Increment iteration counter to 2
<br>0003.416.679: _CR LT iter_, 4 lane(s)
<br>0003.416.772: Adjust request - voltage swing level 0
<br>0003.416.792: Clear LANEx_x_STATUS
<br>0003.417.037:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.417.262:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.417.290: Increment iteration counter to 3
<br>0003.417.324: _CR LT iter_, 4 lane(s)
<br>0003.417.416: Adjust request - voltage swing level 0
<br>0003.417.437: Clear LANEx_x_STATUS
<br>0003.417.679:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.417.904:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.417.932: Increment iteration counter to 4
<br>0003.417.966: _CR LT iter_, 4 lane(s)
<br>0003.418.059: Adjust request - voltage swing level 0
<br>0003.418.079: Clear LANEx_x_STATUS
<br>0003.418.320:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.418.545:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.418.573: Increment iteration counter to 5
<br>0003.418.606: _CR LT iter_, 4 lane(s)
<br>0003.418.700: Adjust request - voltage swing level 0
<br>0003.418.720: Clear LANEx_x_STATUS
<br>0003.418.963:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.419.169:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0004.488.581:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 00 00 00 00
<br>0004.659.192:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 02
<br>0004.659.528:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0004.660.295:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0004.660.310: Source DUT sets LINK_BW_SET = 06h
<br>0004.660.672:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0004.660.688: Source DUT starts Link Training
<br>0004.660.737: _CR LT iter_, 4 lane(s)
<br>0004.660.853: CR lock succeeded on all active lanes
<br>0004.661.121:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0004.661.365:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 22 00 00 00 00
<br>0004.661.378: Source DUT writes TRAINING_PATTERN_SET = 22h
<br>0004.661.431: _EQ LT iter_, 4 lane(s)
<br>0004.662.120:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0004.662.680:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0004.662.698: Equalization succeeded on all active lanes
<br>0004.662.708: Symbol lock succeeded on all active lanes
<br>0004.662.714: All lanes are properly skewed
<br>0004.662.752: Source DUT completes Link Training
<br>0004.662.771: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0004.662.779: Link Training OK
<br>0004.669.063: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID6">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 5</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.5 Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence
<br> 
<br>0000.000.467: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.490: Long HPD Pulse (2000 ms)
<br>0002.000.645: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>GU02.000.645: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>is and Post Cursor 2 Setting During Channel Equalization Sequence
<br> 
<br>0000.000.467: Set MAX_LINK_RATE = 14h, MAX_Lcted LINK_BW_SET = 14h
<br>0003.427.394: Source DUT supports TEST_LINK_TRAINING
<br>0003.427.402: Source DUT is ready to accept test requests at any time after plug
<br>0003.427.699:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.427.716: Source DUT starts Link Training
<br>0003.427.764: _CR LT iter_, 4 lane(s)
<br>0003.428.126:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.428.362:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.428.427: _EQ LT iter_, 4 lane(s)
<br>0003.429.090:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.429.448:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.429.463: Source DUT completes Link Training
<br>0003.432.930: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.432.948: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.432.957: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.432.980: Short HPD pulse (0.75 ms)
<br>0003.433.769: Wait for a write to TEST_RESPONSE
<br>0003.438.987: TEST_RESPONSE.TEST_ACK is set
<br>0003.439.021: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.439.304:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.446.393:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.439.555: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.440.386: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID7">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 6</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 400.3.1.6 Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension
<br> 
<br>0000.000.475: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.499: Long HPD Pulse (2000 ms)
<br>GUCOUNT = 4
<br>0000.000.499: Long HPD Pulse (2000 ms)
<br>T at Lower Link Rate Due to Loss of S0003.432.388:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.433.148:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.433.168: Source DUT sets LANE_COUNT_SET = 4
<br>0003.433.177: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.433.184: Expected LINK_BW_SET = 14h
<br>0003.433.216: Source DUT supports TEST_LINK_TRAINING
<br>0003.433.224: Source DUT is ready to accept test requests at any time after plug
<br>0003.433.507:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.433.524: Source DUT starts Link Training
<br>0003.433.573: _CR LT iter_, 4 lane(s)
<br>0003.433.935:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.434.174:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.434.239: _EQ LT iter_, 4 lane(s)
<br>0003.434.902:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.435.411:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.435.426: Source DUT completes Link Training
<br>0003.438.672: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.438.691: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.438.699: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.438.723: Short HPD pulse (0.75 ms)
<br>0003.439.512: Wait for a write to TEST_RESPONSE
<br>0003.444.794: TEST_RESPONSE.TEST_ACK is set
<br>0003.444.829: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.445.119:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.452.185:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.445.158: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.445.987: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID8">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 7</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 400.3.1.7 Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
<br> 
<br>0000.000.466: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.000.490: Long HPD Pulse (2000 ms)
<br>GUHPD Pulse (2000 ms)
<br> test: 400.3.1.7 Unsuccessful LT at Lower Link Rate #1: Iterate at0003.427.468:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.428.221:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0003.428.240: Source DUT sets LANE_COUNT_SET = 4
<br>0003.428.249: Source DUT sets LINK_BW_SET = 06h
<br>0003.428.568:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.428.584: Source DUT starts Link Training
<br>0003.428.610: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0003.428.701: _CR LT iter_, 4 lane(s)
<br>0003.428.792: Adjust request - voltage swing level 1
<br>0003.428.812: Clear LANEx_x_STATUS
<br>0003.429.056:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11
<br>0003.429.291:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 01 01 01 01
<br>0003.429.354: _CR LT iter_, 4 lane(s)
<br>0003.429.444: Adjust request - voltage swing level 2
<br>0003.429.465: Clear LANEx_x_STATUS
<br>0003.429.714:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
<br>0003.429.941:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 06 06 06 06
<br>0003.430.003: _CR LT iter_, 4 lane(s)
<br>0003.430.094: Adjust request - voltage swing level 2
<br>0003.430.114: Clear LANEx_x_STATUS
<br>0003.430.126: Set iteration counter to 1
<br>0003.430.364:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 22 22
<br>0003.430.562:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.430.582: Source DUT writes TRAINING_PATTERN_SET = 0h
<br>0003.438.628: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID9">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 8</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.8 Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
<br> 
<br>0000.000.469: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.000.494: Long HPD Pulse (2000 ms)
<br>0002.001.159: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.445.444:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.446.208:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0003.446.228: Source DUT sets LANE_COUNT_SET = 4
<br>0003.446.237: Source DUT sets LINK_BW_SET = 06h
<br>0003.446.577:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.446.593: Source DUT starts Link Training
<br>0003.446.619: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0003.446.710: _CR LT iter_, 4 lane(s)
<br>0003.446.800: Adjust request - voltage swing level 0
<br>0003.446.820: Clear LANEx_x_STATUS
<br>0003.446.833: Set iteration counter to 1
<br>0003.447.084:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.447.322:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.447.351: Increment iteration counter to 2
<br>0003.447.384: _CR LT iter_, 4 lane(s)
<br>0003.447.475: Adjust request - voltage swing level 0
<br>0003.447.495: Clear LANEx_x_STATUS
<br>0003.447.758:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.447.994:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.448.023: Increment iteration counter to 3
<br>0003.448.057: _CR LT iter_, 4 lane(s)
<br>0003.448.149: Adjust request - voltage swing level 0
<br>0003.448.168: Clear LANEx_x_STATUS
<br>0003.448.428:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.448.666:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.448.695: Increment iteration counter to 4
<br>0003.448.727: _CR LT iter_, 4 lane(s)
<br>0003.448.819: Adjust request - voltage swing level 0
<br>0003.448.839: Clear LANEx_x_STATUS
<br>0003.449.105:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.449.341:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 00 00 00 00
<br>0003.449.368: Increment iteration counter to 5
<br>0003.449.403: _CR LT iter_, 4 lane(s)
<br>0003.449.493: Adjust request - voltage swing level 0
<br>0003.449.513: Clear LANEx_x_STATUS
<br>0003.449.776:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00
<br>0003.449.996:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.450.016: Source DUT writes TRAINING_PATRN_SET = 00h
<br>0003.450.055: Source DUT terminates link training after 5 iterations
<br>0003.457.365: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID10">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 9</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 400.3.1.9 Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension
<br> 
<br>0000.000.473: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.000.496: Long HPD Pulse (2000 ms)
<br>0002.001.239: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.440.766:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.441.527:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0003.441.546: Source DUT sets LANE_COUNT_SET = 4
<br>0003.441.555: Source DUT sets LINK_BW_SET = 06h
<br>0003.441.890:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.441.906: Source DUT starts Link Training
<br>0003.441.930: Source DUT writes TRAINING_PATTERN_SET = 21h
<br>0003.441.993: _CR LT iter_, 4 lane(s)
<br>0003.442.106: CR lock succeeded on all active lanes
<br>0003.442.368:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.442.609:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.442.622: Source DUT writes TRAINING_PATTERN_SET = 23h
<br>0003.442.708: _EQ LT iter_, 4 lane(s)
<br>0003.442.888: Set LANEx_x_STATUS = 1111h
<br>0003.443.344:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 44 44
<br>0003.443.579:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 08 08 08 08
<br>0003.443.659: _EQ LT iter_, 4 lane(s)
<br>0003.443.788: Set LANEx_x_STATUS = 1111h
<br>0003.444.306:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 88 88
<br>0003.444.540:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 10 10 10 10
<br>0003.444.558: Set iteration counter to 2
<br>0003.444.660: _EQ LT iter_, 4 lane(s)
<br>0003.444.786: Set LANEx_x_STATUS = 1111h
<br>0003.445.268:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 CC CC
<br>0003.445.503:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 38 38 38 38
<br>0003.445.520: Set iteration counter to 3
<br>0003.445.573: _EQ LT iter_, 4 lane(s)
<br>0003.445.700: Set LANEx_x_STATUS = 1111h
<br>0003.446.230:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 CC CC
<br>0003.446.464:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 38 38 38 38
<br>0003.446.492: Increment iteration counter to 4
<br>0003.446.527: _EQ LT iter_, 4 lane(s)
<br>0003.446.655: Set LANEx_x_STATUS = 1111h
<br>0003.447.207:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 CC CC
<br>0003.447.441:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 4&nbsp&nbsp 38 38 38 38
<br>0003.447.469: Increment iteration counter to 5
<br>0003.447.502: _EQ LT iter_, 4 lane(s)
<br>0003.447.629: Set LANEx_x_STATUS = 1111h
<br>0003.447.938:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.447.952: Source DUT completes Link Training
<br>0003.447.967: Source DUT writes TRAINING_PATRN_SET = 00h
<br>0003.448.006: Source DUT terminates link training after 5 iterations
<br>0003.453.582: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID11">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 10</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(700.1.1.1) Additional DPCD Handling Test 1</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 700.1.1.1 Additional DPCD Handling Test 1
<br> 
<br>0000.000.509: Set DPCD_REV = 12h
<br>0000.000.520: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.537: Set DOWNSTREAMPORT_PRESENT = 11h
<br>0000.000.543: Set DOWN_STREAM_PORT_COUNT = 01h
<br>0000.000.549: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
<br>0000.000.581: Long HPD Pulse (2000 ms)
<br>0002.001.267: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
<br>0003.415.141:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.415.893:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.416.234:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.416.250: Source DUT starts Link Training
<br>0003.416.299: _CR LT iter_, 4 lane(s)
<br>0003.416.650:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.416.881:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.416.945: _EQ LT iter_, 4 lane(s)
<br>0003.417.593:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.417.939:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.417.957: Equalization succeeded on all active lanes
<br>0003.417.966: Symbol lock succeeded on all active lanes
<br>0003.417.972: All lanes are properly skewed
<br>0003.417.988: Source DUT completes Link Training
<br>0003.668.467: Source DUT reads EDID, performs Link Training and transmits video stream
<br>0003.670.342: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID12">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 11</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(700.1.1.2) Additional DPCD Handling Test 2</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 700.1.1.2 Additional DPCD Handling Test 2
<br> 
<br>0000.000.509: Set DPCD_REV = 13h
<br>0000.000.525: Set MAX_LINK_RATE = 1Eh, MAX_LANE_COUNT = 4
<br>0000.000.548: Set DOWNSTREAMPORT_PRESENT = 11h
<br>0000.000.554: Set DOWN_STREAM_PORT_COUNT = 01h
<br>0000.000.560: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
<br>0000.000.591: Long HPD Pulse (2000 ms)
<br>0002.001.408: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
<br>0003.417.610:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.418.365:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.418.713:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.418.730: Source DUT starts Link Training
<br>0003.418.778: _CR LT iter_, 4 lane(s)
<br>0003.419.133:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.419.364:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.419.429: _EQ LT iter_, 4 lane(s)
<br>0003.420.080:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.420.429:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.420.448: Equalization succeeded on all active lanes
<br>0003.420.457: Symbol lock succeeded on all active lanes
<br>0003.420.464: All lanes are properly skewed
<br>0003.420.478: Source DUT completes Link Training
<br>0003.637.614: Source DUT reads EDID, performs Link Training and transmits video stream
<br>0003.639.181: -------------------------------------------------------------
<br> 
<br>0003.639.773: Set DPCD_REV = 20h
<br>0003.639.790: Set MAX_LINK_RATE = 20h, MAX_LANE_COUNT = 4
<br>0003.639.814: Set DOWNSTREAMPORT_PRESENT = 11h
<br>0003.639.820: Set DOWN_STREAM_PORT_COUNT = 01h
<br>0003.639.825: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
<br>0003.639.856: Long HPD Pulse (2000 ms)
<br>0005.640.416: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
<br>0007.080.473:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0007.081.234:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0007.081.593:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0007.081.609: Source DUT starts Link Training
<br>0007.081.658: _CR LT iter_, 4 lane(s)
<br>0007.082.026:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0007.082.268:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0007.082.333: _EQ LT iter_, 4 lane(s)
<br>0007.082.991:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0007.083.506:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0007.083.524: Equalization succeeded on all active lanes
<br>0007.083.533: Symbol lock succeeded on all active lanes
<br>0007.083.540: All lanes are properly skewed
<br>0007.083.555: Source DUT completes Link Training
<br>0007.317.652: Source DUT reads EDID, performs Link Training and transmits video stream
<br>0007.319.211: -------------------------------------------------------------
<br> 
<br>0007.319.808: Set DPCD_REV = 21h
<br>0007.319.825: Set MAX_LINK_RATE = 28h, MAX_LANE_COUNT = 4
<br>0007.319.847: Set DOWNSTREAMPORT_PRESENT = 11h
<br>0007.319.853: Set DOWN_STREAM_PORT_COUNT = 01h
<br>0007.319.859: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
<br>0007.319.890: Long HPD Pulse (2000 ms)
<br>0009.320.399: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
<br>0010.759.835:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0010.760.598:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0010.760.960:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0010.760.976: Source DUT starts Link Training
<br>0010.761.027: _CR LT iter_, 4 lane(s)
<br>0010.761.388:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0010.761.626:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0010.761.692: _EQ LT iter_, 4 lane(s)
<br>0010.762.351:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0010.762.863:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0010.762.880: Equalization succeeded on all active lanes
<br>0010.762.889: Symbol lock succeeded on all active lanes
<br>0010.762.896: All lanes are properly skewed
<br>0010.762.910: Source DUT completes Link Training
<br>0010.980.629: Source DUT reads EDID, performs Link Training and transmits video stream
<br>0010.982.212: -------------------------------------------------------------
<br> 
<br>0010.982.815: Set DPCD_REV = 17h
<br>0010.982.832: Set MAX_LINK_RATE = 15h, MAX_LANE_COUNT = 4
<br>0010.982.854: Set DOWNSTREAMPORT_PRESENT = 11h
<br>0010.982.860: Set DOWN_STREAM_PORT_COUNT = 01h
<br>0010.982.865: Set RECEIVER_PORT0_CAP_0&nbsp&nbsp = 08h
<br>0010.982.896: Long HPD Pulse (2000 ms)
<br>0012.983.410: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
<br>0014.406.215:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0014.406.962:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0014.407.299:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0014.407.316: Source DUT starts Link Training
<br>0014.407.365: _CR LT iter_, 4 lane(s)
<br>0014.407.715:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0014.407.942:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0014.408.010: _EQ LT iter_, 4 lane(s)
<br>0014.408.652:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0014.409.153:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0014.409.171: Equalization succeeded on all active lanes
<br>0014.409.180: Symbol lock succeeded on all active lanes
<br>0014.409.187: All lanes are properly skewed
<br>0014.409.203: Source DUT completes Link Training
<br>0014.642.652: Source DUT reads EDID, performs Link Training and transmits video stream
<br>0014.644.803: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID13">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 12</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.12 Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing
<br> 
<br>0000.000.475: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.499: Long HPD Pulse (2000 ms)
<br>0002.001.039: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.421.173:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.421.926:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.421.957: Source DUT sets LANE_COUNT_SET = 4
<br>0003.421.966: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.421.972: Expected LINK_BW_SET = 14h
<br>0003.422.005: Source DUT supports TEST_LINK_TRAINING
<br>0003.422.013: Source DUT is ready to accept test requests at any time after plug
<br>0003.422.276:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.422.292: Source DUT starts Link Training
<br>0003.422.341: _CR LT iter_, 4 lane(s)
<br>0003.422.700:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.422.935:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.423.001: _EQ LT iter_, 4 lane(s)
<br>0003.423.655:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.424.009:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.424.024: Source DUT completes Link Training
<br>0003.427.510: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.427.529: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.427.537: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.427.561: Short HPD pulse (0.75 ms)
<br>0003.428.349: Wait for a write to TEST_RESPONSE
<br>0003.433.631: TEST_RESPONSE.TEST_ACK is set
<br>0003.433.666: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.433.946:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.440.691:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.433.991: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.434.828: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID14">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 13</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 400.3.1.13 Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing
<br> 
<br>0000.000.476: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.500: Long HPD Pulse (2000 ms)
<br>0002.000.809: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.427.724:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.428.471:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.428.491: Source DUT sets LANE_COUNT_SET = 4
<br>0003.428.499: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.428.506: Expected LINK_BW_SET = 14h
<br>0003.428.538: Source DUT supports TEST_LINK_TRAINING
<br>0003.428.546: Source DUT is ready to accept test requests at any time after plug
<br>0003.428.814:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.428.830: Source DUT starts Link Training
<br>0003.428.880: _CR LT iter_, 4 lane(s)
<br>0003.429.232:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.429.465:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.429.530: _EQ LT iter_, 4 lane(s)
<br>0003.430.178:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.430.532:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.430.547: Source DUT completes Link Training
<br>0003.433.981: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.434.000: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.434.008: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.434.032: Short HPD pulse (0.75 ms)
<br>0003.434.820: Wait for a write to TEST_RESPONSE
<br>0003.440.176: TEST_RESPONSE.TEST_ACK is set
<br>0003.440.210: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.440.525:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.448.080:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.440.764: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.441.596: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID15">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 14</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.1.14 Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR
<br> 
<br>0000.000.485: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.508: Long HPD Pulse (2000 ms)
<br>0002.001.287: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.429.627:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.430.396:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.430.415: Source DUT sets LANE_COUNT_SET = 4
<br>0003.430.423: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.430.430: Expected LINK_BW_SET = 14h
<br>0003.430.462: Source DUT supports TEST_LINK_TRAINING
<br>0003.430.470: Source DUT is ready to accept test requests at any time after plug
<br>0003.430.754:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.430.771: Source DUT starts Link Training
<br>0003.430.820: _CR LT iter_, 4 lane(s)
<br>0003.431.179:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.431.416:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.431.482: _EQ LT iter_, 4 lane(s)
<br>0003.432.141:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.432.502:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.432.517: Source DUT completes Link Training
<br>0003.436.737: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.436.756: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.436.764: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.436.788: Short HPD pulse (0.75 ms)
<br>0003.437.576: Wait for a write to TEST_RESPONSE
<br>0003.443.015: TEST_RESPONSE.TEST_ACK is set
<br>0003.443.049: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.443.335:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.449.745:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.443.238: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.444.067: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID16">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 15</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 400.3.1.15 Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences
<br> 
<br>0000.000.486: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.510: Long HPD Pulse (2000 ms)
<br>0002.001.377: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.423.990:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.424.749:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.424.770: Source DUT sets LANE_COUNT_SET = 4
<br>0003.424.778: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.424.785: Expected LINK_BW_SET = 14h
<br>0003.424.817: Source DUT supports TEST_LINK_TRAINING
<br>0003.424.825: Source DUT is ready to accept test requests at any time after plug
<br>0003.425.118:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.425.135: Source DUT starts Link Training
<br>0003.425.184: _CR LT iter_, 4 lane(s)
<br>0003.425.550:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.425.786:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.425.851: _EQ LT iter_, 4 lane(s)
<br>0003.426.513:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.426.874:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.426.888: Source DUT completes Link Training
<br>0003.430.362: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.430.380: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.430.389: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.430.412: Short HPD pulse (0.75 ms)
<br>0003.431.203: Wait for a write to TEST_RESPONSE
<br>0003.436.479: TEST_RESPONSE.TEST_ACK is set
<br>0003.436.514: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.436.793:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.443.446:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.437.291: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.438.123: Test FAILED, step 6, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID17">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 16</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.2.1 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension
<br> 
<br>0000.000.479: Test lane 1
<br>0000.000.549: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.573: Long HPD Pulse (2000 ms)
<br>0002.001.392: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.425.349:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.426.104:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.426.124: Source DUT sets LANE_COUNT_SET = 4
<br>0003.426.134: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.426.140: Expected LINK_BW_SET = 14h
<br>0003.426.172: Source DUT supports TEST_LINK_TRAINING
<br>0003.426.180: Source DUT is ready to accept test requests at any time after plug
<br>0003.426.451:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.426.467: Source DUT starts Link Training
<br>0003.426.516: _CR LT iter_, 4 lane(s)
<br>0003.426.870:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.427.105:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.427.170: _EQ LT iter_, 4 lane(s)
<br>0003.427.826:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.428.176:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.428.191: Source DUT completes Link Training
<br>0003.432.463: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.432.482: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.432.490: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.432.514: Short HPD pulse (0.75 ms)
<br>0003.433.302: Wait for a write to TEST_RESPONSE
<br>0003.438.451: TEST_RESPONSE.TEST_ACK is set
<br>0003.438.485: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.438.765:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.444.895:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.439.386: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.440.576: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID18">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 17</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 400.3.2.2 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension
<br> 
<br>0000.000.481: Test lane 1
<br>0000.000.551: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.574: Long HPD Pulse (2000 ms)
<br>0002.001.297: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.427.022:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.427.777:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.427.799: Source DUT sets LANE_COUNT_SET = 4
<br>0003.427.808: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.427.815: Expected LINK_BW_SET = 14h
<br>0003.427.846: Source DUT supports TEST_LINK_TRAINING
<br>0003.427.854: Source DUT is ready to accept test requests at any time after plug
<br>0003.428.129:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.428.146: Source DUT starts Link Training
<br>0003.428.194: _CR LT iter_, 4 lane(s)
<br>0003.428.553:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.428.788:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.428.853: _EQ LT iter_, 4 lane(s)
<br>0003.429.509:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.429.860:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.429.874: Source DUT completes Link Training
<br>0003.434.130: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.434.148: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.434.157: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.434.180: Short HPD pulse (0.75 ms)
<br>0003.434.969: Wait for a write to TEST_RESPONSE
<br>0003.440.253: TEST_RESPONSE.TEST_ACK is set
<br>0003.440.287: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.440.574:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.446.860:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.441.275: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.442.466: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID19">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 18</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 400.3.2.3 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension
<br> 
<br>0000.000.484: Test lane 1
<br>0000.000.554: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
<br>0000.000.577: Long HPD Pulse (2000 ms)
<br>0002.001.206: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.424.318:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.425.075:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.425.097: Source DUT sets LANE_COUNT_SET = 4
<br>0003.425.106: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.425.118: Expected LINK_BW_SET = 14h
<br>0003.425.149: Source DUT supports TEST_LINK_TRAINING
<br>0003.425.157: Source DUT is ready to accept test requests at any time after plug
<br>0003.425.430:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.425.447: Source DUT starts Link Training
<br>0003.425.495: _CR LT iter_, 4 lane(s)
<br>0003.425.856:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.426.090:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.426.155: _EQ LT iter_, 4 lane(s)
<br>0003.426.809:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.427.163:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.427.178: Source DUT completes Link Training
<br>0003.430.584: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h 
<br>0003.430.602: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.430.611: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.430.634: Short HPD pulse (0.75 ms)
<br>0003.431.423: Wait for a write to TEST_RESPONSE
<br>0003.436.633: TEST_RESPONSE.TEST_ACK is set
<br>0003.436.667: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.436.949:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.443.301:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.437.149: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.438.333: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID20">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 19</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(400.3.3.1) Video Time Stamp Generation</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 400.3.3.1 Video Time Stamp Generation
<br> 
<br>0000.000.511: Configure EDID for the test
<br>0000.000.520: Setup EDID with one block of data (128 bytes)
<br>0000.000.528: Configure EDID for video mode 1920x1080@60Hz 24 bpp
<br>0000.000.589: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.000.612: Long HPD Pulse (2000 ms)
<br>0002.000.880: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.407.806:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.408.571:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 84
<br>0003.408.592: Source DUT sets LANE_COUNT_SET = 4
<br>0003.408.601: Source DUT sets LINK_BW_SET = 06h
<br>0003.408.634: Source DUT supports TEST_LINK_TRAINING
<br>0003.408.642: Source DUT is ready to accept test requests at any time after plug
<br>0003.408.951:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.408.967: Source DUT starts Link Training
<br>0003.409.016: _CR LT iter_, 4 lane(s)
<br>0003.409.401:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.409.647:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 23 00 00 00 00
<br>0003.409.712: _EQ LT iter_, 4 lane(s)
<br>0003.410.392:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.410.935:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.410.950: Source DUT completes Link Training
<br>0003.414.279: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
<br>0003.414.297: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.414.305: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.414.329: Short HPD pulse (0.75 ms)
<br>0003.415.117: Wait for a write to TEST_RESPONSE
<br>0003.420.452: TEST_RESPONSE.TEST_ACK is set
<br>0003.420.486: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.420.777:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.427.516:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.420.844: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.519.825: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID21">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 20</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.1.1 Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
<br> 
<br>0000.000.486: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.509: Long HPD Pulse (2000 ms)
<br>0002.001.343: Reference Sink is set not to respond to any AUX request
<br>0002.001.387: Waiting for AUX request ...
<br>0002.103.809: First AUX request received
<br>0002.103.815: Reference Sink does not send any reply to AUX request
<br>0002.103.842: Waiting for 1ms to simulate the Sink device wake-up timeout period ...
<br>0002.105.113: 1ms timeout elapsed
<br>0002.105.129: Reference Sink is set to respond to AUX requests normally
<br>0002.105.156: Waiting for another AUX request ...
<br>0002.105.469: AUX request received after 1ms wake-up timeout
<br>0002.107.387: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID22">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 21</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.1.2 Source Retry on Invalid Reply During AUX Read after HPD Plug Event
<br> 
<br>0000.000.479: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.503: Long HPD Pulse (2000 ms)
<br>0002.001.009: Reference Sink is set to send partial reply to AUX request
<br>0002.001.052: Waiting for AUX request ...
<br>0002.103.784: First AUX request received
<br>0002.103.799: Reference Sink is set to respond to AUX requests normally
<br>0002.103.809: Reference Sink sends a partial AUX reply
<br>0002.103.829: Waiting for another AUX request ...
<br>0002.104.405: New AUX request received
<br>0002.106.597: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID23">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 22</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.1) EDID Read upon HPD Plug Event</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.2.1 EDID Read upon HPD Plug Event
<br> 
<br>0000.000.505: Setup EDID with one block of data (128 bytes)
<br>0000.098.541: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.098.565: Long HPD Pulse (2000 ms)
<br>0002.098.901: Source DUT does not disable main link transmission, ignore and continue
<br>0002.098.969: Waiting for Source DUT to read entire EDID block ...
<br>0002.206.142: Source DUT reads EDID
<br>0002.305.071: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID24">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 23</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
<br> 
<br>0000.000.482: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.506: Long HPD Pulse (2000 ms)
<br>GU00.000.011: Starting test: 4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
<br> 
<br>0000.000.482: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.506: Long 0002.103.148: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
<br>0002.104.175: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID25">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 24</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.3) EDID Read</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.2.3 EDID Read
<br> 
<br>0000.000.515: Setup EDID with one block of data (128 bytes, single timing)
<br>0000.000.633: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.656: Long HPD Pulse (2000 ms)
<br>0002.001.269: Source DUT does not disable main link transmission, ignore and continue
<br>0002.001.346: Set TEST_REQUEST.TEST_EDID_READ = 1
<br>0002.001.356: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0002.001.392: Waiting for Source DUT to read entire EDID block ...
<br>0002.108.311: Source DUT reads EDID
<br>0002.108.342: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
<br>0002.109.680: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
<br>0002.109.692: TEST_EDID_CHECKSUM field matches expected checksum
<br>0002.109.723: Waiting for requested video ...
<br>0003.416.414:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.417.189:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.417.543:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.417.557: Source DUT starts Link Training
<br>0003.417.613: _CR LT iter_, 1 lane(s)
<br>0003.418.000:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.418.218:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
<br>0003.418.285: _EQ LT iter_, 1 lane(s)
<br>0003.418.971:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.419.499:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.419.514: Source DUT completes Link Training
<br>0003.671.603: Source DUT transmits requested video timing or fail-safe mode
<br>0003.771.609: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID26">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 25</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.010: Starting test: 4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK
<br> 
<br>0000.000.498: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.521: Long HPD Pulse (2000 ms)
<br>GU00.000.010: Starting test: 4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK
<br> 
<br>0000.000.498: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.521: Long HPD Pulse (2000 ms)
<br> 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00002.000.778: Set TEST_REQUEST.TEST_EDID_READ = 1
<br>0002.000.788: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0002.000.842: Waiting for fail-safe mode ...
<br>0002.103.930: Source DUT attempts to read EDID
<br>0003.400.236:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.401.010:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
<br>0003.401.369:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
<br>0003.401.383: Source DUT starts Link Training
<br>0003.401.437: _CR LT iter_, 2 lane(s)
<br>0003.401.822:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
<br>0003.402.049:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00
<br>0003.402.117: _EQ LT iter_, 2 lane(s)
<br>0003.402.798:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
<br>0003.403.340:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.403.354: Source DUT completes Link Training
<br>0007.001.877:&nbsp&nbsp Received 1344 Htotal differs from fail-safe 800
<br>0007.001.882:&nbsp&nbsp Received 1024 Hactive differs from fail-safe 640
<br>0007.001.888:&nbsp&nbsp Received 296 Hstart differs from fail-safe 144
<br>0007.001.895:&nbsp&nbsp Received 136 Hsync width differs from fail-safe 96
<br>0007.001.901:&nbsp&nbsp Received 806 Vtotal differs from fail-safe 525
<br>0007.001.908:&nbsp&nbsp Received 768 Vactive differs from fail-safe 480
<br>0007.001.914:&nbsp&nbsp Received 6 Vsync width differs from fail-safe 2
<br>0007.001.920: WARNING: Source DUT does not transmit fail-safe video mode
<br>0007.006.314: Reference Sink is set to respond normally to I2C over AUX requests
<br>0007.006.866: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID27">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 26</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.2.5 EDID Read Failure #2: I2C-Over-AUX DEFER
<br> 
<br>0000.000.501: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.524: Long HPD Pulse (2000 ms)
<br>0002.000.781: Source DUT does not disable main link transmission, ignore and continue
<br>0002.000.817: Reference Sink is set to respond with I2C over AUX DEFER to requests with 0x60 and 0xA0 I2C address
<br>0002.000.868: Set TEST_REQUEST.TEST_EDID_READ = 1
<br>0002.000.879: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0002.000.933: Waiting for fail-safe mode ...
<br>0002.104.532: Source DUT attempts to read EDID
<br>0003.627.417:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.628.181:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
<br>0003.628.530:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
<br>0003.628.545: Source DUT starts Link Training
<br>0003.628.597: _CR LT iter_, 2 lane(s)
<br>0003.628.975:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
<br>0003.629.199:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00
<br>0003.629.267: _EQ LT iter_, 2 lane(s)
<br>0003.629.946:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
<br>0003.630.484:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.630.499: Source DUT completes Link Training
<br>0007.001.898:&nbsp&nbsp Received 1344 Htotal differs from fail-safe 800
<br>0007.001.904:&nbsp&nbsp Received 1024 Hactive differs from fail-safe 640
<br>0007.001.913:&nbsp&nbsp Received 296 Hstart differs from fail-safe 144
<br>0007.001.920:&nbsp&nbsp Received 136 Hsync width differs from fail-safe 96
<br>0007.001.926:&nbsp&nbsp Received 806 Vtotal differs from fail-safe 525
<br>0007.001.933:&nbsp&nbsp Received 768 Vactive differs from fail-safe 480
<br>0007.001.939:&nbsp&nbsp Received 6 Vsync width differs from fail-safe 2
<br>0007.001.945: WARNING: Source DUT does not transmit fail-safe video mode
<br>0007.006.386: Reference Sink is set to respond normally to I2C over AUX requests
<br>0007.006.946: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID28">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 27</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.6) EDID Corruption Detection</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 4.2.2.6 EDID Corruption Detection
<br> 
<br>0000.000.520: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.543: Long HPD Pulse (2000 ms)
<br>0000.000.572: Reference Sink sets up EDID with incorrect checksum
<br>0002.000.611: Source DUT does not disable main link, ignore and continue
<br>0002.000.687: Set TEST_REQUEST.TEST_EDID_READ = 1
<br>0002.000.697: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0002.000.732: Waiting for Source DUT to read entire EDID block ...
<br>0002.106.934: Source DUT reads EDID
<br>0002.106.966: Waiting for fail-safe video ...
<br>0003.407.013:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.407.799:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82
<br>0003.408.152:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00
<br>0003.408.166: Source DUT starts Link Training
<br>0003.408.221: _CR LT iter_, 2 lane(s)
<br>0003.408.608:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00
<br>0003.408.837:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00
<br>0003.408.905: _EQ LT iter_, 2 lane(s)
<br>0003.409.585:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00
<br>0003.410.125:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.410.139: Source DUT completes Link Training
<br>0003.660.870: Source DUT starts video stream
<br>0008.661.741:&nbsp&nbsp Received 1344 Htotal differs from fail-safe 800
<br>0008.661.747:&nbsp&nbsp Received 1024 Hactive differs from fail-safe 640
<br>0008.661.753:&nbsp&nbsp Received 296 Hstart differs from fail-safe 144
<br>0008.661.760:&nbsp&nbsp Received 136 Hsync width differs from fail-safe 96
<br>0008.661.766:&nbsp&nbsp Received 806 Vtotal differs from fail-safe 525
<br>0008.661.772:&nbsp&nbsp Received 768 Vactive differs from fail-safe 480
<br>0008.661.778:&nbsp&nbsp Received 6 Vsync width differs from fail-safe 2
<br>0008.661.785: Source DUT does not transmit fail-safe video mode
<br>0008.666.275: Reference Sink restores EDID checksum
<br>0008.667.014: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID29">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 28</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.7) Branch Device Detection upon HPD Plug Event</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 4.2.2.7 Branch Device Detection upon HPD Plug Event
<br> 
<br>0000.000.495: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.519: Long HPD Pulse (2000 ms)
<br>GU00.000.012: Starting test: 4.2.2.7 Branch Device Detection upon HPD Plug Event
<br> 
<br>0000.000.495: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.519: Long HPD Pulse (2000 ms)
<br>Test FAILED, step 7,ets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
<br>0002.001.301: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
<br>0002.001.307: Reference Sink sets SINK_COUNT.SINK_COUNT = 01h
<br>0002.001.376: Waiting for Source DUT to read DPCD Receiver Capability field ...
<br>0002.104.175: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
<br>0002.104.210: Start five second timer
<br>0002.104.643: Source DUT reads Link Sink Status field SINK_COUNT (DPCD:00200h)
<br>0002.105.933: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID30">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 29</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.2.8 EDID Read on IRQ HPD Event after Branch Device Detection
<br> 
<br>0000.000.491: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.514: Long HPD Pulse (2000 ms)
<br>0002.000.698: Source DUT does not disable main link transmission, ignore and continue
<br>0002.000.731: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_PRESENT = 1b
<br>0002.000.738: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
<br>0002.000.745: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
<br>0002.000.750: Reference Sink sets SINK_COUNT.SINK_COUNT = 0h
<br>0002.000.820: Waiting for Source DUT to read DPCD Receiver Capability field ...
<br>0002.103.477: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
<br>0002.103.514: Waiting for two seconds ...
<br>0004.103.753: Reference Sink sets SINK_COUNT.SINK_COUNT = 1h
<br>0004.103.760: Reference Sink sets LANE_ALIGN_STATUS_UPDATED.DOWNSTREAM_PORT_STATUS_CHANGED = 1h
<br>0004.104.718: Short HPD pulse (0.75 ms)
<br>0004.105.506: Waiting for Source DUT to read EDID ...
<br>0004.115.258: Source DUT starts reading EDID
<br>0004.116.220: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID31">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 30</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.2.2.9) E-DDC Four Block EDID Read</p>
<p class="BODYTEXT">
Test Result: <b>PASSED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.2.2.9 E-DDC Four Block EDID Read
<br> 
<br>0000.000.513: Setup EDID with four block of data (512 bytes)
<br>0000.098.606: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.098.629: Long HPD Pulse (2000 ms)
<br>0002.098.935: Source DUT does not disable main link transmission, ignore and continue
<br>0002.099.006: Set TEST_REQUEST.TEST_EDID_READ = 1
<br>0002.099.016: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0002.099.051: Waiting for Source DUT to read entire EDID block ...
<br>0002.214.388: Source DUT reads EDID
<br>0002.214.418: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
<br>0002.215.737: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
<br>0002.215.749: TEST_EDID_CHECKSUM field matches expected checksum
<br>0002.314.892: Test PASSED
<br> 
<br>
<br><br></p></div><div id="ID32">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 31</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.3.2.4 Handling of IRQ HPD Pulse with No Error Status Bits Set
<br> 
<br>0000.000.533: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.556: Long HPD Pulse (2000 ms)
<br>GU00.000.011: Starting test: 4.3.2.4 Handling of IRQ HPD Pulse with No Error Status Bits0003.441.625:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.442.392:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.442.410: Source DUT sets LANE_COUNT_SET = 4
<br>0003.442.419: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.442.452: Source DUT supports TEST_LINK_TRAINING
<br>0003.442.460: Source DUT is ready to accept test requests at any time after plug
<br>0003.442.762:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.442.778: Source DUT starts Link Training
<br>0003.442.827: _CR LT iter_, 4 lane(s)
<br>0003.443.203:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.443.446:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 22 00 00 00 00
<br>0003.443.511: _EQ LT iter_, 4 lane(s)
<br>0003.444.180:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.444.549:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.444.563: Source DUT completes Link Training
<br>0003.448.492: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h 
<br>0003.448.511: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.448.519: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.448.543: Short HPD pulse (0.75 ms)
<br>0003.449.331: Wait for a write to TEST_RESPONSE
<br>0003.454.723: TEST_RESPONSE.TEST_ACK is set
<br>0003.454.758: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.455.047:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.461.701:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.455.700: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.456.892: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID33">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 32</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.3.2.5) Lane Count Reduction</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.012: Starting test: 4.3.2.5 Lane Count Reduction
<br> 
<br>0000.001.727: Configure EDID for the test
<br>0000.001.737: Setup EDID with one block of data (128 bytes)
<br>0000.001.745: Configure EDID for video mode 640x480@60Hz 18 bpp
<br>0000.001.807: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.001.830: Long HPD Pulse (2000 ms)
<br>0002.002.037: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.391.315:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.392.078:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.392.100: Source DUT sets LANE_COUNT_SET = 1
<br>0003.392.108: Expected LANE_COUNT_SET = 4
<br>0003.392.115: Source DUT sets LINK_BW_SET = 06h
<br>0003.392.147: Source DUT supports TEST_LINK_TRAINING
<br>0003.392.155: Source DUT is ready to accept test requests at any time after plug
<br>0003.392.434:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.392.448: Source DUT starts Link Training
<br>0003.392.503: _CR LT iter_, 1 lane(s)
<br>0003.392.878:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.393.093:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
<br>0003.393.162: _EQ LT iter_, 1 lane(s)
<br>0003.393.831:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.394.369:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.394.383: Source DUT completes Link Training
<br>0003.397.469: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
<br>0003.397.488: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.397.496: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.397.520: Short HPD pulse (0.75 ms)
<br>0003.398.308: Wait for a write to TEST_RESPONSE
<br>0003.403.702: TEST_RESPONSE.TEST_ACK is set
<br>0003.403.737: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.404.031:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
<br>0004.411.126:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
<br>0018.403.999: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.502.941: Test FAILED, step 8, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID34">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 33</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.3.2.6) Lane Count Increase</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.3.2.6 Lane Count Increase
<br> 
<br>0000.001.704: Configure EDID for the test
<br>0000.001.713: Setup EDID with one block of data (128 bytes)
<br>0000.001.721: Configure EDID for video mode 640x480@60Hz 18 bpp
<br>0000.001.781: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.001.804: Long HPD Pulse (2000 ms)
<br>0002.002.467: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.401.586:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.402.360:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.402.379: Source DUT sets LANE_COUNT_SET = 1
<br>0003.402.392: Expected LANE_COUNT_SET = 4
<br>0003.402.398: Source DUT sets LINK_BW_SET = 06h
<br>0003.402.430: Source DUT supports TEST_LINK_TRAINING
<br>0003.402.438: Source DUT is ready to accept test requests at any time after plug
<br>0003.402.708:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.402.722: Source DUT starts Link Training
<br>0003.402.777: _CR LT iter_, 1 lane(s)
<br>0003.403.160:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.403.379:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
<br>0003.403.448: _EQ LT iter_, 1 lane(s)
<br>0003.404.127:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.404.671:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.404.685: Source DUT completes Link Training
<br>0003.407.677: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
<br>0003.407.696: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.407.704: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.407.728: Short HPD pulse (0.75 ms)
<br>0003.408.515: Wait for a write to TEST_RESPONSE
<br>0003.413.912: TEST_RESPONSE.TEST_ACK is set
<br>0003.413.947: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.414.249:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
<br>0004.421.922:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
<br>0018.414.414: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.513.355: Test FAILED, step 8, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID35">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 34</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.4.1.1) Data Packing and Steering</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.4.1.1 Data Packing and Steering
<br> 
<br>0000.000.525: Setup EDID with one block of data (128 bytes)
<br>0000.000.536: Configure EDID for video mode 640x480@60Hz 18 bpp
<br>0000.000.688: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
<br>0000.000.712: Long HPD Pulse (2000 ms)
<br>0002.001.228: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.400.676:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.401.449:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.401.469: Source DUT sets LANE_COUNT_SET = 1
<br>0003.401.477: Expected LANE_COUNT_SET = 4
<br>0003.401.484: Source DUT sets LINK_BW_SET = 06h
<br>0003.401.516: Source DUT supports TEST_LINK_TRAINING
<br>0003.401.523: Source DUT is ready to accept test requests at any time after plug
<br>0003.401.800:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.401.814: Source DUT starts Link Training
<br>0003.401.869: _CR LT iter_, 1 lane(s)
<br>0003.402.249:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.402.469:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
<br>0003.402.538: _EQ LT iter_, 1 lane(s)
<br>0003.403.218:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.403.761:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.403.774: Source DUT completes Link Training
<br>0003.406.766: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h 
<br>0003.406.785: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.406.793: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.406.818: Short HPD pulse (0.75 ms)
<br>0003.407.606: Wait for a write to TEST_RESPONSE
<br>0003.412.967: TEST_RESPONSE.TEST_ACK is set
<br>0003.413.001: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.413.301:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
<br>0004.420.206:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
<br>0018.413.174: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.512.129: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID36">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 35</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.4.1.2 Main Stream Data Packing and Stuffing - Least Packed TU
<br> 
<br>0000.000.523: Setup EDID with one block of data (128 bytes)
<br>0000.000.534: Configure EDID for video mode 640x480@60Hz 18 bpp
<br>0000.000.686: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.709: Long HPD Pulse (2000 ms)
<br>0002.001.027: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.404.275:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.405.049:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.405.068: Source DUT sets LANE_COUNT_SET = 1
<br>0003.405.077: Expected LANE_COUNT_SET = 4
<br>0003.405.083: Source DUT sets LINK_BW_SET = 06h
<br>0003.405.090: Expected LINK_BW_SET = 0Ah
<br>0003.405.121: Source DUT supports TEST_LINK_TRAINING
<br>0003.405.129: Source DUT is ready to accept test requests at any time after plug
<br>0003.405.399:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.405.413: Source DUT starts Link Training
<br>0003.405.468: _CR LT iter_, 1 lane(s)
<br>0003.405.855:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.406.073:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
<br>0003.406.141: _EQ LT iter_, 1 lane(s)
<br>0003.406.832:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.407.372:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.407.387: Source DUT completes Link Training
<br>0003.410.308: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h 
<br>0003.410.326: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.410.334: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.410.358: Short HPD pulse (0.75 ms)
<br>0003.411.145: Wait for a write to TEST_RESPONSE
<br>0003.416.556: TEST_RESPONSE.TEST_ACK is set
<br>0003.416.590: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.416.896:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
<br>0004.424.073:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
<br>0018.416.986: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.515.932: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID37">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 36</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.4.1.3 Main Stream Data Packing and Stuffing - Most Packed TU
<br> 
<br>0000.000.528: Configure EDID for the test
<br>0000.000.538: Setup EDID with one block of data (128 bytes)
<br>0000.000.546: Configure EDID for video mode 1280x800@60Hz 18 bpp
<br>0000.000.606: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1
<br>0000.000.629: Long HPD Pulse (2000 ms)
<br>0002.001.335: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.405.422:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.406.193:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81
<br>0003.406.212: Source DUT sets LANE_COUNT_SET = 1
<br>0003.406.220: Source DUT sets LINK_BW_SET = 06h
<br>0003.406.254: Source DUT supports TEST_LINK_TRAINING
<br>0003.406.262: Source DUT is ready to accept test requests at any time after plug
<br>0003.406.540:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00
<br>0003.406.554: Source DUT starts Link Training
<br>0003.406.609: _CR LT iter_, 1 lane(s)
<br>0003.406.992:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00
<br>0003.407.210:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 22 00
<br>0003.407.279: _EQ LT iter_, 1 lane(s)
<br>0003.407.957:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 00 00
<br>0003.408.479:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.408.493: Source DUT completes Link Training
<br>0003.411.678: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 1h 
<br>0003.411.697: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.411.705: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.411.729: Short HPD pulse (0.75 ms)
<br>0003.412.518: Wait for a write to TEST_RESPONSE
<br>0003.417.997: TEST_RESPONSE.TEST_ACK is set
<br>0003.418.032: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.418.329:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 00 00 00
<br>0004.425.370:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 01 01 00 00
<br>0018.418.302: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.517.271: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div><div id="ID38">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 37</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.4.2) Main Video Stream Format Change Handling</p>
<p class="BODYTEXT">
Test Result: <b>SKIPPED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.013: Starting test: 4.4.2 Main Video Stream Format Change Handling
<br> 
<br>0000.000.523: Skip test. Source DUT does not support video format change without re-training
<br>0000.002.618: Test SKIPED
<br> 
<br>
<br><br></p></div><div id="ID39">
<p class="SUBHEADING" style="margin-left: 0; margin-top: 0;">&nbsp;&nbsp;&nbsp;Test Details, Test 38</p>
<p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;(4.4.3) Power Management</p>
<p class="BODYTEXT">
Test Result: <b>FAILED</b>
<br><br><b>Test Settings:</b></p>
<p class="BODYTEXT">
DUT Capabilities:
<br>&emsp;Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
<br>&emsp;Video format change without LT: Not supported
<br>&emsp;Link count reduction without LT: Not supported
<br>&emsp;Driver level 3 (1.2V): Not supported
<br>&emsp;Pre-Emphasis level 3 (9.5dB): Supported
<br>&emsp;Fixed timing DUT: No
<br>&emsp;E-DDC: Supported
<br>&emsp;HPD Unplug timeout: 2000 ms
<br>
<br>Test automation:
<br>&emsp;LLCTS_TEST_LINK_TRAINING: Supported
<br>&emsp;LLCTS_TEST_PATTERN: Not supported
<br>&emsp;LLCTS_TEST_EDID_READ: Supported
<br>&emsp;Event indicating DUT ready = None.
<br>
</p><p class="GREENSUBHEADING">&nbsp;&nbsp;&nbsp;Test Log</p><p class="LOGBODYTEXT">0000.000.011: Starting test: 4.4.3 Power Management
<br> 
<br>0000.000.546: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
<br>0000.000.569: Long HPD Pulse (2000 ms)
<br>GU00.000.011: Starting test: 4.4.3 Power Management
<br> 
<br>0000.000.546: Set MAX_LINK_RATE = 0003.412.277:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x600:&nbsp 1&nbsp&nbsp 01
<br>0003.413.028:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 84
<br>0003.413.048: Source DUT sets LANE_COUNT_SET = 4
<br>0003.413.057: Source DUT sets LINK_BW_SET = 0Ah
<br>0003.413.091: Source DUT supports TEST_LINK_TRAINING
<br>0003.413.099: Source DUT is ready to accept test requests at any time after plug
<br>0003.413.367:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 21 00 00 00 00
<br>0003.413.384: Source DUT starts Link Training
<br>0003.413.438: _CR LT iter_, 4 lane(s)
<br>0003.413.784:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 00 00
<br>0003.414.012:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 5&nbsp&nbsp 22 00 00 00 00
<br>0003.414.077: _EQ LT iter_, 4 lane(s)
<br>0003.414.724:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 81 00 00 00
<br>0003.415.067:&nbsp&nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00
<br>0003.415.081: Source DUT completes Link Training
<br>0003.418.673: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h 
<br>0003.418.692: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
<br>0003.418.700: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
<br>0003.418.724: Short HPD pulse (0.75 ms)
<br>0003.419.513: Wait for a write to TEST_RESPONSE
<br>0003.424.683: TEST_RESPONSE.TEST_ACK is set
<br>0003.424.718: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
<br>0003.424.990:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 00 00 00
<br>0004.431.058:&nbsp&nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 77 01 01 00 00
<br>0018.425.447: Source DUT did not write LINK_BW_SET and/or LANE_COUNT_SET
<br>0018.426.281: Test FAILED, step 7, error 2: Test timeout
<br> 
<br>
<br><br></p></div>	</div>
	<hr>
	<p class="BODYTEXT" style="text-align: center;">
		Unigraf Oy<span style="color:#808080;"> |</span> Piispantilankuja 4 <span style="color:#808080;">|</span> 02240 Espoo <span style="color:#808080;">|</span> Finland <span style="color:#808080;">|</span> +358-9-859 550<br />
		E-mail: <a href="mailto:info@unigraf.fi">info@unigraf.fi</a><span style="color:#808080;"> |</span> Web site: <a href="http://www.unigraf.fi">www.unigraf.fi</a>
	</p>
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