Attachment 144804 Details for Bug 111149 – [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[patch] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

0001-drm-i915-Make-sure-cdclk-is-high-enough-for-DP-audio.patch (text/plain), 2.43 KB, created by Ville Syrjala on 2019-07-16 18:06:55 UTC

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Creator: Ville Syrjala

Created: 2019-07-16 18:06:55 UTC

Size: 2.43 KB

patch

obsolete

>From a5362ee329cb8020158a750d6f119c437677b433 Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Tue, 16 Jul 2019 20:45:29 +0300
>Subject: [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on
> VLV/CHV
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>On VLV/CHV there is some kind of linkage between the cdclk frequency
>and the DP link frequency. The spec says:
>"For DP audio configuration, cdclk frequency shall be set to
> meet the following requirements:
> DP Link Frequency(MHz) | Cdclk frequency(MHz)
> 270                    | 320 or higher
> 162                    | 200 or higher"
>
>I suspect that would more accurately be expressed as
>"cdclk >= DP link clock", and in any case we can express it like
>that in the code because of the limited set of cdclk and link
>frequencies we support.
>
>Without this we can end up in a situation where the cdclk
>is too low and enabling DP audio will kill the pipe. Happens
>eg. with 2560x1440 modes where the 266MHz cdclk is sufficient
>to pump the pixels (241.5 MHz dotclock) but is too low for
>the DP audio due to the link frequency being 270 MHz.
>
>Cc: stable@vger.kernel.org
>Cc: Stefan Gottwald <gottwald@igel.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111149
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index d0581a1ac243..93b0d190c184 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> 	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> 		min_cdclk = max(2 * 96000, min_cdclk);
> 
>+	/*
>+	 * "For DP audio configuration, cdclk frequency shall be set to
>+	 *  meet the following requirements:
>+	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
>+	 *  270                    | 320 or higher
>+	 *  162                    | 200 or higher"
>+	 */
>+	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>+	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
>+		min_cdclk = max(crtc_state->port_clock, min_cdclk);
>+
> 	/*
> 	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> 	 * than 320000KHz.
>-- 
>2.21.0
>

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Attachments on bug 111149: 144799 | 144804

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