Attachment 46702 Details for Bug 36599 – Don't enable SSC on the common clock source when shared with a non-SSC output.

[patch] Don't enable SSC on the common clock source when shared with a non-SSC output.

0001-drm-i915-Don-t-enable-SSC-on-the-common-clock-source.patch (text/plain), 5.00 KB, created by Chris Wilson on 2011-05-14 01:26:30 UTC

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Creator: Chris Wilson

Created: 2011-05-14 01:26:30 UTC

Size: 5.00 KB

patch

obsolete

>From dd032cb456d2a13afa937c69dba3ec94b8c14fbd Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Wed, 27 Apr 2011 09:06:36 +0100
>Subject: [PATCH] drm/i915: Don't enable SSC on the common clock source when
> sharing with non-SSC
>
>On the PCH, there is a single clock source which can be enabled to
>generate a Spread-Spectrum Clock. This source is then used to drive all
>outputs, so if there is an output not capable of handling SSC, such as
>VGA, then we need to disable SSC on the common source and all outputs.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36599
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_drv.h      |    1 +
> drivers/gpu/drm/i915/intel_bios.c    |    1 +
> drivers/gpu/drm/i915/intel_bios.h    |    4 ++-
> drivers/gpu/drm/i915/intel_display.c |   65 +++++++++++++++++++++-------------
> 4 files changed, 45 insertions(+), 26 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index b492779..2e35a64 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -340,6 +340,7 @@ typedef struct drm_i915_private {
> 	unsigned int lvds_vbt:1;
> 	unsigned int int_crt_support:1;
> 	unsigned int lvds_use_ssc:1;
>+	unsigned int display_clock_mode:1;
> 	int lvds_ssc_freq;
> 	struct {
> 		int rate;
>diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>index fb5b4d4..48a0f03 100644
>--- a/drivers/gpu/drm/i915/intel_bios.c
>+++ b/drivers/gpu/drm/i915/intel_bios.c
>@@ -285,6 +285,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
> 		dev_priv->lvds_use_ssc = general->enable_ssc;
> 		dev_priv->lvds_ssc_freq =
> 			intel_bios_ssc_frequency(dev, general->ssc_freq);
>+		dev_priv->display_clock_mode = general->display_clock_mode;
> 	}
> }
> 
>diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
>index 5f8e4ed..02b1b624 100644
>--- a/drivers/gpu/drm/i915/intel_bios.h
>+++ b/drivers/gpu/drm/i915/intel_bios.h
>@@ -120,7 +120,9 @@ struct bdb_general_features {
> 	u8 ssc_freq:1;
> 	u8 enable_lfp_on_override:1;
> 	u8 disable_ssc_ddt:1;
>-	u8 rsvd8:3; /* finish byte */
>+	u8 rsvd7:1;
>+	u8 display_clock_mode:1;
>+	u8 rsvd8:1; /* finish byte */
> 
>         /* bits 3 */
> 	u8 disable_smooth_vision:1;
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 4101391..de8bcd7 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -4830,44 +4830,59 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
> 	 * ignoring this setting.
> 	 */
> 	if (HAS_PCH_SPLIT(dev)) {
>+		bool use_ssc = intel_panel_use_ssc(dev_priv);
>+
>+		/* Are any non-SSC outputs enabled? */
>+		list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
>+			if (encoder->base.crtc == NULL)
>+				continue;
>+
>+			if (encoder->type == INTEL_OUTPUT_ANALOG)
>+				use_ssc = false;
>+		}
>+
>+		/*XXX BIOS treats 16:31 as a mask for 0:15 */
> 		temp = I915_READ(PCH_DREF_CONTROL);
>-		/* Always enable nonspread source */
>+
>+		/* First clear the current state for output switching */
>+		temp &= ~DREF_SSC1_ENABLE;
>+		temp &= ~DREF_SSC4_ENABLE;
>+		temp &= ~DREF_SUPERSPREAD_SOURCE_MASK;
> 		temp &= ~DREF_NONSPREAD_SOURCE_MASK;
>-		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
> 		temp &= ~DREF_SSC_SOURCE_MASK;
>-		temp |= DREF_SSC_SOURCE_ENABLE;
>+		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> 		I915_WRITE(PCH_DREF_CONTROL, temp);
> 
> 		POSTING_READ(PCH_DREF_CONTROL);
> 		udelay(200);
> 
>-		if (has_edp_encoder) {
>-			if (intel_panel_use_ssc(dev_priv)) {
>-				temp |= DREF_SSC1_ENABLE;
>-				I915_WRITE(PCH_DREF_CONTROL, temp);
>-
>-				POSTING_READ(PCH_DREF_CONTROL);
>-				udelay(200);
>-			}
>-			temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
>-
>-			/* Enable CPU source on CPU attached eDP */
>-			if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
>-				if (intel_panel_use_ssc(dev_priv))
>+		if ((is_lvds || has_edp_encoder) && use_ssc) {
>+			temp |= DREF_SSC_SOURCE_ENABLE;
>+			if (has_edp_encoder) {
>+				if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
>+					/* Enable CPU source on CPU attached eDP */
> 					temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
>-				else
>-					temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
>-			} else {
>-				/* Enable SSC on PCH eDP if needed */
>-				if (intel_panel_use_ssc(dev_priv)) {
>-					DRM_ERROR("enabling SSC on PCH\n");
>+				} else {
>+					/* Enable SSC on PCH eDP if needed */
> 					temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
> 				}
>+				I915_WRITE(PCH_DREF_CONTROL, temp);
> 			}
>-			I915_WRITE(PCH_DREF_CONTROL, temp);
>-			POSTING_READ(PCH_DREF_CONTROL);
>-			udelay(200);
>+			if (!dev_priv->display_clock_mode)
>+				temp |= DREF_SSC1_ENABLE;
>+		} else {
>+			if (dev_priv->display_clock_mode)
>+				temp |= DREF_NONSPREAD_CK505_ENABLE;
>+			else
>+				temp |= DREF_NONSPREAD_SOURCE_ENABLE;
>+			if (has_edp_encoder &&
>+			    !intel_encoder_is_pch_edp(&has_edp_encoder->base))
>+				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> 		}
>+
>+		I915_WRITE(PCH_DREF_CONTROL, temp);
>+		POSTING_READ(PCH_DREF_CONTROL);
>+		udelay(200);
> 	}
> 
> 	if (IS_PINEVIEW(dev)) {
>-- 
>1.7.5.1
>

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Attachments on bug 36599: 46076 | 46077 | 46078 | 46079 | 46112 | 46702 | 46770

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