Attachment 63483 Details for Bug 51436 – add CS_STALL to render cache flush

[patch] add CS_STALL to render cache flush

0001-drm-i915-Flush-Me-Harder-required-on-gen6.patch (text/plain), 2.50 KB, created by Daniel Vetter on 2012-06-26 03:42:41 UTC

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Creator: Daniel Vetter

Created: 2012-06-26 03:42:41 UTC

Size: 2.50 KB

patch

obsolete

>From e44754f620c825a920a99b0b2ade571654a9cd74 Mon Sep 17 00:00:00 2001
>From: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date: Tue, 26 Jun 2012 11:02:24 +0200
>Subject: [PATCH] drm/i915: "Flush Me Harder" required on gen6+
>
>The prep to remove the flushing list in
>
>commit cc889e0f6ce6a63c62db17d702ecfed86d58083f
>Author: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date:   Wed Jun 13 20:45:19 2012 +0200
>
>    drm/i915: disable flushing_list/gpu_write_list
>
>cause quite some decent regressions. We can fix this by setting the
>CS_STALL bit to ensure that the following seqno write happens only
>after the cache flush has completed. But only do that when the caller
>actually wants the flush (and not also when we invalidate caches
>before starting the next batch).
>
>I've looked through all our ancient scrolls about gen6+ pipe control
>workarounds, and this seems to be indeed a legal combination: We're
>allowed to set the CS_STALL bit when we flush the render cache (which
>we do).
>
>While yelling at this code, also pass back the return value from
>intel_emit_post_sync_nonzero_flush properly.
>
>v2: Instead of emitting more pipe controls, set the CS_STALL bit on
>the write flush as suggested by Chris Wilson. It seems to work, too.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51429
>Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>---
> drivers/gpu/drm/i915/intel_ringbuffer.c |   10 +++++++++-
> 1 files changed, 9 insertions(+), 1 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>index f30a53a..dce4d1a 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>@@ -219,7 +219,9 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
> 	int ret;
> 
> 	/* Force SNB workarounds for PIPE_CONTROL flushes */
>-	intel_emit_post_sync_nonzero_flush(ring);
>+	ret = intel_emit_post_sync_nonzero_flush(ring);
>+	if (ret)
>+		return ret;
> 
> 	/* Just flush everything.  Experiments have shown that reducing the
> 	 * number of bits based on the write domains has little performance
>@@ -233,6 +235,12 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
> 	flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
> 	flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
> 	flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
>+	/*
>+	 * Ensure that any following seqno writes only happen when the render
>+	 * cache is indeed flushed (but only if the caller actually wants that).
>+	 */
>+	if (flush_domains)
>+		flags |= PIPE_CONTROL_CS_STALL;
> 
> 	ret = intel_ring_begin(ring, 6);
> 	if (ret)
>-- 
>1.7.7.6
>

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