Attachment 87227 Details for Bug 67454 – save/restore some more backlight registers

[patch] save/restore some more backlight registers

0001-save-restore-some-more-backlight-registers.patch (text/plain), 3.14 KB, created by Jani Nikula on 2013-10-07 09:27:53 UTC

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Creator: Jani Nikula

Created: 2013-10-07 09:27:53 UTC

Size: 3.14 KB

patch

obsolete

>From 17524e7eaeeb6733fdef90aebeb1c8b2d5d27bfb Mon Sep 17 00:00:00 2001
>From: Jani Nikula <jani.nikula@intel.com>
>Date: Mon, 7 Oct 2013 12:28:46 +0300
>Subject: [PATCH] save/restore some more backlight registers
>Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
>Cc: Jani Nikula <jani.nikula@intel.com>
>
>---
> drivers/gpu/drm/i915/i915_drv.h     |    4 ++++
> drivers/gpu/drm/i915/i915_reg.h     |    2 ++
> drivers/gpu/drm/i915/i915_suspend.c |   16 ++++++++++++++++
> 3 files changed, 22 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index ed8653f..f884a25 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -719,6 +719,10 @@ struct i915_suspend_saved_registers {
> 	u32 saveBLC_PWM_CTL2;
> 	u32 saveBLC_CPU_PWM_CTL;
> 	u32 saveBLC_CPU_PWM_CTL2;
>+	u32 saveHSW_BLC_PWM2_CTL;
>+	u32 saveHSW_BLC_PWM2_DATA;
>+	u32 saveHSW_BLC_MISC_CTL;
>+	u32 saveUTIL_PIN_CTL;
> 	u32 saveFPB0;
> 	u32 saveFPB1;
> 	u32 saveDPLL_B;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 4be72b2..4a56653 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2358,6 +2358,8 @@
> #define BLC_PWM_CPU_CTL		0x48254
> 
> #define HSW_BLC_PWM2_CTL	0x48350
>+#define HSW_BLC_PWM2_DATA	0x48354
>+#define HSW_BLC_MISC_CTL	0x48360
> 
> /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
>  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
>diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>index 3538370..66f3ac7 100644
>--- a/drivers/gpu/drm/i915/i915_suspend.c
>+++ b/drivers/gpu/drm/i915/i915_suspend.c
>@@ -212,6 +212,14 @@ static void i915_save_display(struct drm_device *dev)
> 		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
> 		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
> 		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
>+
>+		if (IS_HASWELL(dev)) {
>+			dev_priv->regfile.saveHSW_BLC_PWM2_CTL = I915_READ(HSW_BLC_PWM2_CTL);
>+			dev_priv->regfile.saveHSW_BLC_PWM2_DATA = I915_READ(HSW_BLC_PWM2_DATA);
>+			dev_priv->regfile.saveHSW_BLC_MISC_CTL = I915_READ(HSW_BLC_MISC_CTL);
>+			dev_priv->regfile.saveUTIL_PIN_CTL = I915_READ(UTIL_PIN_CTL);
>+		}
>+
> 		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> 			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
> 	} else {
>@@ -296,6 +304,14 @@ static void i915_restore_display(struct drm_device *dev)
> 		 */
> 		I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
> 		I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
>+
>+		if (IS_HASWELL(dev)) {
>+			I915_WRITE(HSW_BLC_PWM2_CTL, dev_priv->regfile.saveHSW_BLC_PWM2_CTL);
>+			I915_WRITE(HSW_BLC_PWM2_DATA, dev_priv->regfile.saveHSW_BLC_PWM2_DATA);
>+			I915_WRITE(HSW_BLC_MISC_CTL, dev_priv->regfile.saveHSW_BLC_MISC_CTL);
>+			I915_WRITE(UTIL_PIN_CTL, dev_priv->regfile.saveUTIL_PIN_CTL);
>+		}
>+
> 		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
> 		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
> 		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>-- 
>1.7.9.5
>

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Attachments on bug 67454: 83161 | 83162 | 83163 | 83164 | 83165 | 83166 | 83167 | 83168 | 83169 | 83170 | 83171 | 83172 | 83173 | 83174 | 83175 | 83176 | 83177 | 83179 | 83181 | 83182 | 83233 | 83234 | 83235 | 83236 | 86483 | 87227 | 88822 | 88823 | 91732 | 91733 | 126443

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