Attachment 87720 Details for Bug 70524 – intel reg info

intel reg info

intel_reg_dumper_it6506_dp_audio_display_1280_1024_2lane_intel-drm-nightly.log (text/plain), 10.07 KB, created by Ken Lin on 2013-10-16 09:13:10 UTC

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Creator: Ken Lin

Created: 2013-10-16 09:13:10 UTC

Size: 10.07 KB

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obsolete

>             HSW_PWR_WELL_CTL1: 0x40000000
>             HSW_PWR_WELL_CTL2: 0xc0000000
>             HSW_PWR_WELL_CTL3: 0x40000000
>             HSW_PWR_WELL_CTL4: 0x40000000
>             HSW_PWR_WELL_CTL5: 0x0004050f
>             HSW_PWR_WELL_CTL6: 0x00000000
>           PIPE_DDI_FUNC_CTL_A: 0x91030000 (enabled, DDIB, DVI, 8 bpc, +VSync, +HSync, EDP A ON, x1)
>           PIPE_DDI_FUNC_CTL_B: 0xa2030002 (enabled, DDIC, DP SST, 8 bpc, +VSync, +HSync, EDP A ON, x2)
>           PIPE_DDI_FUNC_CTL_C: 0x00030000 (disabled, no port, HDMI, 8 bpc, +VSync, +HSync, EDP A ON, x1)
>         PIPE_DDI_FUNC_CTL_EDP: 0x00030000 (disabled, no port, HDMI, 8 bpc, +VSync, +HSync, EDP A ON, x1)
>                   DP_TP_CTL_A: 0x00000000
>                   DP_TP_CTL_B: 0x00000000
>                   DP_TP_CTL_C: 0x80040300
>                   DP_TP_CTL_D: 0x00000000
>                   DP_TP_CTL_E: 0x00000000
>                DP_TP_STATUS_B: 0x00000000
>                DP_TP_STATUS_C: 0x00000000
>                DP_TP_STATUS_D: 0x00000000
>                DP_TP_STATUS_E: 0x00000000
>                 DDI_BUF_CTL_A: 0x00000080 (disabled not reversed x1 not detected)
>                 DDI_BUF_CTL_B: 0x80000000 (enabled not reversed x1 not detected)
>                 DDI_BUF_CTL_C: 0x80000002 (enabled not reversed x2 not detected)
>                 DDI_BUF_CTL_D: 0x00000000 (disabled not reversed x1 not detected)
>                 DDI_BUF_CTL_E: 0x00000000 (disabled not reversed x1 not detected)
>                      SPLL_CTL: 0x00000000
>                     LCPLL_CTL: 0x44000037
>                    WRPLL_CTL1: 0xb0210614
>                    WRPLL_CTL2: 0x00202418
>                PORT_CLK_SEL_A: 0xe0000000 (None)
>                PORT_CLK_SEL_B: 0x80000000 (WRPLL 1)
>                PORT_CLK_SEL_C: 0x40000000 (LCPLL 810)
>                PORT_CLK_SEL_D: 0xe0000000 (None)
>                PORT_CLK_SEL_E: 0xe0000000 (None)
>                PIPE_CLK_SEL_A: 0x40000000 (DDIB)
>                PIPE_CLK_SEL_B: 0x60000000 (DDIC)
>                PIPE_CLK_SEL_C: 0x00000000 (None)
>                     WM_PIPE_A: 0x00150006 (primary 21, sprite 0, pipe 6)
>                     WM_PIPE_B: 0x00100006 (primary 16, sprite 0, pipe 6)
>                     WM_PIPE_C: 0x00000000 (primary 0, sprite 0, pipe 0)
>                        WM_LP1: 0x82301506
>                        WM_LP2: 0x8440aa0a
>                        WM_LP3: 0x00000000
>                    WM_LP1_SPR: 0x00000000
>                    WM_LP2_SPR: 0x00000000
>                    WM_LP3_SPR: 0x00000000
>                       WM_MISC: 0x00000000
>                     WM_SR_CNT: 0x00000000
>            PIPE_WM_LINETIME_A: 0x00210077
>            PIPE_WM_LINETIME_B: 0x0000007d
>            PIPE_WM_LINETIME_C: 0x00000000
>                        WM_DBG: 0x00210077
>                   SFUSE_STRAP: 0x00000007 (display enabled, crt no, lane reversal no, port b yes, port c yes, port d yes)
>                      PIPEASRC: 0x077f0437 (1920, 1080)
>                      DSPACNTR: 0xd9000400 (enabled)
>                    DSPASTRIDE: 0x00003200 (200)
>                      DSPASURF: 0x07523000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x04ff03ff (1280, 1024)
>                      DSPBCNTR: 0xd9000400 (enabled)
>                    DSPBSTRIDE: 0x00003200 (200)
>                      DSPBSURF: 0x075e1000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPECSRC: 0x00000000 (1, 1)
>                      DSPCCNTR: 0x00000000 (disabled)
>                    DSPCSTRIDE: 0x00000000 (0)
>                      DSPCSURF: 0x00000000
>                   DSPCTILEOFF: 0x00000000 (0, 0)
>                     PIPEACONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_A: 0x0897077f (1920 active, 2200 total)
>                      HBLANK_A: 0x0897077f (1920 start, 2200 end)
>                       HSYNC_A: 0x080307d7 (2008 start, 2052 end)
>                      VTOTAL_A: 0x04640437 (1080 active, 1125 total)
>                      VBLANK_A: 0x04640437 (1080 start, 1125 end)
>                       VSYNC_A: 0x0440043b (1084 start, 1089 end)
>                  VSYNCSHIFT_A: 0x00000000
>                 PIPEA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N1: 0x00000000 (val 0x0 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_B: 0x069704ff (1280 active, 1688 total)
>                      HBLANK_B: 0x069704ff (1280 start, 1688 end)
>                       HSYNC_B: 0x059f052f (1328 start, 1440 end)
>                      VTOTAL_B: 0x042903ff (1024 active, 1066 total)
>                      VBLANK_B: 0x042903ff (1024 start, 1066 end)
>                       VSYNC_B: 0x04030400 (1025 start, 1028 end)
>                  VSYNCSHIFT_B: 0x00000000
>                 PIPEB_DATA_M1: 0x7e400000 (TU 64, val 0x400000 4194304)
>                 PIPEB_DATA_N1: 0x00400000 (val 0x400000 4194304)
>                 PIPEB_LINK_M1: 0x0002aaaa (val 0x2aaaa 174762)
>                 PIPEB_LINK_N1: 0x00040000 (val 0x40000 262144)
>                     PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_C: 0x00000000 (1 active, 1 total)
>                      HBLANK_C: 0x00000000 (1 start, 1 end)
>                       HSYNC_C: 0x00000000 (1 start, 1 end)
>                      VTOTAL_C: 0x00000000 (1 active, 1 total)
>                      VBLANK_C: 0x00000000 (1 start, 1 end)
>                       VSYNC_C: 0x00000000 (1 start, 1 end)
>                  VSYNCSHIFT_C: 0x00000000
>                 PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N1: 0x00000000 (val 0x0 0)
>                   PIPEEDPCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
>                    HTOTAL_EDP: 0x00000000 (1 active, 1 total)
>                    HBLANK_EDP: 0x00000000 (1 start, 1 end)
>                     HSYNC_EDP: 0x00000000 (1 start, 1 end)
>                    VTOTAL_EDP: 0x00000000 (1 active, 1 total)
>                    VBLANK_EDP: 0x00000000 (1 start, 1 end)
>                     VSYNC_EDP: 0x00000000 (1 start, 1 end)
>                VSYNCSHIFT_EDP: 0x00000000
>               PIPEEDP_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>               PIPEEDP_DATA_N1: 0x00000000 (val 0x0 0)
>               PIPEEDP_LINK_M1: 0x00000000 (val 0x0 0)
>               PIPEEDP_LINK_N1: 0x00000000 (val 0x0 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>                     PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                   PFC_WIN_POS: 0x00000000 (0, 0)
>                  PFC_WIN_SIZE: 0x00000000 (0, 0)
>                TRANS_HTOTAL_A: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_A: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_A: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_A: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_A: 0x00000000 (1 start, 1 end)
>                 TRANS_VSYNC_A: 0x00000000 (1 start, 1 end)
>            TRANS_VSYNCSHIFT_A: 0x00000000
>                    TRANSACONF: 0x00000000 (disable, inactive, progressive)
>                  FDI_RXA_MISC: 0x0a200090 (FDI Delay 144)
>               FDI_RXA_TUSIZE1: 0x7e000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x00000fff
>              BLC_PWM_CPU_CTL2: 0x60000000 (enable 0, pipe EDP, blinking 0, granularity 128)
>               BLC_PWM_CPU_CTL: 0x00000000 (cycle 0, freq 0)
>             BLC_PWM2_CPU_CTL2: 0x60000000 (enable 0, pipe EDP, blinking 0, granularity 128)
>              BLC_PWM2_CPU_CTL: 0x00000000 (cycle 0, freq 0)
>                  BLC_MISC_CTL: 0x00000000 (PWM1-PCH PWM2-CPU)
>              BLC_PWM_PCH_CTL1: 0x00000000 (enable 0, override 0, inverted polarity 0)
>              BLC_PWM_PCH_CTL2: 0x00000000 (freq 0, cycle 0)
>                  UTIL_PIN_CTL: 0x00000000 (enable 0, transcoder A, mode data, data 0 inverted polarity 0)
>                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0x00000000 (blacklight disabled, do not power down on reset, panel off)
>              PCH_PP_ON_DELAYS: 0x00000000
>             PCH_PP_OFF_DELAYS: 0x00000000
>                PCH_PP_DIVISOR: 0x00186906
>                   PIXCLK_GATE: 0x00000000
>                        SDEISR: 0x00600000 (port d:0, port c:1, port b:1, crt:0)
>            RC6_RESIDENCY_TIME: 0x0c3aa95b
>               GEN6_RP_CONTROL: 0x00000d92 (enabled)
>                 GEN6_RPNSWREQ: 0x07000000
>          GEN6_RP_DOWN_TIMEOUT: 0x0000c350
>      GEN6_RP_INTERRUPT_LIMITS: 0x14000000
>          GEN6_RP_UP_THRESHOLD: 0x00002409
>                 GEN6_RP_UP_EI: 0x0000280a
>               GEN6_RP_DOWN_EI: 0x000061a8
>        GEN6_RP_IDLE_HYSTERSIS: 0x0000000a
>                 GEN6_RC_STATE: 0x00000000
>               GEN6_RC_CONTROL: 0x88040000
>      GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000
>      GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e
>   GEN6_RC_EVALUATION_INTERVAL: 0x0001e848
>        GEN6_RC_IDLE_HYSTERSIS: 0x00000019
>                 GEN6_RC_SLEEP: 0x00000000
>           GEN6_RC1e_THRESHOLD: 0x000003e8
>            GEN6_RC6_THRESHOLD: 0x0000c350
>            GEN6_RC_VIDEO_FREQ: 0x18000000
>                    GEN6_PMIER: 0x00000470
>                    GEN6_PMIMR: 0xffffff8f
>                GEN6_PMINTRMSK: 0x0000000e

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Attachments on bug 70524: 87717 | 87718 | 87719 | 87720 | 87721 | 87722 | 87723 | 87724 | 87767

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