Attachment 114067 Details for Bug 89456 – dmesg

dmesg

dmesg.txt (text/plain), 123.81 KB, created by Ding Heng on 2015-03-06 05:55:20 UTC

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Creator: Ding Heng

Created: 2015-03-06 05:55:20 UTC

Size: 123.81 KB

patch

obsolete

>[ 7850.700463] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7850.700465] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7850.700468] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7850.700470] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7850.700471] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7850.700473] [drm:intel_dump_pipe_config] requested mode:
>[ 7850.700477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7850.700478] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7850.700481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7850.700485] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7850.700486] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7850.700488] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7850.700490] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7850.700491] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7850.700493] [drm:intel_dump_pipe_config] ips: 0
>[ 7850.700494] [drm:intel_dump_pipe_config] double wide: 0
>[ 7850.700497] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7850.700500] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7850.700502] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7850.700504] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7850.700507] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7850.700509] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7850.700512] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7850.700514] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7850.700516] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7850.700518] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7850.700519] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7850.700520] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7850.700523] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7850.700525] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7850.700527] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7850.700528] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7850.700529] [drm:intel_dump_pipe_config] requested mode:
>[ 7850.700533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7850.700534] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7850.700538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7850.700541] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7850.700542] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7850.700544] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7850.700546] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7850.700548] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7850.700549] [drm:intel_dump_pipe_config] ips: 0
>[ 7850.700550] [drm:intel_dump_pipe_config] double wide: 0
>[ 7850.700571] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7850.700574] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7850.700576] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7850.700578] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7850.700581] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7850.700583] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7850.700585] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7850.700588] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7850.700590] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7850.700592] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7850.700594] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7850.700596] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7850.700597] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7850.700599] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7850.700601] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7850.700604] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7850.700606] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7850.700607] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7850.700609] [drm:intel_dump_pipe_config] requested mode:
>[ 7850.700612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7850.700613] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7850.700617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7850.700620] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7850.700622] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7850.700623] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7850.700625] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7850.700627] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7850.700628] [drm:intel_dump_pipe_config] ips: 0
>[ 7850.700629] [drm:intel_dump_pipe_config] double wide: 0
>[ 7850.700632] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7850.700635] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7850.700637] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7850.700639] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7850.700642] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7850.700644] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7850.700647] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7850.700649] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7850.700651] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7850.700652] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7850.700653] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7850.700655] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7850.700657] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7850.700660] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7850.700662] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7850.700663] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7850.700664] [drm:intel_dump_pipe_config] requested mode:
>[ 7850.700668] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7850.700669] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7850.700673] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7850.700676] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7850.700677] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7850.700679] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7850.700681] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7850.700682] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7850.700684] [drm:intel_dump_pipe_config] ips: 0
>[ 7850.700685] [drm:intel_dump_pipe_config] double wide: 0
>[ 7854.655321] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7854.655327] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7854.655330] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7854.655333] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7854.655336] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7854.655340] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7854.655342] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7854.655347] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7854.655350] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7854.655351] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7854.655355] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7854.655357] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7854.655358] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7854.655360] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7854.655362] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7854.655365] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7854.655367] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7854.655369] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7854.655370] [drm:intel_dump_pipe_config] requested mode:
>[ 7854.655375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7854.655376] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7854.655379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7854.655383] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7854.655384] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7854.655386] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7854.655388] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7854.655389] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7854.655391] [drm:intel_dump_pipe_config] ips: 0
>[ 7854.655392] [drm:intel_dump_pipe_config] double wide: 0
>[ 7854.655397] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7854.655400] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7854.655402] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7854.655404] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7854.655407] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7854.655409] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7854.655414] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7854.655415] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7854.655417] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7854.655419] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7854.655420] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7854.655422] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7854.655424] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7854.655426] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7854.655428] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7854.655430] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7854.655431] [drm:intel_dump_pipe_config] requested mode:
>[ 7854.655434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7854.655435] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7854.655439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7854.655442] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7854.655444] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7854.655445] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7854.655447] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7854.655449] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7854.655450] [drm:intel_dump_pipe_config] ips: 0
>[ 7854.655451] [drm:intel_dump_pipe_config] double wide: 0
>[ 7855.338782] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7855.338804] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7855.338807] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7855.338809] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7855.338813] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7855.338817] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7855.338819] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7855.338824] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7855.338826] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7855.338828] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7855.338831] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7855.338833] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7855.338835] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7855.338836] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7855.338839] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7855.338842] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7855.338844] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7855.338845] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7855.338846] [drm:intel_dump_pipe_config] requested mode:
>[ 7855.338851] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7855.338852] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7855.338856] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7855.338859] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7855.338861] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7855.338862] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7855.338864] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7855.338866] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7855.338867] [drm:intel_dump_pipe_config] ips: 0
>[ 7855.338868] [drm:intel_dump_pipe_config] double wide: 0
>[ 7855.338873] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7855.338876] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7855.338878] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7855.338880] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7855.338883] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7855.338885] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7855.338890] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7855.338892] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7855.338894] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7855.338896] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7855.338897] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7855.338898] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7855.338901] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7855.338903] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7855.338905] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7855.338907] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7855.338908] [drm:intel_dump_pipe_config] requested mode:
>[ 7855.338911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7855.338912] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7855.338916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7855.338919] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7855.338921] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7855.338922] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7855.338924] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7855.338926] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7855.338927] [drm:intel_dump_pipe_config] ips: 0
>[ 7855.338928] [drm:intel_dump_pipe_config] double wide: 0
>[ 7855.597704] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7855.597726] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7855.597729] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7855.597731] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7855.597735] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7855.597739] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7855.597741] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7855.597745] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7855.597748] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7855.597750] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7855.597753] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7855.597756] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7855.597757] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7855.597758] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7855.597761] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7855.597764] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7855.597766] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7855.597768] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7855.597769] [drm:intel_dump_pipe_config] requested mode:
>[ 7855.597773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7855.597774] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7855.597778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7855.597782] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7855.597783] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7855.597785] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7855.597786] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7855.597788] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7855.597789] [drm:intel_dump_pipe_config] ips: 0
>[ 7855.597791] [drm:intel_dump_pipe_config] double wide: 0
>[ 7855.597795] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7855.597799] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7855.597801] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7855.597803] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7855.597805] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7855.597808] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7855.597813] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7855.597814] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7855.597816] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7855.597818] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7855.597819] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7855.597821] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7855.597823] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7855.597825] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7855.597827] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7855.597829] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7855.597830] [drm:intel_dump_pipe_config] requested mode:
>[ 7855.597834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7855.597835] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7855.597838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7855.597841] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7855.597843] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7855.597844] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7855.597846] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7855.597848] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7855.597849] [drm:intel_dump_pipe_config] ips: 0
>[ 7855.597850] [drm:intel_dump_pipe_config] double wide: 0
>[ 7860.793688] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7860.793704] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7860.793719] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7860.793721] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7860.793725] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7860.793728] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7860.793730] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7860.793735] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7860.793738] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7860.793740] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7860.793744] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7860.793746] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7860.793747] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7860.793749] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7860.793751] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7860.793755] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7860.793757] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7860.793758] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7860.793759] [drm:intel_dump_pipe_config] requested mode:
>[ 7860.793764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7860.793765] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7860.793769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7860.793772] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7860.793774] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7860.793775] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7860.793777] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7860.793779] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7860.793780] [drm:intel_dump_pipe_config] ips: 0
>[ 7860.793782] [drm:intel_dump_pipe_config] double wide: 0
>[ 7860.793786] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7860.793790] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7860.793792] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7860.793794] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7860.793796] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7860.793799] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7860.793804] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7860.793805] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7860.793807] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7860.793809] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7860.793810] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7860.793811] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7860.793814] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7860.793816] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7860.793818] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7860.793820] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7860.793821] [drm:intel_dump_pipe_config] requested mode:
>[ 7860.793824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7860.793825] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7860.793829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7860.793832] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7860.793833] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7860.793835] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7860.793837] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7860.793839] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7860.793840] [drm:intel_dump_pipe_config] ips: 0
>[ 7860.793841] [drm:intel_dump_pipe_config] double wide: 0
>[ 7861.516163] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7861.516179] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7861.516188] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7861.516239] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7861.516243] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7861.516247] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7861.516249] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7861.516253] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7861.516256] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7861.516258] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7861.516261] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7861.516263] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7861.516264] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7861.516266] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7861.516269] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7861.516272] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7861.516274] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7861.516275] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7861.516277] [drm:intel_dump_pipe_config] requested mode:
>[ 7861.516281] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7861.516282] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7861.516286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7861.516289] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7861.516291] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7861.516292] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7861.516294] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7861.516296] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7861.516297] [drm:intel_dump_pipe_config] ips: 0
>[ 7861.516298] [drm:intel_dump_pipe_config] double wide: 0
>[ 7861.516303] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7861.516307] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7861.516309] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7861.516311] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7861.516313] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7861.516316] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7861.516320] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7861.516322] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7861.516323] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7861.516325] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7861.516326] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7861.516328] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7861.516330] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7861.516333] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7861.516335] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7861.516336] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7861.516337] [drm:intel_dump_pipe_config] requested mode:
>[ 7861.516341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7861.516342] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7861.516346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7861.516349] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7861.516350] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7861.516352] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7861.516354] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7861.516355] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7861.516356] [drm:intel_dump_pipe_config] ips: 0
>[ 7861.516358] [drm:intel_dump_pipe_config] double wide: 0
>[ 7861.870100] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7861.870116] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7861.870127] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7861.870129] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7861.870133] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7861.870137] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7861.870139] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7861.870144] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7861.870146] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7861.870148] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7861.870152] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7861.870154] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7861.870155] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7861.870157] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7861.870160] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7861.870162] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7861.870165] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7861.870166] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7861.870167] [drm:intel_dump_pipe_config] requested mode:
>[ 7861.870172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7861.870173] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7861.870176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7861.870180] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7861.870181] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7861.870183] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7861.870185] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7861.870186] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7861.870188] [drm:intel_dump_pipe_config] ips: 0
>[ 7861.870189] [drm:intel_dump_pipe_config] double wide: 0
>[ 7861.870193] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7861.870197] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7861.870199] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7861.870201] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7861.870203] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7861.870206] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7861.870211] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7861.870212] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7861.870214] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7861.870216] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7861.870217] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7861.870219] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7861.870221] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7861.870223] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7861.870225] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7861.870227] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7861.870228] [drm:intel_dump_pipe_config] requested mode:
>[ 7861.870231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7861.870232] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7861.870236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7861.870239] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7861.870241] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7861.870242] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7861.870244] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7861.870246] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7861.870247] [drm:intel_dump_pipe_config] ips: 0
>[ 7861.870248] [drm:intel_dump_pipe_config] double wide: 0
>[ 7862.136393] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7862.136410] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7862.136421] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7862.136424] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7862.136427] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7862.136431] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7862.136432] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7862.136438] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7862.136440] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7862.136442] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7862.136446] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7862.136448] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7862.136449] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7862.136451] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7862.136453] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7862.136456] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7862.136459] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7862.136460] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7862.136461] [drm:intel_dump_pipe_config] requested mode:
>[ 7862.136466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7862.136467] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7862.136470] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7862.136474] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7862.136475] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7862.136477] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7862.136479] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7862.136480] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7862.136482] [drm:intel_dump_pipe_config] ips: 0
>[ 7862.136483] [drm:intel_dump_pipe_config] double wide: 0
>[ 7862.136487] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7862.136491] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7862.136493] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7862.136495] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7862.136497] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7862.136500] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7862.136504] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7862.136506] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7862.136508] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7862.136510] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7862.136511] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7862.136512] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7862.136515] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7862.136517] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7862.136519] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7862.136521] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7862.136522] [drm:intel_dump_pipe_config] requested mode:
>[ 7862.136525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7862.136526] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7862.136530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7862.136533] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7862.136535] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7862.136536] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7862.136538] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7862.136540] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7862.136541] [drm:intel_dump_pipe_config] ips: 0
>[ 7862.136542] [drm:intel_dump_pipe_config] double wide: 0
>[ 7862.625148] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7862.625154] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7862.625157] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7862.625160] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7862.625163] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7862.625167] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7862.625169] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7862.625174] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7862.625177] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7862.625178] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7862.625182] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7862.625184] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7862.625185] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7862.625187] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7862.625189] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7862.625192] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7862.625195] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7862.625196] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7862.625197] [drm:intel_dump_pipe_config] requested mode:
>[ 7862.625202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7862.625203] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7862.625206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7862.625210] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7862.625211] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7862.625213] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7862.625215] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7862.625217] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7862.625218] [drm:intel_dump_pipe_config] ips: 0
>[ 7862.625219] [drm:intel_dump_pipe_config] double wide: 0
>[ 7862.625224] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7862.625227] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7862.625229] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7862.625231] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7862.625233] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7862.625236] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7862.625241] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7862.625242] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7862.625244] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7862.625246] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7862.625247] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7862.625249] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7862.625251] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7862.625253] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7862.625256] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7862.625257] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7862.625258] [drm:intel_dump_pipe_config] requested mode:
>[ 7862.625262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7862.625263] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7862.625266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7862.625269] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7862.625271] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7862.625272] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7862.625274] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7862.625276] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7862.625277] [drm:intel_dump_pipe_config] ips: 0
>[ 7862.625279] [drm:intel_dump_pipe_config] double wide: 0
>[ 7863.817206] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7863.817229] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7863.817232] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7863.817234] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7863.817238] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7863.817241] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7863.817243] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7863.817248] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7863.817251] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7863.817252] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7863.817256] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7863.817258] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7863.817259] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7863.817261] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7863.817263] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7863.817266] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7863.817268] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7863.817270] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7863.817271] [drm:intel_dump_pipe_config] requested mode:
>[ 7863.817275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7863.817276] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7863.817280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7863.817284] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7863.817285] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7863.817286] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7863.817288] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7863.817290] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7863.817291] [drm:intel_dump_pipe_config] ips: 0
>[ 7863.817293] [drm:intel_dump_pipe_config] double wide: 0
>[ 7863.817298] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7863.817301] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7863.817303] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7863.817305] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7863.817307] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7863.817310] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7863.817314] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7863.817316] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7863.817318] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7863.817319] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7863.817321] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7863.817322] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7863.817325] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7863.817327] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7863.817329] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7863.817331] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7863.817332] [drm:intel_dump_pipe_config] requested mode:
>[ 7863.817335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7863.817336] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7863.817340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7863.817343] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7863.817344] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7863.817346] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7863.817348] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7863.817350] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7863.817351] [drm:intel_dump_pipe_config] ips: 0
>[ 7863.817352] [drm:intel_dump_pipe_config] double wide: 0
>[ 7864.223294] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7864.223310] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7864.223321] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7864.223323] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7864.223327] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7864.223331] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7864.223332] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7864.223337] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7864.223340] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7864.223342] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7864.223345] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7864.223348] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7864.223349] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7864.223350] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7864.223353] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7864.223356] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7864.223358] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7864.223359] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7864.223360] [drm:intel_dump_pipe_config] requested mode:
>[ 7864.223365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7864.223366] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7864.223370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7864.223373] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7864.223375] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7864.223376] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7864.223378] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7864.223380] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7864.223381] [drm:intel_dump_pipe_config] ips: 0
>[ 7864.223382] [drm:intel_dump_pipe_config] double wide: 0
>[ 7864.223387] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7864.223390] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7864.223406] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7864.223408] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7864.223410] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7864.223413] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7864.223418] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7864.223419] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7864.223421] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7864.223423] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7864.223425] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7864.223426] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7864.223428] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7864.223431] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7864.223433] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7864.223434] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7864.223435] [drm:intel_dump_pipe_config] requested mode:
>[ 7864.223439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7864.223440] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7864.223444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7864.223447] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7864.223448] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7864.223450] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7864.223452] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7864.223453] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7864.223455] [drm:intel_dump_pipe_config] ips: 0
>[ 7864.223456] [drm:intel_dump_pipe_config] double wide: 0
>[ 7935.228493] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3906/3906
>[ 7935.228503] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[ 7935.228517] [drm:intel_edp_backlight_power] panel power control backlight disable
>[ 7935.429753] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/3906
>[ 7935.429761] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[ 7935.429847] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3906/3906
>[ 7935.429851] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[ 7935.429928] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3906/3906
>[ 7935.429932] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[ 7935.429938] [drm:intel_edp_backlight_power] panel power control backlight enable
>[ 7935.439205] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439216] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff880071ecd840 state to ffff88017a732a80
>[ 7935.439222] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff88017516d400 state to ffff88017a732a80
>[ 7935.439226] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439233] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439262] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 7935.439272] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439277] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439282] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439287] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff880071ecd540 state to ffff88017a732a80
>[ 7935.439308] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439322] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439335] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439343] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439348] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439353] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff880071ecd000 state to ffff88017a732a80
>[ 7935.439357] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439360] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439364] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439368] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439372] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439377] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880071ecd480 state to ffff88017a732a80
>[ 7935.439380] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439384] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439388] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439391] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439396] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439401] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880071ecd180 state to ffff88017a732a80
>[ 7935.439406] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff88017516d400 state to ffff88017a732a80
>[ 7935.439409] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439414] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439431] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 7935.439438] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439442] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439450] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439464] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880071ecde40 state to ffff88017a732a80
>[ 7935.439477] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439490] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439503] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439516] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439523] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439527] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880071ecd900 state to ffff88017a732a80
>[ 7935.439531] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439534] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439538] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439542] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439546] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88017a732a80
>[ 7935.439551] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880071ecdcc0 state to ffff88017a732a80
>[ 7935.439554] [drm:drm_atomic_check_only] checking ffff88017a732a80
>[ 7935.439558] [drm:drm_atomic_commit] commiting ffff88017a732a80
>[ 7935.439562] [drm:drm_atomic_state_clear] Clearing atomic state ffff88017a732a80
>[ 7935.439565] [drm:drm_atomic_state_free] Freeing atomic state ffff88017a732a80
>[ 7935.439571] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7935.439579] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7935.439584] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7935.439588] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7935.439593] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7935.439598] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7935.439602] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7935.439609] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7935.439613] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7935.439617] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7935.439622] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7935.439626] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7935.439629] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7935.439632] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7935.439636] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7935.439641] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7935.439646] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7935.439649] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7935.439652] [drm:intel_dump_pipe_config] requested mode:
>[ 7935.439658] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7935.439661] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7935.439666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7935.439672] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7935.439686] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7935.439700] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7935.439714] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7935.439728] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7935.439741] [drm:intel_dump_pipe_config] ips: 0
>[ 7935.439754] [drm:intel_dump_pipe_config] double wide: 0
>[ 7935.439768] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7935.439782] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7935.439793] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7935.439796] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7935.439801] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7935.439805] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7935.439812] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7935.439815] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7935.439819] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7935.439823] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7935.439826] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7935.439829] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7935.439833] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7935.439837] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7935.439841] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7935.439845] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7935.439847] [drm:intel_dump_pipe_config] requested mode:
>[ 7935.439853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7935.439856] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7935.439861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7935.439866] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7935.439870] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7935.439873] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7935.439876] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7935.439880] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7935.439883] [drm:intel_dump_pipe_config] ips: 0
>[ 7935.439886] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.710653] [drm:i915_gem_open] 
>[ 7938.710745] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.710752] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff880002f203c0 state to ffff88006cb3fd80
>[ 7938.710758] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff880002d96c00 state to ffff88006cb3fd80
>[ 7938.710762] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.710769] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.710795] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 7938.710806] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.710811] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.710816] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.710821] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff880002f20a80 state to ffff88006cb3fd80
>[ 7938.710825] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.710829] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.710833] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.710836] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.710841] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.710846] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff880002f209c0 state to ffff88006cb3fd80
>[ 7938.710849] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.710853] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.710857] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.710860] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.710865] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.710869] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880002f206c0 state to ffff88006cb3fd80
>[ 7938.710872] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.710876] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.710880] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.710884] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.710888] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.710892] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880002f20000 state to ffff88006cb3fd80
>[ 7938.710897] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880002d96c00 state to ffff88006cb3fd80
>[ 7938.710901] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.710906] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.710922] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 7938.710929] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.710933] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.710938] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.710943] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880002f200c0 state to ffff88006cb3fd80
>[ 7938.710946] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.710974] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.710989] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.711002] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.711017] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.711031] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880002f20c00 state to ffff88006cb3fd80
>[ 7938.711044] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.711057] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.711071] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.711084] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.711097] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88006cb3fd80
>[ 7938.711104] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880002f20d80 state to ffff88006cb3fd80
>[ 7938.711108] [drm:drm_atomic_check_only] checking ffff88006cb3fd80
>[ 7938.711111] [drm:drm_atomic_commit] commiting ffff88006cb3fd80
>[ 7938.711115] [drm:drm_atomic_state_clear] Clearing atomic state ffff88006cb3fd80
>[ 7938.711119] [drm:drm_atomic_state_free] Freeing atomic state ffff88006cb3fd80
>[ 7938.711124] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7938.711131] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7938.711136] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7938.711140] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7938.711145] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7938.711150] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7938.711154] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7938.711160] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7938.711165] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7938.711168] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7938.711173] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7938.711177] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7938.711180] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7938.711184] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7938.711188] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.711193] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7938.711197] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7938.711200] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7938.711203] [drm:intel_dump_pipe_config] requested mode:
>[ 7938.711209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7938.711212] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7938.711217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7938.711223] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7938.711226] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7938.711229] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7938.711233] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7938.711236] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7938.711239] [drm:intel_dump_pipe_config] ips: 0
>[ 7938.711242] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.711247] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7938.711252] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7938.711256] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7938.711260] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7938.711265] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7938.711269] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7938.711276] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7938.711279] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7938.711283] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7938.711286] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7938.711289] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7938.711293] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7938.711297] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.711301] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.711305] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7938.711308] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7938.711311] [drm:intel_dump_pipe_config] requested mode:
>[ 7938.711316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7938.711319] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7938.711325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7938.711330] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7938.711333] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7938.711336] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7938.711340] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7938.711343] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7938.711346] [drm:intel_dump_pipe_config] ips: 0
>[ 7938.711349] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.720799] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7938.720805] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7938.720808] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7938.720810] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7938.720814] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7938.720817] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7938.720819] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7938.720824] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7938.720827] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7938.720829] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7938.720832] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7938.720835] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7938.720836] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7938.720837] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7938.720840] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.720843] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7938.720845] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7938.720846] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7938.720847] [drm:intel_dump_pipe_config] requested mode:
>[ 7938.720852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7938.720853] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7938.720857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7938.720860] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7938.720862] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7938.720863] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7938.720865] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7938.720867] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7938.720868] [drm:intel_dump_pipe_config] ips: 0
>[ 7938.720869] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.720873] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7938.720876] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7938.720878] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7938.720880] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7938.720883] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7938.720885] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7938.720890] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7938.720892] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7938.720894] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7938.720895] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7938.720897] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7938.720898] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7938.720900] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.720903] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.720905] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7938.720906] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7938.720907] [drm:intel_dump_pipe_config] requested mode:
>[ 7938.720911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7938.720912] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7938.720916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7938.720919] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7938.720920] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7938.720922] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7938.720924] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7938.720925] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7938.720927] [drm:intel_dump_pipe_config] ips: 0
>[ 7938.720928] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.729957] [drm:i915_gem_open] 
>[ 7938.730001] [drm:drm_mode_getresources] CRTC[2] CONNECTORS[4] ENCODERS[4]
>[ 7938.731201] [drm:i915_gem_open] 
>[ 7938.731230] [drm:drm_mode_getresources] CRTC[2] CONNECTORS[4] ENCODERS[4]
>[ 7938.731237] [drm:drm_mode_getresources] CRTC[2] CONNECTORS[4] ENCODERS[4]
>[ 7938.732235] [drm:drm_mode_getresources] CRTC[2] CONNECTORS[4] ENCODERS[4]
>[ 7938.732265] [drm:add_framebuffer_internal] [FB:70]
>[ 7938.733333] [drm:drm_mode_getresources] CRTC[2] CONNECTORS[4] ENCODERS[4]
>[ 7938.733344] [drm:drm_mode_getresources] CRTC[2] CONNECTORS[4] ENCODERS[4]
>[ 7938.733468] [drm:drm_mode_getconnector] [CONNECTOR:38:?]
>[ 7938.733491] [drm:drm_mode_getconnector] [CONNECTOR:38:?]
>[ 7938.733904] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[ 7938.733917] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[ 7938.734020] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 7938.734035] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 7938.734120] [drm:drm_mode_getconnector] [CONNECTOR:36:?]
>[ 7938.734131] [drm:drm_mode_getconnector] [CONNECTOR:36:?]
>[ 7938.866235] [drm:add_framebuffer_internal] [FB:70]
>[ 7938.958738] [drm:drm_mode_setcrtc] [CRTC:20]
>[ 7938.958750] [drm:drm_mode_setcrtc] [CONNECTOR:38:eDP-1]
>[ 7938.958755] [drm:intel_crtc_set_config] [CRTC:20] [FB:70] #connectors=1 (x y) (0 0)
>[ 7938.958762] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[ 7938.958767] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7938.958770] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7938.958776] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7938.958781] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7938.958785] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7938.958791] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7938.958795] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7938.958799] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7938.958804] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7938.958808] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7938.958811] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7938.958814] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7938.958819] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.958823] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7938.958827] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7938.958831] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7938.958834] [drm:intel_dump_pipe_config] requested mode:
>[ 7938.958839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 0 71000 1366 1404 1426 1482 768 771 777 798 0x0 0xa
>[ 7938.958842] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7938.958848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7938.958853] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7938.958857] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7938.958860] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7938.958864] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7938.958867] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7938.958871] [drm:intel_dump_pipe_config] ips: 0
>[ 7938.958873] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.958881] [drm:drm_atomic_set_fb_for_plane] Set [FB:70] for plane state ffff880071ecd0c0
>[ 7938.962462] [drm:i9xx_update_primary_plane] Writing base 02E2D000 00000000 0 0 7680
>[ 7938.976367] [drm:drm_mode_setcrtc] [CRTC:25]
>[ 7938.976375] [drm:drm_mode_setcrtc] [CONNECTOR:31:HDMI-A-1]
>[ 7938.976379] [drm:intel_crtc_set_config] [CRTC:25] [FB:70] #connectors=1 (x y) (0 0)
>[ 7938.976384] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=1
>[ 7938.976389] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7938.976392] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7938.976397] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7938.976401] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7938.976408] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7938.976411] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7938.976415] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7938.976419] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7938.976422] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7938.976425] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7938.976429] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.976433] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7938.976437] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7938.976441] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7938.976443] [drm:intel_dump_pipe_config] requested mode:
>[ 7938.976449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 7938.976452] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7938.976457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 7938.976463] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[ 7938.976466] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7938.976469] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7938.976473] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7938.976476] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7938.976480] [drm:intel_dump_pipe_config] ips: 0
>[ 7938.976482] [drm:intel_dump_pipe_config] double wide: 0
>[ 7938.976488] [drm:drm_atomic_set_fb_for_plane] Set [FB:70] for plane state ffff880071ecd9c0
>[ 7938.976506] [drm:i9xx_update_primary_plane] Writing base 02E2D000 00000000 0 0 7680
>[ 7943.150716] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017a446d80
>[ 7943.160697] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017a446780
>[ 7943.175708] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175713] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff88017a4186c0 state to ffff880002d5c960
>[ 7943.175715] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175718] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175721] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175723] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175727] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175730] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff88017a418f00 state to ffff880002d5c960
>[ 7943.175732] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175734] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175736] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175738] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175740] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175743] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff88017a418000 state to ffff880002d5c960
>[ 7943.175745] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175746] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175748] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175750] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175753] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175756] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff88017a418600 state to ffff880002d5c960
>[ 7943.175757] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175759] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175761] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175763] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175766] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175768] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff88017a446d80 state to ffff880002d5c960
>[ 7943.175770] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175772] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175774] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175776] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175778] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175781] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff88017a446780 state to ffff880002d5c960
>[ 7943.175783] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175784] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175786] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175788] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175791] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175794] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff88017a3526c0 state to ffff880002d5c960
>[ 7943.175795] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175797] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175799] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175801] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175803] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c960
>[ 7943.175806] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff88017a3529c0 state to ffff880002d5c960
>[ 7943.175807] [drm:drm_atomic_check_only] checking ffff880002d5c960
>[ 7943.175809] [drm:drm_atomic_commit] commiting ffff880002d5c960
>[ 7943.175811] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c960
>[ 7943.175813] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c960
>[ 7943.175817] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.175821] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[ 7943.175823] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[ 7943.175826] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.175828] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.175832] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7943.175835] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7943.175837] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7943.175842] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7943.175844] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7943.175846] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7943.175849] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7943.175851] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7943.175853] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7943.175854] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7943.175857] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.175860] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7943.175862] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.175863] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7943.175864] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.175869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.175870] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.175874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.175877] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7943.175878] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7943.175880] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7943.175882] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.175884] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.175885] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.175886] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.175889] [drm:drm_atomic_set_fb_for_plane] Set [FB:71] for plane state ffff88017a352d80
>[ 7943.175910] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 7943.177352] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.177355] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[ 7943.177357] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=1
>[ 7943.177360] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.177361] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.177364] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7943.177367] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7943.177372] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7943.177373] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7943.177375] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7943.177377] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7943.177378] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7943.177380] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7943.177382] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.177385] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.177387] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.177388] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7943.177389] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.177393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.177394] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.177398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.177401] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7943.177402] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7943.177404] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7943.177406] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.177408] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.177409] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.177410] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.177413] [drm:drm_atomic_set_fb_for_plane] Set [FB:71] for plane state ffff88017a352900
>[ 7943.177428] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 7943.192823] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.192829] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7943.192832] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.192834] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.192837] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7943.192841] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7943.192843] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7943.192848] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7943.192850] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7943.192852] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7943.192855] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7943.192857] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7943.192859] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7943.192860] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7943.192863] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.192865] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7943.192868] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.192869] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7943.192870] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.192875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.192876] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.192879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.192883] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7943.192884] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7943.192886] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7943.192888] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.192889] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.192891] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.192892] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.192896] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.192899] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7943.192901] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.192903] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.192906] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7943.192908] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7943.192913] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7943.192914] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7943.192916] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7943.192918] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7943.192919] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7943.192921] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7943.192923] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.192925] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.192928] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.192929] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7943.192930] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.192934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.192935] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.192938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.192942] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7943.192943] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7943.192945] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7943.192946] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.192948] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.192949] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.192951] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.192971] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.192974] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7943.192976] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.192978] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.192981] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7943.192983] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7943.192985] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7943.192988] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7943.192990] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7943.192992] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7943.192994] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7943.192996] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7943.192997] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7943.192999] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7943.193001] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.193004] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7943.193006] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.193008] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7943.193009] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.193012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.193013] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.193017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.193020] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7943.193022] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7943.193023] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7943.193025] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.193027] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.193028] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.193029] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.193032] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.193035] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7943.193037] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.193039] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.193042] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7943.193044] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7943.193047] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7943.193048] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7943.193050] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7943.193052] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7943.193053] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7943.193055] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7943.193057] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.193060] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.193062] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.193063] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7943.193064] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.193068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.193069] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.193072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.193076] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7943.193077] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7943.193078] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7943.193080] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.193082] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.193083] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.193084] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.856356] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.856372] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 7943.856385] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.856387] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.856391] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 7943.856395] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 7943.856397] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 7943.856402] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 7943.856405] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 7943.856406] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 7943.856410] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 7943.856412] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 7943.856414] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 7943.856415] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 7943.856418] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.856421] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 7943.856423] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.856425] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 7943.856426] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.856430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.856431] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.856435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 7943.856439] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 7943.856440] [drm:intel_dump_pipe_config] port clock: 270000
>[ 7943.856441] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 7943.856444] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.856445] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.856447] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.856448] [drm:intel_dump_pipe_config] double wide: 0
>[ 7943.856452] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 7943.856456] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 7943.856458] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 7943.856460] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 7943.856463] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 7943.856465] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 7943.856470] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 7943.856472] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 7943.856474] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 7943.856475] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 7943.856477] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 7943.856478] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 7943.856480] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.856483] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 7943.856485] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 7943.856486] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 7943.856487] [drm:intel_dump_pipe_config] requested mode:
>[ 7943.856491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.856492] [drm:intel_dump_pipe_config] adjusted mode:
>[ 7943.856496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 7943.856499] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 7943.856500] [drm:intel_dump_pipe_config] port clock: 148500
>[ 7943.856502] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 7943.856503] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 7943.856505] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 7943.856507] [drm:intel_dump_pipe_config] ips: 0
>[ 7943.856508] [drm:intel_dump_pipe_config] double wide: 0
>[ 8134.520976] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3906/3906
>[ 8134.520985] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[ 8134.520997] [drm:intel_edp_backlight_power] panel power control backlight disable
>[ 8134.721342] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/3906
>[ 8134.721347] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[ 8134.721413] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3906/3906
>[ 8134.721417] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[ 8134.721481] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=3906/3906
>[ 8134.721485] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[ 8134.721491] [drm:intel_edp_backlight_power] panel power control backlight enable
>[ 8134.728411] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728421] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff8800028a26c0 state to ffff880002d5c720
>[ 8134.728428] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff8801755fd800 state to ffff880002d5c720
>[ 8134.728432] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728439] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728466] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 8134.728476] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728480] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728486] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728491] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff8800028a2300 state to ffff880002d5c720
>[ 8134.728495] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728499] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728503] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728507] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728511] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728516] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff8800028a2d80 state to ffff880002d5c720
>[ 8134.728519] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728523] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728527] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728530] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728535] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728540] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800028a2180 state to ffff880002d5c720
>[ 8134.728543] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728547] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728550] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728554] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728558] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728564] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800028a2000 state to ffff880002d5c720
>[ 8134.728568] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801755fd800 state to ffff880002d5c720
>[ 8134.728572] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728577] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728593] [drm:i9xx_update_primary_plane] Writing base 00853000 00000000 0 0 7680
>[ 8134.728600] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728605] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728609] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728614] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800028a2540 state to ffff880002d5c720
>[ 8134.728618] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728622] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728626] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728629] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728634] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728638] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800028a2f00 state to ffff880002d5c720
>[ 8134.728642] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728645] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728649] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728653] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728658] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880002d5c720
>[ 8134.728662] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800028a2600 state to ffff880002d5c720
>[ 8134.728665] [drm:drm_atomic_check_only] checking ffff880002d5c720
>[ 8134.728669] [drm:drm_atomic_commit] commiting ffff880002d5c720
>[ 8134.728673] [drm:drm_atomic_state_clear] Clearing atomic state ffff880002d5c720
>[ 8134.728676] [drm:drm_atomic_state_free] Freeing atomic state ffff880002d5c720
>[ 8134.728682] [drm:intel_crtc_set_config] [CRTC:20] [FB:71] #connectors=1 (x y) (0 0)
>[ 8134.728688] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 8134.728693] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 8134.728697] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 8134.728702] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 8134.728707] [drm:connected_sink_compute_bpp] [CONNECTOR:38:eDP-1] checking for sink bpp constrains
>[ 8134.728710] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 8134.728717] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 0a pixel clock 71000KHz
>[ 8134.728722] [drm:intel_dp_compute_config] DP link bw 0a lane count 1 clock 270000 bpp 18
>[ 8134.728725] [drm:intel_dp_compute_config] DP link bw required 127800 available 216000
>[ 8134.728730] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 8134.728734] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 8134.728737] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[ 8134.728741] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 8134.728745] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 8134.728750] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2481629, gmch_n: 4194304, link_m: 137868, link_n: 524288, tu: 64
>[ 8134.728754] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 8134.728757] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 8134.728760] [drm:intel_dump_pipe_config] requested mode:
>[ 8134.728766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 8134.728769] [drm:intel_dump_pipe_config] adjusted mode:
>[ 8134.728775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 71000 1366 1404 1426 1482 768 771 777 798 0x48 0xa
>[ 8134.728780] [drm:intel_dump_crtc_timings] crtc timings: 71000 1366 1404 1426 1482 768 771 777 798, type: 0x48 flags: 0xa
>[ 8134.728783] [drm:intel_dump_pipe_config] port clock: 270000
>[ 8134.728786] [drm:intel_dump_pipe_config] pipe src size: 1366x768
>[ 8134.728790] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 8134.728794] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 8134.728797] [drm:intel_dump_pipe_config] ips: 0
>[ 8134.728800] [drm:intel_dump_pipe_config] double wide: 0
>[ 8134.728805] [drm:intel_crtc_set_config] [CRTC:25] [FB:71] #connectors=1 (x y) (0 0)
>[ 8134.728810] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[ 8134.728814] [drm:intel_modeset_stage_output_state] [CONNECTOR:38:eDP-1] to [CRTC:20]
>[ 8134.728818] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:HDMI-A-1] to [CRTC:25]
>[ 8134.728822] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 8134.728827] [drm:connected_sink_compute_bpp] [CONNECTOR:31:HDMI-A-1] checking for sink bpp constrains
>[ 8134.728834] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[ 8134.728837] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[ 8134.728841] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 8134.728845] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[ 8134.728848] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 8134.728851] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 8134.728855] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 8134.728859] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 8134.728863] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 8134.728867] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[ 8134.728869] [drm:intel_dump_pipe_config] requested mode:
>[ 8134.728875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 8134.728878] [drm:intel_dump_pipe_config] adjusted mode:
>[ 8134.728883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 8134.728888] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 8134.728892] [drm:intel_dump_pipe_config] port clock: 148500
>[ 8134.728895] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 8134.728899] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 8134.728902] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 8134.728905] [drm:intel_dump_pipe_config] ips: 0
>[ 8134.728908] [drm:intel_dump_pipe_config] double wide: 0

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Attachments on bug 89456: 114067 | 114073

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