Attachment 116540 Details for Bug 90999 – Output of dmesg (see detail in description)

Output of dmesg (see detail in description)

dmesg.txt (text/plain), 634.32 KB, created by freedesktop on 2015-06-16 20:24:41 UTC

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Description:

Filename:

MIME Type:

Creator: freedesktop

Created: 2015-06-16 20:24:41 UTC

Size: 634.32 KB

patch

obsolete

>[    0.000000] Initializing cgroup subsys cpuset
>[    0.000000] Initializing cgroup subsys cpu
>[    0.000000] Initializing cgroup subsys cpuacct
>[    0.000000] Linux version 4.0.5-gnuNOUVEAUDEBUG (root@localhost) (gcc version 4.9.2 (Funtoo 4.9.2-r1) ) #5 SMP Tue Jun 16 16:07:15 EDT 2015
>[    0.000000] Command line: \vmlinuz-4.0.5-gnuNOUVEAUDEBUG 
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000008efff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000008f000-0x000000000008ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000090000-0x000000000009ffff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000000bffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000007ad13fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007ad14000-0x000000007ad52fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000007ad53000-0x000000007ad5ffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007ad60000-0x000000007ad8efff] ACPI data
>[    0.000000] BIOS-e820: [mem 0x000000007ad8f000-0x000000007ae38fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007ae39000-0x000000007ae8efff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007ae8f000-0x000000007aecffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007aed0000-0x000000007aefefff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007aeff000-0x000000007af7afff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007af7b000-0x000000007afe4fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007afe5000-0x000000007affffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007b000000-0x000000007f9fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000e00f8000-0x00000000e00f8fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000ffe10000-0x00000000ffe3ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000047f5fffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] e820: update [mem 0x6e4b5190-0x6e4cb7cf] usable ==> usable
>[    0.000000] extended physical RAM map:
>[    0.000000] reserve setup_data: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000000059000-0x000000000008efff] usable
>[    0.000000] reserve setup_data: [mem 0x000000000008f000-0x000000000008ffff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000000090000-0x000000000009ffff] usable
>[    0.000000] reserve setup_data: [mem 0x00000000000a0000-0x00000000000bffff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000000100000-0x000000006e4b518f] usable
>[    0.000000] reserve setup_data: [mem 0x000000006e4b5190-0x000000006e4cb7cf] usable
>[    0.000000] reserve setup_data: [mem 0x000000006e4cb7d0-0x000000007ad13fff] usable
>[    0.000000] reserve setup_data: [mem 0x000000007ad14000-0x000000007ad52fff] ACPI NVS
>[    0.000000] reserve setup_data: [mem 0x000000007ad53000-0x000000007ad5ffff] usable
>[    0.000000] reserve setup_data: [mem 0x000000007ad60000-0x000000007ad8efff] ACPI data
>[    0.000000] reserve setup_data: [mem 0x000000007ad8f000-0x000000007ae38fff] usable
>[    0.000000] reserve setup_data: [mem 0x000000007ae39000-0x000000007ae8efff] reserved
>[    0.000000] reserve setup_data: [mem 0x000000007ae8f000-0x000000007aecffff] usable
>[    0.000000] reserve setup_data: [mem 0x000000007aed0000-0x000000007aefefff] reserved
>[    0.000000] reserve setup_data: [mem 0x000000007aeff000-0x000000007af7afff] usable
>[    0.000000] reserve setup_data: [mem 0x000000007af7b000-0x000000007afe4fff] reserved
>[    0.000000] reserve setup_data: [mem 0x000000007afe5000-0x000000007affffff] usable
>[    0.000000] reserve setup_data: [mem 0x000000007b000000-0x000000007f9fffff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000e00f8000-0x00000000e00f8fff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000ffe10000-0x00000000ffe3ffff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000100000000-0x000000047f5fffff] usable
>[    0.000000] efi: EFI v1.10 by Apple
>[    0.000000] efi:  ACPI=0x7ad8e000  ACPI 2.0=0x7ad8e014  SMBIOS=0x7ad15000 
>[    0.000000] efi: mem00: [Conventional Memory|attr=0x080000000000000f] range=[0x0000000000000000-0x0000000000001000) (0MB)
>[    0.000000] efi: mem01: [Loader Data        |attr=0x080000000000000f] range=[0x0000000000001000-0x0000000000007000) (0MB)
>[    0.000000] efi: mem02: [Conventional Memory|attr=0x080000000000000f] range=[0x0000000000007000-0x0000000000058000) (0MB)
>[    0.000000] efi: mem03: [Reserved           |attr=0x080000000000000f] range=[0x0000000000058000-0x0000000000059000) (0MB)
>[    0.000000] efi: mem04: [Conventional Memory|attr=0x080000000000000f] range=[0x0000000000059000-0x000000000008f000) (0MB)
>[    0.000000] efi: mem05: [Reserved           |attr=0x080000000000000f] range=[0x000000000008f000-0x0000000000090000) (0MB)
>[    0.000000] efi: mem06: [Conventional Memory|attr=0x080000000000000f] range=[0x0000000000090000-0x00000000000a0000) (0MB)
>[    0.000000] efi: mem07: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000000100000-0x0000000001000000) (15MB)
>[    0.000000] efi: mem08: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000001000000-0x0000000002465000) (20MB)
>[    0.000000] efi: mem09: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000002465000-0x000000006aedc000) (1674MB)
>[    0.000000] efi: mem10: [Loader Code        |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006aedc000-0x000000006c541000) (22MB)
>[    0.000000] efi: mem11: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006c541000-0x000000006cbc7000) (6MB)
>[    0.000000] efi: mem12: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006cbc7000-0x000000006cbd2000) (0MB)
>[    0.000000] efi: mem13: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006cbd2000-0x000000006cbe4000) (0MB)
>[    0.000000] efi: mem14: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006cbe4000-0x000000006cc3f000) (0MB)
>[    0.000000] efi: mem15: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006cc3f000-0x000000006cc44000) (0MB)
>[    0.000000] efi: mem16: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006cc44000-0x000000006e4af000) (24MB)
>[    0.000000] efi: mem17: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e4af000-0x000000006e4b0000) (0MB)
>[    0.000000] efi: mem18: [Loader Data        |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e4b0000-0x000000006e4cd000) (0MB)
>[    0.000000] efi: mem19: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e4cd000-0x000000006e4f1000) (0MB)
>[    0.000000] efi: mem20: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e4f1000-0x000000006e508000) (0MB)
>[    0.000000] efi: mem21: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e508000-0x000000006e514000) (0MB)
>[    0.000000] efi: mem22: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e514000-0x000000006e51f000) (0MB)
>[    0.000000] efi: mem23: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e51f000-0x000000006e520000) (0MB)
>[    0.000000] efi: mem24: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e520000-0x000000006e534000) (0MB)
>[    0.000000] efi: mem25: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e534000-0x000000006e53e000) (0MB)
>[    0.000000] efi: mem26: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e53e000-0x000000006e548000) (0MB)
>[    0.000000] efi: mem27: [Loader Code        |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e548000-0x000000006e57a000) (0MB)
>[    0.000000] efi: mem28: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e57a000-0x000000006e57d000) (0MB)
>[    0.000000] efi: mem29: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e57d000-0x000000006e58b000) (0MB)
>[    0.000000] efi: mem30: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006e58b000-0x000000006eca1000) (7MB)
>[    0.000000] efi: mem31: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006eca1000-0x000000006edcd000) (1MB)
>[    0.000000] efi: mem32: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006edcd000-0x000000006ef60000) (1MB)
>[    0.000000] efi: mem33: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006ef60000-0x000000006ef87000) (0MB)
>[    0.000000] efi: mem34: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006ef87000-0x000000006efa9000) (0MB)
>[    0.000000] efi: mem35: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efa9000-0x000000006efaf000) (0MB)
>[    0.000000] efi: mem36: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efaf000-0x000000006efb9000) (0MB)
>[    0.000000] efi: mem37: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efb9000-0x000000006efbc000) (0MB)
>[    0.000000] efi: mem38: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efbc000-0x000000006efc1000) (0MB)
>[    0.000000] efi: mem39: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efc1000-0x000000006efc8000) (0MB)
>[    0.000000] efi: mem40: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efc8000-0x000000006efc9000) (0MB)
>[    0.000000] efi: mem41: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efc9000-0x000000006efd0000) (0MB)
>[    0.000000] efi: mem42: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efd0000-0x000000006efd2000) (0MB)
>[    0.000000] efi: mem43: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efd2000-0x000000006efd8000) (0MB)
>[    0.000000] efi: mem44: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000006efd8000-0x0000000074079000) (80MB)
>[    0.000000] efi: mem45: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000074079000-0x000000007409d000) (0MB)
>[    0.000000] efi: mem46: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007409d000-0x000000007409f000) (0MB)
>[    0.000000] efi: mem47: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007409f000-0x00000000740b3000) (0MB)
>[    0.000000] efi: mem48: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740b3000-0x00000000740b7000) (0MB)
>[    0.000000] efi: mem49: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740b7000-0x00000000740d7000) (0MB)
>[    0.000000] efi: mem50: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740d7000-0x00000000740d9000) (0MB)
>[    0.000000] efi: mem51: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740d9000-0x00000000740da000) (0MB)
>[    0.000000] efi: mem52: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740da000-0x00000000740de000) (0MB)
>[    0.000000] efi: mem53: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740de000-0x00000000740f1000) (0MB)
>[    0.000000] efi: mem54: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740f1000-0x00000000740f8000) (0MB)
>[    0.000000] efi: mem55: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000740f8000-0x0000000074103000) (0MB)
>[    0.000000] efi: mem56: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000074103000-0x0000000074104000) (0MB)
>[    0.000000] efi: mem57: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000074104000-0x000000007410b000) (0MB)
>[    0.000000] efi: mem58: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007410b000-0x000000007410e000) (0MB)
>[    0.000000] efi: mem59: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007410e000-0x0000000074112000) (0MB)
>[    0.000000] efi: mem60: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000074112000-0x0000000077416000) (51MB)
>[    0.000000] efi: mem61: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000077416000-0x000000007741b000) (0MB)
>[    0.000000] efi: mem62: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007741b000-0x0000000077420000) (0MB)
>[    0.000000] efi: mem63: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000077420000-0x0000000077425000) (0MB)
>[    0.000000] efi: mem64: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000077425000-0x0000000077428000) (0MB)
>[    0.000000] efi: mem65: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000077428000-0x0000000077429000) (0MB)
>[    0.000000] efi: mem66: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000077429000-0x000000007793e000) (5MB)
>[    0.000000] efi: mem67: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007793e000-0x0000000077943000) (0MB)
>[    0.000000] efi: mem68: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000077943000-0x000000007941a000) (26MB)
>[    0.000000] efi: mem69: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007941a000-0x000000007942a000) (0MB)
>[    0.000000] efi: mem70: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007942a000-0x0000000079441000) (0MB)
>[    0.000000] efi: mem71: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079441000-0x0000000079443000) (0MB)
>[    0.000000] efi: mem72: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079443000-0x0000000079446000) (0MB)
>[    0.000000] efi: mem73: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079446000-0x0000000079447000) (0MB)
>[    0.000000] efi: mem74: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079447000-0x000000007944a000) (0MB)
>[    0.000000] efi: mem75: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007944a000-0x000000007944b000) (0MB)
>[    0.000000] efi: mem76: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007944b000-0x000000007944e000) (0MB)
>[    0.000000] efi: mem77: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007944e000-0x000000007944f000) (0MB)
>[    0.000000] efi: mem78: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007944f000-0x0000000079450000) (0MB)
>[    0.000000] efi: mem79: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079450000-0x0000000079451000) (0MB)
>[    0.000000] efi: mem80: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079451000-0x000000007945b000) (0MB)
>[    0.000000] efi: mem81: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007945b000-0x0000000079470000) (0MB)
>[    0.000000] efi: mem82: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079470000-0x0000000079479000) (0MB)
>[    0.000000] efi: mem83: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079479000-0x000000007947a000) (0MB)
>[    0.000000] efi: mem84: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007947a000-0x0000000079489000) (0MB)
>[    0.000000] efi: mem85: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079489000-0x000000007948d000) (0MB)
>[    0.000000] efi: mem86: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007948d000-0x0000000079491000) (0MB)
>[    0.000000] efi: mem87: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079491000-0x000000007949c000) (0MB)
>[    0.000000] efi: mem88: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007949c000-0x000000007949e000) (0MB)
>[    0.000000] efi: mem89: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007949e000-0x000000007949f000) (0MB)
>[    0.000000] efi: mem90: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007949f000-0x00000000794a1000) (0MB)
>[    0.000000] efi: mem91: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794a1000-0x00000000794a2000) (0MB)
>[    0.000000] efi: mem92: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794a2000-0x00000000794a7000) (0MB)
>[    0.000000] efi: mem93: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794a7000-0x00000000794a9000) (0MB)
>[    0.000000] efi: mem94: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794a9000-0x00000000794f0000) (0MB)
>[    0.000000] efi: mem95: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794f0000-0x00000000794f9000) (0MB)
>[    0.000000] efi: mem96: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794f9000-0x00000000794fe000) (0MB)
>[    0.000000] efi: mem97: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000794fe000-0x0000000079501000) (0MB)
>[    0.000000] efi: mem98: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079501000-0x000000007951a000) (0MB)
>[    0.000000] efi: mem99: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007951a000-0x0000000079555000) (0MB)
>[    0.000000] efi: mem100: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079555000-0x0000000079576000) (0MB)
>[    0.000000] efi: mem101: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079576000-0x0000000079588000) (0MB)
>[    0.000000] efi: mem102: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079588000-0x00000000795a4000) (0MB)
>[    0.000000] efi: mem103: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795a4000-0x00000000795ae000) (0MB)
>[    0.000000] efi: mem104: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795ae000-0x00000000795af000) (0MB)
>[    0.000000] efi: mem105: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795af000-0x00000000795bb000) (0MB)
>[    0.000000] efi: mem106: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795bb000-0x00000000795bc000) (0MB)
>[    0.000000] efi: mem107: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795bc000-0x00000000795cc000) (0MB)
>[    0.000000] efi: mem108: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795cc000-0x00000000795cf000) (0MB)
>[    0.000000] efi: mem109: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795cf000-0x00000000795d4000) (0MB)
>[    0.000000] efi: mem110: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795d4000-0x00000000795d7000) (0MB)
>[    0.000000] efi: mem111: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795d7000-0x00000000795d8000) (0MB)
>[    0.000000] efi: mem112: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795d8000-0x00000000795da000) (0MB)
>[    0.000000] efi: mem113: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795da000-0x00000000795e8000) (0MB)
>[    0.000000] efi: mem114: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795e8000-0x00000000795e9000) (0MB)
>[    0.000000] efi: mem115: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795e9000-0x00000000795ea000) (0MB)
>[    0.000000] efi: mem116: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795ea000-0x00000000795ee000) (0MB)
>[    0.000000] efi: mem117: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795ee000-0x00000000795ef000) (0MB)
>[    0.000000] efi: mem118: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795ef000-0x00000000795f0000) (0MB)
>[    0.000000] efi: mem119: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795f0000-0x00000000795f1000) (0MB)
>[    0.000000] efi: mem120: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795f1000-0x00000000795f4000) (0MB)
>[    0.000000] efi: mem121: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795f4000-0x00000000795f7000) (0MB)
>[    0.000000] efi: mem122: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795f7000-0x00000000795fb000) (0MB)
>[    0.000000] efi: mem123: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000795fb000-0x0000000079605000) (0MB)
>[    0.000000] efi: mem124: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079605000-0x0000000079607000) (0MB)
>[    0.000000] efi: mem125: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079607000-0x0000000079608000) (0MB)
>[    0.000000] efi: mem126: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079608000-0x0000000079609000) (0MB)
>[    0.000000] efi: mem127: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079609000-0x000000007960a000) (0MB)
>[    0.000000] efi: mem128: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007960a000-0x000000007960b000) (0MB)
>[    0.000000] efi: mem129: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007960b000-0x0000000079615000) (0MB)
>[    0.000000] efi: mem130: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079615000-0x0000000079616000) (0MB)
>[    0.000000] efi: mem131: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079616000-0x000000007961c000) (0MB)
>[    0.000000] efi: mem132: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007961c000-0x0000000079627000) (0MB)
>[    0.000000] efi: mem133: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079627000-0x0000000079641000) (0MB)
>[    0.000000] efi: mem134: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079641000-0x0000000079643000) (0MB)
>[    0.000000] efi: mem135: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079643000-0x0000000079648000) (0MB)
>[    0.000000] efi: mem136: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079648000-0x0000000079651000) (0MB)
>[    0.000000] efi: mem137: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079651000-0x000000007965f000) (0MB)
>[    0.000000] efi: mem138: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007965f000-0x0000000079661000) (0MB)
>[    0.000000] efi: mem139: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079661000-0x0000000079663000) (0MB)
>[    0.000000] efi: mem140: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079663000-0x0000000079666000) (0MB)
>[    0.000000] efi: mem141: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079666000-0x0000000079675000) (0MB)
>[    0.000000] efi: mem142: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079675000-0x0000000079677000) (0MB)
>[    0.000000] efi: mem143: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079677000-0x000000007967e000) (0MB)
>[    0.000000] efi: mem144: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007967e000-0x000000007967f000) (0MB)
>[    0.000000] efi: mem145: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007967f000-0x0000000079683000) (0MB)
>[    0.000000] efi: mem146: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079683000-0x000000007968b000) (0MB)
>[    0.000000] efi: mem147: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007968b000-0x000000007968e000) (0MB)
>[    0.000000] efi: mem148: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007968e000-0x0000000079690000) (0MB)
>[    0.000000] efi: mem149: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079690000-0x0000000079692000) (0MB)
>[    0.000000] efi: mem150: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079692000-0x0000000079696000) (0MB)
>[    0.000000] efi: mem151: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079696000-0x00000000796a8000) (0MB)
>[    0.000000] efi: mem152: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796a8000-0x00000000796aa000) (0MB)
>[    0.000000] efi: mem153: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796aa000-0x00000000796d1000) (0MB)
>[    0.000000] efi: mem154: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796d1000-0x00000000796d3000) (0MB)
>[    0.000000] efi: mem155: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796d3000-0x00000000796d5000) (0MB)
>[    0.000000] efi: mem156: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796d5000-0x00000000796d6000) (0MB)
>[    0.000000] efi: mem157: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796d6000-0x00000000796d7000) (0MB)
>[    0.000000] efi: mem158: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796d7000-0x00000000796de000) (0MB)
>[    0.000000] efi: mem159: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796de000-0x00000000796e4000) (0MB)
>[    0.000000] efi: mem160: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796e4000-0x00000000796e6000) (0MB)
>[    0.000000] efi: mem161: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796e6000-0x00000000796ec000) (0MB)
>[    0.000000] efi: mem162: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796ec000-0x00000000796ef000) (0MB)
>[    0.000000] efi: mem163: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796ef000-0x00000000796f0000) (0MB)
>[    0.000000] efi: mem164: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796f0000-0x00000000796f1000) (0MB)
>[    0.000000] efi: mem165: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796f1000-0x00000000796f2000) (0MB)
>[    0.000000] efi: mem166: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796f2000-0x00000000796f7000) (0MB)
>[    0.000000] efi: mem167: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796f7000-0x00000000796f9000) (0MB)
>[    0.000000] efi: mem168: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796f9000-0x00000000796fe000) (0MB)
>[    0.000000] efi: mem169: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796fe000-0x00000000796ff000) (0MB)
>[    0.000000] efi: mem170: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000796ff000-0x0000000079700000) (0MB)
>[    0.000000] efi: mem171: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079700000-0x0000000079703000) (0MB)
>[    0.000000] efi: mem172: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079703000-0x0000000079705000) (0MB)
>[    0.000000] efi: mem173: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079705000-0x0000000079707000) (0MB)
>[    0.000000] efi: mem174: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079707000-0x000000007970f000) (0MB)
>[    0.000000] efi: mem175: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007970f000-0x0000000079711000) (0MB)
>[    0.000000] efi: mem176: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079711000-0x0000000079714000) (0MB)
>[    0.000000] efi: mem177: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079714000-0x0000000079718000) (0MB)
>[    0.000000] efi: mem178: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079718000-0x000000007971c000) (0MB)
>[    0.000000] efi: mem179: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007971c000-0x000000007971d000) (0MB)
>[    0.000000] efi: mem180: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007971d000-0x0000000079723000) (0MB)
>[    0.000000] efi: mem181: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079723000-0x0000000079725000) (0MB)
>[    0.000000] efi: mem182: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079725000-0x000000007972a000) (0MB)
>[    0.000000] efi: mem183: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007972a000-0x000000007972b000) (0MB)
>[    0.000000] efi: mem184: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007972b000-0x000000007972c000) (0MB)
>[    0.000000] efi: mem185: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007972c000-0x000000007972d000) (0MB)
>[    0.000000] efi: mem186: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007972d000-0x0000000079730000) (0MB)
>[    0.000000] efi: mem187: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079730000-0x0000000079731000) (0MB)
>[    0.000000] efi: mem188: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079731000-0x0000000079744000) (0MB)
>[    0.000000] efi: mem189: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079744000-0x0000000079752000) (0MB)
>[    0.000000] efi: mem190: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079752000-0x0000000079767000) (0MB)
>[    0.000000] efi: mem191: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079767000-0x000000007976a000) (0MB)
>[    0.000000] efi: mem192: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007976a000-0x000000007979d000) (0MB)
>[    0.000000] efi: mem193: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007979d000-0x00000000797b3000) (0MB)
>[    0.000000] efi: mem194: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797b3000-0x00000000797c1000) (0MB)
>[    0.000000] efi: mem195: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797c1000-0x00000000797c7000) (0MB)
>[    0.000000] efi: mem196: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797c7000-0x00000000797d9000) (0MB)
>[    0.000000] efi: mem197: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797d9000-0x00000000797db000) (0MB)
>[    0.000000] efi: mem198: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797db000-0x00000000797de000) (0MB)
>[    0.000000] efi: mem199: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797de000-0x00000000797e5000) (0MB)
>[    0.000000] efi: mem200: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797e5000-0x00000000797f3000) (0MB)
>[    0.000000] efi: mem201: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797f3000-0x00000000797f4000) (0MB)
>[    0.000000] efi: mem202: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797f4000-0x00000000797f5000) (0MB)
>[    0.000000] efi: mem203: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797f5000-0x00000000797f6000) (0MB)
>[    0.000000] efi: mem204: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797f6000-0x00000000797f8000) (0MB)
>[    0.000000] efi: mem205: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797f8000-0x00000000797fa000) (0MB)
>[    0.000000] efi: mem206: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x00000000797fa000-0x0000000079812000) (0MB)
>[    0.000000] efi: mem207: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079812000-0x000000007981a000) (0MB)
>[    0.000000] efi: mem208: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007981a000-0x000000007981b000) (0MB)
>[    0.000000] efi: mem209: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007981b000-0x000000007981c000) (0MB)
>[    0.000000] efi: mem210: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007981c000-0x0000000079821000) (0MB)
>[    0.000000] efi: mem211: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079821000-0x0000000079831000) (0MB)
>[    0.000000] efi: mem212: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079831000-0x000000007983e000) (0MB)
>[    0.000000] efi: mem213: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007983e000-0x000000007983f000) (0MB)
>[    0.000000] efi: mem214: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007983f000-0x0000000079840000) (0MB)
>[    0.000000] efi: mem215: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079840000-0x0000000079841000) (0MB)
>[    0.000000] efi: mem216: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079841000-0x0000000079843000) (0MB)
>[    0.000000] efi: mem217: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079843000-0x0000000079844000) (0MB)
>[    0.000000] efi: mem218: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079844000-0x0000000079c69000) (4MB)
>[    0.000000] efi: mem219: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c69000-0x0000000079c6f000) (0MB)
>[    0.000000] efi: mem220: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c6f000-0x0000000079c71000) (0MB)
>[    0.000000] efi: mem221: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c71000-0x0000000079c78000) (0MB)
>[    0.000000] efi: mem222: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c78000-0x0000000079c79000) (0MB)
>[    0.000000] efi: mem223: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c79000-0x0000000079c7a000) (0MB)
>[    0.000000] efi: mem224: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c7a000-0x0000000079c80000) (0MB)
>[    0.000000] efi: mem225: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c80000-0x0000000079c82000) (0MB)
>[    0.000000] efi: mem226: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c82000-0x0000000079c89000) (0MB)
>[    0.000000] efi: mem227: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c89000-0x0000000079c8a000) (0MB)
>[    0.000000] efi: mem228: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079c8a000-0x0000000079d16000) (0MB)
>[    0.000000] efi: mem229: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d16000-0x0000000079d17000) (0MB)
>[    0.000000] efi: mem230: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d17000-0x0000000079d1b000) (0MB)
>[    0.000000] efi: mem231: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d1b000-0x0000000079d1c000) (0MB)
>[    0.000000] efi: mem232: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d1c000-0x0000000079d1d000) (0MB)
>[    0.000000] efi: mem233: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d1d000-0x0000000079d22000) (0MB)
>[    0.000000] efi: mem234: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d22000-0x0000000079d27000) (0MB)
>[    0.000000] efi: mem235: [Boot Code          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d27000-0x0000000079d28000) (0MB)
>[    0.000000] efi: mem236: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000079d28000-0x000000007ad03000) (15MB)
>[    0.000000] efi: mem237: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007ad03000-0x000000007ad14000) (0MB)
>[    0.000000] efi: mem238: [ACPI Memory NVS    |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007ad14000-0x000000007ad53000) (0MB)
>[    0.000000] efi: mem239: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007ad53000-0x000000007ad60000) (0MB)
>[    0.000000] efi: mem240: [ACPI Reclaim Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007ad60000-0x000000007ad8f000) (0MB)
>[    0.000000] efi: mem241: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007ad8f000-0x000000007ae39000) (0MB)
>[    0.000000] efi: mem242: [Runtime Data       |RUN|  |  |  |   |WB|WT|WC|UC] range=[0x000000007ae39000-0x000000007ae8f000) (0MB)
>[    0.000000] efi: mem243: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007ae8f000-0x000000007aed0000) (0MB)
>[    0.000000] efi: mem244: [Runtime Code       |RUN|  |  |  |   |WB|WT|WC|UC] range=[0x000000007aed0000-0x000000007aeff000) (0MB)
>[    0.000000] efi: mem245: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007aeff000-0x000000007af7b000) (0MB)
>[    0.000000] efi: mem246: [Reserved           |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007af7b000-0x000000007afe5000) (0MB)
>[    0.000000] efi: mem247: [Boot Data          |   |  |  |  |   |WB|WT|WC|UC] range=[0x000000007afe5000-0x000000007b000000) (0MB)
>[    0.000000] efi: mem248: [Conventional Memory|   |  |  |  |   |WB|WT|WC|UC] range=[0x0000000100000000-0x000000047f600000) (14326MB)
>[    0.000000] efi: mem249: [Reserved           |RUN|  |  |  |   |  |  |  |  ] range=[0x00000000000a0000-0x00000000000c0000) (0MB)
>[    0.000000] efi: mem250: [Reserved           |RUN|  |  |  |   |  |  |  |  ] range=[0x000000007b000000-0x000000007fa00000) (74MB)
>[    0.000000] efi: mem251: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000e00f8000-0x00000000e00f9000) (0MB)
>[    0.000000] efi: mem252: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000fed1c000-0x00000000fed20000) (0MB)
>[    0.000000] efi: mem253: [Memory Mapped I/O  |RUN|  |  |  |   |  |  |  |UC] range=[0x00000000ffe10000-0x00000000ffe40000) (0MB)
>[    0.000000] SMBIOS 2.4 present.
>[    0.000000] DMI: Apple Inc. MacBookPro11,3/Mac-2BD1B31983FE1663, BIOS MBP112.88Z.0138.B02.1310181745 10/18/2013
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] e820: last_pfn = 0x47f600 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: write-back
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-DFFFF write-protect
>[    0.000000]   E0000-FFFFF uncachable
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 0080000000 mask 7F80000000 uncachable
>[    0.000000]   1 base 007C000000 mask 7FFC000000 uncachable
>[    0.000000]   2 base 007B800000 mask 7FFF800000 uncachable
>[    0.000000]   3 disabled
>[    0.000000]   4 disabled
>[    0.000000]   5 disabled
>[    0.000000]   6 disabled
>[    0.000000]   7 disabled
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] PAT configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- UC  
>[    0.000000] e820: last_pfn = 0x7b000 max_arch_pfn = 0x400000000
>[    0.000000] Scanning 1 areas for low memory corruption
>[    0.000000] Base memory trampoline at [ffff880000099000] 99000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
>[    0.000000]  [mem 0x00000000-0x000fffff] page 4k
>[    0.000000] BRK [0x022dd000, 0x022ddfff] PGTABLE
>[    0.000000] BRK [0x022de000, 0x022defff] PGTABLE
>[    0.000000] BRK [0x022df000, 0x022dffff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x47f400000-0x47f5fffff]
>[    0.000000]  [mem 0x47f400000-0x47f5fffff] page 2M
>[    0.000000] BRK [0x022e0000, 0x022e0fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x460000000-0x47f3fffff]
>[    0.000000]  [mem 0x460000000-0x47f3fffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x440000000-0x45fffffff]
>[    0.000000]  [mem 0x440000000-0x45fffffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x00100000-0x7ad13fff]
>[    0.000000]  [mem 0x00100000-0x001fffff] page 4k
>[    0.000000]  [mem 0x00200000-0x7abfffff] page 2M
>[    0.000000]  [mem 0x7ac00000-0x7ad13fff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x7ad53000-0x7ad5ffff]
>[    0.000000]  [mem 0x7ad53000-0x7ad5ffff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x7ad8f000-0x7ae38fff]
>[    0.000000]  [mem 0x7ad8f000-0x7ae38fff] page 4k
>[    0.000000] BRK [0x022e1000, 0x022e1fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x7ae8f000-0x7aecffff]
>[    0.000000]  [mem 0x7ae8f000-0x7aecffff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x7aeff000-0x7af7afff]
>[    0.000000]  [mem 0x7aeff000-0x7af7afff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x7afe5000-0x7affffff]
>[    0.000000]  [mem 0x7afe5000-0x7affffff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x100000000-0x43fffffff]
>[    0.000000]  [mem 0x100000000-0x43fffffff] page 1G
>[    0.000000] ACPI: Early table checksum verification disabled
>[    0.000000] ACPI: RSDP 0x000000007AD8E014 000024 (v02 APPLE )
>[    0.000000] ACPI: XSDT 0x000000007AD8E1C0 00009C (v01 APPLE  Apple00  00000000      01000013)
>[    0.000000] ACPI: FACP 0x000000007AD8C000 0000F4 (v05 APPLE  Apple00  00000000 Loki 0000005F)
>[    0.000000] ACPI BIOS Warning (bug): 32/64X length mismatch in FADT/Gpe0Block: 128/0 (20150204/tbfadt-618)
>[    0.000000] ACPI: DSDT 0x000000007AD80000 006BF9 (v03 APPLE  MacBookP 00110002 INTL 20100915)
>[    0.000000] ACPI: FACS 0x000000007AD1C000 000040
>[    0.000000] ACPI: HPET 0x000000007AD8B000 000038 (v01 APPLE  Apple00  00000001 Loki 0000005F)
>[    0.000000] ACPI: APIC 0x000000007AD8A000 0000BC (v02 APPLE  Apple00  00000001 Loki 0000005F)
>[    0.000000] ACPI: SBST 0x000000007AD88000 000030 (v01 APPLE  Apple00  00000001 Loki 0000005F)
>[    0.000000] ACPI: ECDT 0x000000007AD87000 000053 (v01 APPLE  Apple00  00000001 Loki 0000005F)
>[    0.000000] ACPI: SSDT 0x000000007AD7F000 00010B (v01 APPLE  SataAhci 00001000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD7E000 000024 (v01 APPLE  SmcDppt  00001000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD7C000 000688 (v01 APPLE  SDUsbLpt 00001000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD79000 000032 (v01 APPLE  SsdtS3   00001000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD65000 009CE3 (v01 APPLE  TbtPEG11 00001000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD64000 0000B8 (v01 APPLE  Sdxc     00001000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD62000 0006DE (v01 PmRef  Cpu0Ist  00003000 INTL 20100915)
>[    0.000000] ACPI: SSDT 0x000000007AD61000 000B83 (v01 PmRef  CpuPm    00003000 INTL 20100915)
>[    0.000000] ACPI: MCFG 0x000000007AD89000 00003C (v01 APPLE  Apple00  00000001 Loki 0000005F)
>[    0.000000] ACPI: DMAR 0x000000007AD60000 000088 (v01 APPLE  HSW      00000001 AAPL 00000001)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] No NUMA configuration found
>[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000047f5fffff]
>[    0.000000] NODE_DATA(0) allocated [mem 0x47f5fa000-0x47f5fdfff]
>[    0.000000]  [ffffea0000000000-ffffea0011ffffff] PMD -> [ffff88046ec00000-ffff88047ebfffff] on node 0
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000047f5fffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>[    0.000000]   node   0: [mem 0x0000000000059000-0x000000000008efff]
>[    0.000000]   node   0: [mem 0x0000000000090000-0x000000000009ffff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x000000007ad13fff]
>[    0.000000]   node   0: [mem 0x000000007ad53000-0x000000007ad5ffff]
>[    0.000000]   node   0: [mem 0x000000007ad8f000-0x000000007ae38fff]
>[    0.000000]   node   0: [mem 0x000000007ae8f000-0x000000007aecffff]
>[    0.000000]   node   0: [mem 0x000000007aeff000-0x000000007af7afff]
>[    0.000000]   node   0: [mem 0x000000007afe5000-0x000000007affffff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000047f5fffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000047f5fffff]
>[    0.000000] On node 0 totalpages: 4170816
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 22 pages reserved
>[    0.000000]   DMA zone: 3997 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 7803 pages used for memmap
>[    0.000000]   DMA32 zone: 499363 pages, LIFO batch:31
>[    0.000000]   Normal zone: 57304 pages used for memmap
>[    0.000000]   Normal zone: 3667456 pages, LIFO batch:31
>[    0.000000] ACPI: PM-Timer IO Port: 0x408
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x06] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x01] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x03] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x05] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x07] enabled)
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
>[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
>[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
>[    0.000000] smpboot: Allowing 8 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0008f000-0x0008ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000bffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x000c0000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x6e4b5000-0x6e4b5fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x6e4cb000-0x6e4cbfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ad14000-0x7ad52fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ad60000-0x7ad8efff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ae39000-0x7ae8efff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7aed0000-0x7aefefff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7af7b000-0x7afe4fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b000000-0x7f9fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7fa00000-0xe00f7fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe00f8000-0xe00f8fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe00f9000-0xfed1bfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed1c000-0xfed1ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed20000-0xffe0ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xffe10000-0xffe3ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xffe40000-0xffffffff]
>[    0.000000] e820: [mem 0x7fa00000-0xe00f7fff] available for PCI devices
>[    0.000000] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:8 nr_node_ids:1
>[    0.000000] PERCPU: Embedded 30 pages/cpu @ffff88047f200000 s85208 r8192 d29480 u262144
>[    0.000000] pcpu-alloc: s85208 r8192 d29480 u262144 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 
>[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 4105623
>[    0.000000] Policy zone: Normal
>[    0.000000] Kernel command line: root=/dev/sda7 nouveau.debug=VBIOS=trace,I2C=debug,DISP=debug,DRM=debug drm.debug=0xe \vmlinuz-4.0.5-gnuNOUVEAUDEBUG 
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] xsave: enabled xstate_bv 0x7, cntxt size 0x340 using standard form
>[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
>[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
>[    0.000000] Memory: 16104056K/16683264K available (9934K kernel code, 1146K rwdata, 3284K rodata, 1076K init, 2712K bss, 579208K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] 	RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
>[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>[    0.000000] NR_IRQS:4352 nr_irqs:488 16
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] hpet clockevent registered
>[    0.000000] tsc: Fast TSC calibration using PIT
>[    0.000000] tsc: Detected 2294.824 MHz processor
>[    0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 4589.64 BogoMIPS (lpj=2294824)
>[    0.000006] pid_max: default: 32768 minimum: 301
>[    0.000009] ACPI: Core revision 20150204
>[    0.014536] ACPI: All ACPI Tables successfully acquired
>[    0.026544] Security Framework initialized
>[    0.026547] SELinux:  Initializing.
>[    0.026552] SELinux:  Starting in permissive mode
>[    0.027142] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
>[    0.029176] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.030057] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.030069] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.030212] Initializing cgroup subsys freezer
>[    0.030230] CPU: Physical Processor ID: 0
>[    0.030232] CPU: Processor Core ID: 0
>[    0.030236] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>[    0.030238] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>[    0.030996] mce: CPU supports 10 MCE banks
>[    0.031008] CPU0: Thermal monitoring enabled (TM1)
>[    0.031017] process: using mwait in idle threads
>[    0.031020] Last level iTLB entries: 4KB 1024, 2MB 1024, 4MB 1024
>[    0.031022] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 1024, 1GB 4
>[    0.031118] Freeing SMP alternatives memory: 32K (ffffffff8202d000 - ffffffff82035000)
>[    0.035834] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.045840] TSC deadline timer enabled
>[    0.045843] smpboot: CPU0: Intel(R) Core(TM) i7-4850HQ CPU @ 2.30GHz (fam: 06, model: 46, stepping: 01)
>[    0.045861] Performance Events: PEBS fmt2+, 16-deep LBR, Haswell events, full-width counters, Intel PMU driver.
>[    0.045877] ... version:                3
>[    0.045879] ... bit width:              48
>[    0.045881] ... generic registers:      4
>[    0.045882] ... value mask:             0000ffffffffffff
>[    0.045884] ... max period:             0000ffffffffffff
>[    0.045886] ... fixed-purpose events:   3
>[    0.045888] ... event mask:             000000070000000f
>[    0.046061] x86: Booting SMP configuration:
>[    0.046063] .... node  #0, CPUs:      #1 #2 #3 #4 #5 #6 #7
>[    0.170918] x86: Booted up 1 node, 8 CPUs
>[    0.170923] smpboot: Total of 8 processors activated (36717.18 BogoMIPS)
>[    0.247178] devtmpfs: initialized
>[    0.247303] PM: Registering ACPI NVS region [mem 0x7ad14000-0x7ad52fff] (258048 bytes)
>[    0.247377] kworker/u16:0 (42) used greatest stack depth: 14000 bytes left
>[    0.247414] pinctrl core: initialized pinctrl subsystem
>[    0.247450] RTC time: 20:10:53, date: 06/16/15
>[    0.247519] NET: Registered protocol family 16
>[    0.253087] cpuidle: using governor ladder
>[    0.264107] cpuidle: using governor menu
>[    0.264161] ACPI: bus type PCI registered
>[    0.264216] PCI: MMCONFIG for domain 0000 [bus 00-9c] at [mem 0xe0000000-0xe9cfffff] (base 0xe0000000)
>[    0.264221] PCI: not using MMCONFIG
>[    0.264224] PCI: Using configuration type 1 for base access
>[    0.281361] ACPI: Added _OSI(Module Device)
>[    0.281366] ACPI: Added _OSI(Processor Device)
>[    0.281369] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.281372] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.283628] ACPI : EC: EC description table is found, configuring boot EC
>[    0.289539] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
>[    0.289722] ACPI: Dynamic OEM Table Load:
>[    0.289730] ACPI: SSDT 0xFFFF88046C1F1000 0004F0 (v01 PmRef  Cpu0Cst  00003001 INTL 20100915)
>[    0.290341] ACPI: Dynamic OEM Table Load:
>[    0.290348] ACPI: SSDT 0xFFFF88046C1F1800 00067C (v01 PmRef  ApIst    00003000 INTL 20100915)
>[    0.290975] ACPI: Dynamic OEM Table Load:
>[    0.290980] ACPI: SSDT 0xFFFF88046C6BA200 000119 (v01 PmRef  ApCst    00003000 INTL 20100915)
>[    0.292129] ACPI: Interpreter enabled
>[    0.292135] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20150204/hwxface-580)
>[    0.292141] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20150204/hwxface-580)
>[    0.292153] ACPI: (supports S0 S3 S4 S5)
>[    0.292155] ACPI: Using IOAPIC for interrupt routing
>[    0.292168] PCI: MMCONFIG for domain 0000 [bus 00-9c] at [mem 0xe0000000-0xe9cfffff] (base 0xe0000000)
>[    0.292517] PCI: MMCONFIG at [mem 0xe0000000-0xe9cfffff] reserved in ACPI motherboard resources
>[    0.292610] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.298297] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>[    0.298303] acpi PNP0A08:00: _OSC: OS assumes control of [PCIeHotplug SHPCHotplug AER PCIeCapability]
>[    0.298380] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-9c] only partially covers this bridge
>[    0.298402] PCI host bridge to bus 0000:00
>[    0.298405] pci_bus 0000:00: root bus resource [bus 00-ff]
>[    0.298408] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
>[    0.298410] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>[    0.298413] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>[    0.298417] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window]
>[    0.298420] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window]
>[    0.298424] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window]
>[    0.298427] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window]
>[    0.298431] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window]
>[    0.298434] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window]
>[    0.298438] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window]
>[    0.298441] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window]
>[    0.298445] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window]
>[    0.298448] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window]
>[    0.298451] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window]
>[    0.298455] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window]
>[    0.298458] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window]
>[    0.298462] pci_bus 0000:00: root bus resource [mem 0x7fa00000-0xfeafffff window]
>[    0.298466] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed44fff window]
>[    0.298474] pci 0000:00:00.0: [8086:0d04] type 00 class 0x060000
>[    0.298542] pci 0000:00:01.0: [8086:0d01] type 01 class 0x060400
>[    0.298580] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
>[    0.298608] pci 0000:00:01.0: System wakeup disabled by ACPI
>[    0.298636] pci 0000:00:01.1: [8086:0d05] type 01 class 0x060400
>[    0.298666] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
>[    0.298692] pci 0000:00:01.1: System wakeup disabled by ACPI
>[    0.298746] pci 0000:00:14.0: [8086:8c31] type 00 class 0x0c0330
>[    0.298765] pci 0000:00:14.0: reg 0x10: [mem 0xc1e00000-0xc1e0ffff 64bit]
>[    0.298821] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    0.298842] pci 0000:00:14.0: System wakeup disabled by ACPI
>[    0.298879] pci 0000:00:16.0: [8086:8c3a] type 00 class 0x078000
>[    0.298896] pci 0000:00:16.0: reg 0x10: [mem 0xc1e19100-0xc1e1910f 64bit]
>[    0.298954] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
>[    0.299015] pci 0000:00:1b.0: [8086:8c20] type 00 class 0x040300
>[    0.299030] pci 0000:00:1b.0: reg 0x10: [mem 0xc1e14000-0xc1e17fff 64bit]
>[    0.299094] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>[    0.299116] pci 0000:00:1b.0: System wakeup disabled by ACPI
>[    0.299156] pci 0000:00:1c.0: [8086:8c10] type 01 class 0x060400
>[    0.299221] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    0.299277] pci 0000:00:1c.2: [8086:8c14] type 01 class 0x060400
>[    0.299346] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold
>[    0.299371] pci 0000:00:1c.2: System wakeup disabled by ACPI
>[    0.299406] pci 0000:00:1c.3: [8086:8c16] type 01 class 0x060400
>[    0.299476] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
>[    0.299500] pci 0000:00:1c.3: System wakeup disabled by ACPI
>[    0.299535] pci 0000:00:1c.4: [8086:8c18] type 01 class 0x060400
>[    0.299617] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
>[    0.299638] pci 0000:00:1c.4: System wakeup disabled by ACPI
>[    0.299672] pci 0000:00:1f.0: [8086:8c4b] type 00 class 0x060100
>[    0.299800] pci 0000:00:1f.3: [8086:8c22] type 00 class 0x0c0500
>[    0.299812] pci 0000:00:1f.3: reg 0x10: [mem 0xc1e19000-0xc1e190ff 64bit]
>[    0.299829] pci 0000:00:1f.3: reg 0x20: [io  0xefa0-0xefbf]
>[    0.299908] pci 0000:01:00.0: [10de:0fe9] type 00 class 0x030000
>[    0.299918] pci 0000:01:00.0: reg 0x10: [mem 0xc0000000-0xc0ffffff]
>[    0.299927] pci 0000:01:00.0: reg 0x14: [mem 0x80000000-0x8fffffff 64bit pref]
>[    0.299936] pci 0000:01:00.0: reg 0x1c: [mem 0x90000000-0x91ffffff 64bit pref]
>[    0.299943] pci 0000:01:00.0: reg 0x24: [io  0x1000-0x107f]
>[    0.299949] pci 0000:01:00.0: reg 0x30: [mem 0xc1000000-0xc107ffff pref]
>[    0.300007] pci 0000:01:00.0: System wakeup disabled by ACPI
>[    0.300044] pci 0000:01:00.1: [10de:0e1b] type 00 class 0x040300
>[    0.300052] pci 0000:01:00.1: reg 0x10: [mem 0xc1080000-0xc1083fff]
>[    0.304173] pci 0000:00:01.0: PCI bridge to [bus 01]
>[    0.304178] pci 0000:00:01.0:   bridge window [io  0x1000-0x1fff]
>[    0.304180] pci 0000:00:01.0:   bridge window [mem 0xc0000000-0xc10fffff]
>[    0.304183] pci 0000:00:01.0:   bridge window [mem 0x80000000-0x91ffffff 64bit pref]
>[    0.304223] pci 0000:06:00.0: [8086:156d] type 01 class 0x060400
>[    0.304307] pci 0000:06:00.0: supports D1 D2
>[    0.304308] pci 0000:06:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.306164] pci 0000:00:01.1: PCI bridge to [bus 06-9c]
>[    0.306168] pci 0000:00:01.1:   bridge window [io  0x3000-0x5fff]
>[    0.306170] pci 0000:00:01.1:   bridge window [mem 0xc1f00000-0xcdffffff]
>[    0.306173] pci 0000:00:01.1:   bridge window [mem 0xce000000-0xd9ffffff 64bit pref]
>[    0.306226] pci 0000:07:00.0: [8086:156d] type 01 class 0x060400
>[    0.306314] pci 0000:07:00.0: supports D1 D2
>[    0.306316] pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.306375] pci 0000:07:03.0: [8086:156d] type 01 class 0x060400
>[    0.306457] pci 0000:07:03.0: supports D1 D2
>[    0.306458] pci 0000:07:03.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.306512] pci 0000:07:04.0: [8086:156d] type 01 class 0x060400
>[    0.306594] pci 0000:07:04.0: supports D1 D2
>[    0.306595] pci 0000:07:04.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.306652] pci 0000:07:05.0: [8086:156d] type 01 class 0x060400
>[    0.306734] pci 0000:07:05.0: supports D1 D2
>[    0.306735] pci 0000:07:05.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.306791] pci 0000:07:06.0: [8086:156d] type 01 class 0x060400
>[    0.306872] pci 0000:07:06.0: supports D1 D2
>[    0.306873] pci 0000:07:06.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.306940] pci 0000:06:00.0: PCI bridge to [bus 07-6c]
>[    0.306946] pci 0000:06:00.0:   bridge window [io  0x3000-0x4fff]
>[    0.306949] pci 0000:06:00.0:   bridge window [mem 0xc1f00000-0xc9ffffff]
>[    0.306954] pci 0000:06:00.0:   bridge window [mem 0xce000000-0xd5ffffff 64bit pref]
>[    0.307010] pci 0000:08:00.0: [8086:156c] type 00 class 0x088000
>[    0.307026] pci 0000:08:00.0: reg 0x10: [mem 0xc1f00000-0xc1f3ffff]
>[    0.307036] pci 0000:08:00.0: reg 0x14: [mem 0xc1f40000-0xc1f40fff]
>[    0.307162] pci 0000:08:00.0: supports D1 D2
>[    0.307163] pci 0000:08:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.309172] pci 0000:07:00.0: PCI bridge to [bus 08]
>[    0.309181] pci 0000:07:00.0:   bridge window [mem 0xc1f00000-0xc1ffffff]
>[    0.309229] pci 0000:07:03.0: PCI bridge to [bus 09-39]
>[    0.309235] pci 0000:07:03.0:   bridge window [io  0x3000-0x3fff]
>[    0.309238] pci 0000:07:03.0:   bridge window [mem 0xc2000000-0xc5ffffff]
>[    0.309243] pci 0000:07:03.0:   bridge window [mem 0xce000000-0xd1ffffff 64bit pref]
>[    0.309286] pci 0000:07:04.0: PCI bridge to [bus 3a]
>[    0.309338] pci 0000:07:05.0: PCI bridge to [bus 3b-6b]
>[    0.309345] pci 0000:07:05.0:   bridge window [io  0x4000-0x4fff]
>[    0.309348] pci 0000:07:05.0:   bridge window [mem 0xc6000000-0xc9ffffff]
>[    0.309352] pci 0000:07:05.0:   bridge window [mem 0xd2000000-0xd5ffffff 64bit pref]
>[    0.309395] pci 0000:07:06.0: PCI bridge to [bus 6c]
>[    0.309478] pci 0000:00:1c.0: PCI bridge to [bus 02]
>[    0.309602] pci 0000:03:00.0: [14e4:43a0] type 00 class 0x028000
>[    0.309642] pci 0000:03:00.0: reg 0x10: [mem 0xc1a00000-0xc1a07fff 64bit]
>[    0.309669] pci 0000:03:00.0: reg 0x18: [mem 0xc1800000-0xc19fffff 64bit]
>[    0.309868] pci 0000:03:00.0: supports D1 D2
>[    0.309869] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.309908] pci 0000:03:00.0: System wakeup disabled by ACPI
>[    0.311215] pci 0000:00:1c.2: PCI bridge to [bus 03]
>[    0.311223] pci 0000:00:1c.2:   bridge window [mem 0xc1800000-0xc1afffff]
>[    0.311300] pci 0000:04:00.0: [14e4:1570] type 00 class 0x048000
>[    0.311323] pci 0000:04:00.0: reg 0x10: [mem 0xc1d00000-0xc1d0ffff 64bit]
>[    0.311339] pci 0000:04:00.0: reg 0x18: [mem 0xa0000000-0xafffffff 64bit pref]
>[    0.311355] pci 0000:04:00.0: reg 0x20: [mem 0xc1c00000-0xc1cfffff 64bit]
>[    0.311445] pci 0000:04:00.0: supports D1
>[    0.311447] pci 0000:04:00.0: PME# supported from D0 D3hot
>[    0.313183] pci 0000:00:1c.3: PCI bridge to [bus 04]
>[    0.313191] pci 0000:00:1c.3:   bridge window [mem 0xc1c00000-0xc1dfffff]
>[    0.313196] pci 0000:00:1c.3:   bridge window [mem 0xa0000000-0xafffffff 64bit pref]
>[    0.313314] pci 0000:05:00.0: [144d:1600] type 00 class 0x010601
>[    0.313377] pci 0000:05:00.0: reg 0x24: [mem 0xc1b00000-0xc1b01fff]
>[    0.313388] pci 0000:05:00.0: reg 0x30: [mem 0xffff0000-0xffffffff pref]
>[    0.313456] pci 0000:05:00.0: PME# supported from D3hot D3cold
>[    0.315187] pci 0000:00:1c.4: PCI bridge to [bus 05]
>[    0.315194] pci 0000:00:1c.4:   bridge window [mem 0xc1b00000-0xc1bfffff]
>[    0.316095] ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 12 14 15) *0, disabled.
>[    0.316155] ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 11 12 14 15) *0, disabled.
>[    0.316214] ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *0, disabled.
>[    0.316269] ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 11 12 14 15) *0, disabled.
>[    0.316323] ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *0, disabled.
>[    0.316372] ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 11 12 14 15) *0, disabled.
>[    0.316421] ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *0, disabled.
>[    0.316469] ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 11 12 14 15) *0, disabled.
>[    0.316612] ACPI: Enabled 2 GPEs in block 00 to 3F
>[    0.316640] ACPI : EC: GPE = 0x17, I/O: command/status = 0x66, data = 0x62
>[    0.316729] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,locks=none
>[    0.316734] vgaarb: loaded
>[    0.316737] vgaarb: setting as boot device: PCI:0000:01:00.0
>[    0.316740] vgaarb: bridge control possible 0000:01:00.0
>[    0.316800] SCSI subsystem initialized
>[    0.316843] libata version 3.00 loaded.
>[    0.316875] ACPI: bus type USB registered
>[    0.316908] usbcore: registered new interface driver usbfs
>[    0.316916] usbcore: registered new interface driver hub
>[    0.316936] usbcore: registered new device driver usb
>[    0.316955] Linux video capture interface: v2.00
>[    0.316964] pps_core: LinuxPPS API ver. 1 registered
>[    0.316966] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    0.316973] PTP clock support registered
>[    0.317057] wmi: Mapper loaded
>[    0.317076] Advanced Linux Sound Architecture Driver Initialized.
>[    0.317079] PCI: Using ACPI for IRQ routing
>[    0.320344] PCI: pci_cache_line_size set to 64 bytes
>[    0.320496] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    0.320497] e820: reserve RAM buffer [mem 0x0008f000-0x0008ffff]
>[    0.320498] e820: reserve RAM buffer [mem 0x6e4b5190-0x6fffffff]
>[    0.320499] e820: reserve RAM buffer [mem 0x7ad14000-0x7bffffff]
>[    0.320500] e820: reserve RAM buffer [mem 0x7ad60000-0x7bffffff]
>[    0.320501] e820: reserve RAM buffer [mem 0x7ae39000-0x7bffffff]
>[    0.320502] e820: reserve RAM buffer [mem 0x7aed0000-0x7bffffff]
>[    0.320503] e820: reserve RAM buffer [mem 0x7af7b000-0x7bffffff]
>[    0.320504] e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff]
>[    0.320505] e820: reserve RAM buffer [mem 0x47f600000-0x47fffffff]
>[    0.320620] cfg80211: Calling CRDA to update world regulatory domain
>[    0.320629] NetLabel: Initializing
>[    0.320632] NetLabel:  domain hash size = 128
>[    0.320634] NetLabel:  protocols = UNLABELED CIPSOv4
>[    0.320647] NetLabel:  unlabeled traffic allowed by default
>[    0.320716] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    0.320722] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
>[    0.322758] Switched to clocksource hpet
>[    0.326080] pnp: PnP ACPI init
>[    0.326562] system 00:00: [mem 0xfed00000-0xfed003ff] has been reserved
>[    0.326566] system 00:00: Plug and Play ACPI device, IDs PNP0103 PNP0c01 (active)
>[    0.326591] system 00:01: [io  0xffff] has been reserved
>[    0.326594] system 00:01: [io  0x0400-0x047f] could not be reserved
>[    0.326597] system 00:01: [io  0x0800-0x087f] has been reserved
>[    0.326599] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.326612] pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    0.326650] pnp 00:03: Plug and Play ACPI device, IDs APP000b (active)
>[    0.326733] system 00:04: [mem 0xfed1c000-0xfed1ffff] has been reserved
>[    0.326736] system 00:04: [mem 0xfed10000-0xfed17fff] has been reserved
>[    0.326738] system 00:04: [mem 0xfed18000-0xfed18fff] has been reserved
>[    0.326740] system 00:04: [mem 0xfed19000-0xfed19fff] has been reserved
>[    0.326744] system 00:04: [mem 0xe0000000-0xefffffff] could not be reserved
>[    0.326746] system 00:04: [mem 0xfed20000-0xfed3ffff] has been reserved
>[    0.326748] system 00:04: [mem 0xfed90000-0xfed93fff] has been reserved
>[    0.326751] system 00:04: [mem 0xfed45000-0xfed8ffff] has been reserved
>[    0.326772] system 00:04: [mem 0xff000000-0xffffffff] could not be reserved
>[    0.326774] system 00:04: [mem 0xfee00000-0xfeefffff] has been reserved
>[    0.326777] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.326805] system 00:05: [mem 0x20000000-0x201fffff] could not be reserved
>[    0.326808] system 00:05: [mem 0x40000000-0x401fffff] could not be reserved
>[    0.326810] system 00:05: Plug and Play ACPI device, IDs PNP0c01 (active)
>[    0.326899] pnp: PnP ACPI: found 6 devices
>[    0.332637] pci 0000:05:00.0: can't claim BAR 6 [mem 0xffff0000-0xffffffff pref]: no compatible bridge window
>[    0.332650] pci 0000:07:00.0: bridge window [io  0x1000-0x0fff] to [bus 08] add_size 1000
>[    0.332652] pci 0000:07:00.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 08] add_size 200000
>[    0.332663] pci 0000:07:04.0: bridge window [io  0x1000-0x0fff] to [bus 3a] add_size 1000
>[    0.332664] pci 0000:07:04.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 3a] add_size 200000
>[    0.332665] pci 0000:07:04.0: bridge window [mem 0x00100000-0x000fffff] to [bus 3a] add_size 200000
>[    0.332675] pci 0000:07:06.0: bridge window [io  0x1000-0x0fff] to [bus 6c] add_size 1000
>[    0.332676] pci 0000:07:06.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 6c] add_size 200000
>[    0.332677] pci 0000:07:06.0: bridge window [mem 0x00100000-0x000fffff] to [bus 6c] add_size 200000
>[    0.332696] pci 0000:00:1c.0: bridge window [io  0x1000-0x0fff] to [bus 02] add_size 1000
>[    0.332697] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000
>[    0.332698] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000
>[    0.332717] pci 0000:00:1c.0: res[8]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000
>[    0.332718] pci 0000:00:1c.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[    0.332719] pci 0000:00:1c.0: res[7]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[    0.332724] pci 0000:00:1c.0: BAR 8: assigned [mem 0x7fa00000-0x7fbfffff]
>[    0.332731] pci 0000:00:1c.0: BAR 9: assigned [mem 0x7fc00000-0x7fdfffff 64bit pref]
>[    0.332735] pci 0000:00:1c.0: BAR 7: assigned [io  0x2000-0x2fff]
>[    0.332738] pci 0000:00:01.0: PCI bridge to [bus 01]
>[    0.332741] pci 0000:00:01.0:   bridge window [io  0x1000-0x1fff]
>[    0.332744] pci 0000:00:01.0:   bridge window [mem 0xc0000000-0xc10fffff]
>[    0.332760] pci 0000:00:01.0:   bridge window [mem 0x80000000-0x91ffffff 64bit pref]
>[    0.332771] pci 0000:07:00.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[    0.332772] pci 0000:07:04.0: res[8]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000
>[    0.332773] pci 0000:07:04.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[    0.332774] pci 0000:07:06.0: res[8]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000
>[    0.332775] pci 0000:07:06.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[    0.332776] pci 0000:07:00.0: res[7]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[    0.332777] pci 0000:07:04.0: res[7]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[    0.332778] pci 0000:07:06.0: res[7]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[    0.332781] pci 0000:07:00.0: BAR 9: no space for [mem size 0x00200000 64bit pref]
>[    0.332784] pci 0000:07:00.0: BAR 9: failed to assign [mem size 0x00200000 64bit pref]
>[    0.332788] pci 0000:07:04.0: BAR 8: no space for [mem size 0x00200000]
>[    0.332790] pci 0000:07:04.0: BAR 8: failed to assign [mem size 0x00200000]
>[    0.332793] pci 0000:07:04.0: BAR 9: no space for [mem size 0x00200000 64bit pref]
>[    0.332796] pci 0000:07:04.0: BAR 9: failed to assign [mem size 0x00200000 64bit pref]
>[    0.332799] pci 0000:07:06.0: BAR 8: no space for [mem size 0x00200000]
>[    0.332801] pci 0000:07:06.0: BAR 8: failed to assign [mem size 0x00200000]
>[    0.332804] pci 0000:07:06.0: BAR 9: no space for [mem size 0x00200000 64bit pref]
>[    0.332807] pci 0000:07:06.0: BAR 9: failed to assign [mem size 0x00200000 64bit pref]
>[    0.332811] pci 0000:07:00.0: BAR 7: no space for [io  size 0x1000]
>[    0.332813] pci 0000:07:00.0: BAR 7: failed to assign [io  size 0x1000]
>[    0.332815] pci 0000:07:04.0: BAR 7: no space for [io  size 0x1000]
>[    0.332817] pci 0000:07:04.0: BAR 7: failed to assign [io  size 0x1000]
>[    0.332819] pci 0000:07:06.0: BAR 7: no space for [io  size 0x1000]
>[    0.332822] pci 0000:07:06.0: BAR 7: failed to assign [io  size 0x1000]
>[    0.332824] pci 0000:07:06.0: BAR 8: no space for [mem size 0x00200000]
>[    0.332827] pci 0000:07:06.0: BAR 8: failed to assign [mem size 0x00200000]
>[    0.332830] pci 0000:07:06.0: BAR 9: no space for [mem size 0x00200000 64bit pref]
>[    0.332833] pci 0000:07:06.0: BAR 9: failed to assign [mem size 0x00200000 64bit pref]
>[    0.332836] pci 0000:07:06.0: BAR 7: no space for [io  size 0x1000]
>[    0.332838] pci 0000:07:06.0: BAR 7: failed to assign [io  size 0x1000]
>[    0.332840] pci 0000:07:04.0: BAR 8: no space for [mem size 0x00200000]
>[    0.332842] pci 0000:07:04.0: BAR 8: failed to assign [mem size 0x00200000]
>[    0.332845] pci 0000:07:04.0: BAR 9: no space for [mem size 0x00200000 64bit pref]
>[    0.332849] pci 0000:07:04.0: BAR 9: failed to assign [mem size 0x00200000 64bit pref]
>[    0.332852] pci 0000:07:04.0: BAR 7: no space for [io  size 0x1000]
>[    0.332854] pci 0000:07:04.0: BAR 7: failed to assign [io  size 0x1000]
>[    0.332857] pci 0000:07:00.0: BAR 9: no space for [mem size 0x00200000 64bit pref]
>[    0.332860] pci 0000:07:00.0: BAR 9: failed to assign [mem size 0x00200000 64bit pref]
>[    0.332863] pci 0000:07:00.0: BAR 7: no space for [io  size 0x1000]
>[    0.332865] pci 0000:07:00.0: BAR 7: failed to assign [io  size 0x1000]
>[    0.332868] pci 0000:07:00.0: PCI bridge to [bus 08]
>[    0.332872] pci 0000:07:00.0:   bridge window [mem 0xc1f00000-0xc1ffffff]
>[    0.332879] pci 0000:07:03.0: PCI bridge to [bus 09-39]
>[    0.332882] pci 0000:07:03.0:   bridge window [io  0x3000-0x3fff]
>[    0.332886] pci 0000:07:03.0:   bridge window [mem 0xc2000000-0xc5ffffff]
>[    0.332890] pci 0000:07:03.0:   bridge window [mem 0xce000000-0xd1ffffff 64bit pref]
>[    0.332896] pci 0000:07:04.0: PCI bridge to [bus 3a]
>[    0.332905] pci 0000:07:05.0: PCI bridge to [bus 3b-6b]
>[    0.332908] pci 0000:07:05.0:   bridge window [io  0x4000-0x4fff]
>[    0.332913] pci 0000:07:05.0:   bridge window [mem 0xc6000000-0xc9ffffff]
>[    0.332916] pci 0000:07:05.0:   bridge window [mem 0xd2000000-0xd5ffffff 64bit pref]
>[    0.332923] pci 0000:07:06.0: PCI bridge to [bus 6c]
>[    0.332932] pci 0000:06:00.0: PCI bridge to [bus 07-6c]
>[    0.332934] pci 0000:06:00.0:   bridge window [io  0x3000-0x4fff]
>[    0.332939] pci 0000:06:00.0:   bridge window [mem 0xc1f00000-0xc9ffffff]
>[    0.332943] pci 0000:06:00.0:   bridge window [mem 0xce000000-0xd5ffffff 64bit pref]
>[    0.332949] pci 0000:00:01.1: PCI bridge to [bus 06-9c]
>[    0.332951] pci 0000:00:01.1:   bridge window [io  0x3000-0x5fff]
>[    0.332954] pci 0000:00:01.1:   bridge window [mem 0xc1f00000-0xcdffffff]
>[    0.332957] pci 0000:00:01.1:   bridge window [mem 0xce000000-0xd9ffffff 64bit pref]
>[    0.332961] pci 0000:00:1c.0: PCI bridge to [bus 02]
>[    0.332970] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
>[    0.332975] pci 0000:00:1c.0:   bridge window [mem 0x7fa00000-0x7fbfffff]
>[    0.332979] pci 0000:00:1c.0:   bridge window [mem 0x7fc00000-0x7fdfffff 64bit pref]
>[    0.332986] pci 0000:00:1c.2: PCI bridge to [bus 03]
>[    0.332992] pci 0000:00:1c.2:   bridge window [mem 0xc1800000-0xc1afffff]
>[    0.333000] pci 0000:00:1c.3: PCI bridge to [bus 04]
>[    0.333005] pci 0000:00:1c.3:   bridge window [mem 0xc1c00000-0xc1dfffff]
>[    0.333009] pci 0000:00:1c.3:   bridge window [mem 0xa0000000-0xafffffff 64bit pref]
>[    0.333017] pci 0000:05:00.0: BAR 6: assigned [mem 0xc1b10000-0xc1b1ffff pref]
>[    0.333020] pci 0000:00:1c.4: PCI bridge to [bus 05]
>[    0.333030] pci 0000:00:1c.4:   bridge window [mem 0xc1b00000-0xc1bfffff]
>[    0.333039] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
>[    0.333040] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
>[    0.333041] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
>[    0.333042] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window]
>[    0.333043] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window]
>[    0.333044] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window]
>[    0.333045] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window]
>[    0.333046] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window]
>[    0.333047] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window]
>[    0.333048] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window]
>[    0.333048] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window]
>[    0.333049] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window]
>[    0.333050] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window]
>[    0.333051] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window]
>[    0.333052] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window]
>[    0.333053] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff window]
>[    0.333054] pci_bus 0000:00: resource 20 [mem 0x7fa00000-0xfeafffff window]
>[    0.333055] pci_bus 0000:00: resource 21 [mem 0xfed40000-0xfed44fff window]
>[    0.333056] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
>[    0.333057] pci_bus 0000:01: resource 1 [mem 0xc0000000-0xc10fffff]
>[    0.333058] pci_bus 0000:01: resource 2 [mem 0x80000000-0x91ffffff 64bit pref]
>[    0.333059] pci_bus 0000:06: resource 0 [io  0x3000-0x5fff]
>[    0.333060] pci_bus 0000:06: resource 1 [mem 0xc1f00000-0xcdffffff]
>[    0.333061] pci_bus 0000:06: resource 2 [mem 0xce000000-0xd9ffffff 64bit pref]
>[    0.333062] pci_bus 0000:07: resource 0 [io  0x3000-0x4fff]
>[    0.333063] pci_bus 0000:07: resource 1 [mem 0xc1f00000-0xc9ffffff]
>[    0.333063] pci_bus 0000:07: resource 2 [mem 0xce000000-0xd5ffffff 64bit pref]
>[    0.333064] pci_bus 0000:08: resource 1 [mem 0xc1f00000-0xc1ffffff]
>[    0.333066] pci_bus 0000:09: resource 0 [io  0x3000-0x3fff]
>[    0.333066] pci_bus 0000:09: resource 1 [mem 0xc2000000-0xc5ffffff]
>[    0.333067] pci_bus 0000:09: resource 2 [mem 0xce000000-0xd1ffffff 64bit pref]
>[    0.333068] pci_bus 0000:3b: resource 0 [io  0x4000-0x4fff]
>[    0.333069] pci_bus 0000:3b: resource 1 [mem 0xc6000000-0xc9ffffff]
>[    0.333070] pci_bus 0000:3b: resource 2 [mem 0xd2000000-0xd5ffffff 64bit pref]
>[    0.333071] pci_bus 0000:02: resource 0 [io  0x2000-0x2fff]
>[    0.333072] pci_bus 0000:02: resource 1 [mem 0x7fa00000-0x7fbfffff]
>[    0.333073] pci_bus 0000:02: resource 2 [mem 0x7fc00000-0x7fdfffff 64bit pref]
>[    0.333074] pci_bus 0000:03: resource 1 [mem 0xc1800000-0xc1afffff]
>[    0.333075] pci_bus 0000:04: resource 1 [mem 0xc1c00000-0xc1dfffff]
>[    0.333076] pci_bus 0000:04: resource 2 [mem 0xa0000000-0xafffffff 64bit pref]
>[    0.333077] pci_bus 0000:05: resource 1 [mem 0xc1b00000-0xc1bfffff]
>[    0.333097] NET: Registered protocol family 2
>[    0.333245] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
>[    0.333389] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>[    0.333496] TCP: Hash tables configured (established 131072 bind 65536)
>[    0.333508] TCP: reno registered
>[    0.333521] UDP hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.333559] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.333616] NET: Registered protocol family 1
>[    0.333667] RPC: Registered named UNIX socket transport module.
>[    0.333669] RPC: Registered udp transport module.
>[    0.333671] RPC: Registered tcp transport module.
>[    0.333673] RPC: Registered tcp NFSv4.1 backchannel transport module.
>[    0.333936] PCI: CLS 256 bytes, default 64
>[    0.333965] dmar: Host address width 39
>[    0.333968] dmar: DRHD base: 0x000000fed90000 flags: 0x0
>[    0.333976] dmar: IOMMU 0: reg_base_addr fed90000 ver 1:0 cap c0000020660462 ecap f0101a
>[    0.333979] dmar: DRHD base: 0x000000fed91000 flags: 0x1
>[    0.333984] dmar: IOMMU 1: reg_base_addr fed91000 ver 1:0 cap d2008020660462 ecap f010da
>[    0.333987] dmar: RMRR base: 0x0000007b800000 end: 0x0000007f9fffff
>[    0.333993] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    0.333996] software IO TLB [mem 0x68bc7000-0x6cbc7000] (64MB) mapped at [ffff880068bc7000-ffff88006cbc6fff]
>[    0.334273] microcode: CPU0 sig=0x40661, pf=0x20, revision=0xf
>[    0.334278] microcode: CPU1 sig=0x40661, pf=0x20, revision=0xf
>[    0.334284] microcode: CPU2 sig=0x40661, pf=0x20, revision=0xf
>[    0.334297] microcode: CPU3 sig=0x40661, pf=0x20, revision=0xf
>[    0.334308] microcode: CPU4 sig=0x40661, pf=0x20, revision=0xf
>[    0.334313] microcode: CPU5 sig=0x40661, pf=0x20, revision=0xf
>[    0.334324] microcode: CPU6 sig=0x40661, pf=0x20, revision=0xf
>[    0.334329] microcode: CPU7 sig=0x40661, pf=0x20, revision=0xf
>[    0.334357] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[    0.334619] Scanning for low memory corruption every 60 seconds
>[    0.334826] futex hash table entries: 2048 (order: 5, 131072 bytes)
>[    0.334851] audit: initializing netlink subsys (disabled)
>[    0.334862] audit: type=2000 audit(1434485453.232:1): initialized
>[    0.335003] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[    0.336068] VFS: Disk quotas dquot_6.5.2
>[    0.336091] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>[    0.336485] NFS: Registering the id_resolver key type
>[    0.336492] Key type id_resolver registered
>[    0.336494] Key type id_legacy registered
>[    0.336524] fuse init (API version 7.23)
>[    0.336632] SELinux:  Registering netfilter hooks
>[    0.336927] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
>[    0.336933] io scheduler noop registered
>[    0.336936] io scheduler deadline registered
>[    0.336966] io scheduler cfq registered (default)
>[    0.337182] pcieport 0000:00:1c.0: enabling device (0000 -> 0003)
>[    0.337713] pcieport 0000:07:03.0: enabling device (0000 -> 0003)
>[    0.337977] pcieport 0000:07:05.0: enabling device (0000 -> 0003)
>[    0.338229] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[    0.339021] nvidiafb 0000:01:00.0: enabling device (0006 -> 0007)
>[    0.339087] nvidiafb: Device ID: 10de0fe9 
>[    0.339089] nvidiafb: unknown NV_ARCH
>[    0.339131] efifb: probing for efifb
>[    0.339150] efifb: framebuffer at 0x80020000, mapped to 0xffffc9000c980000, using 28800k, total 28800k
>[    0.339153] efifb: mode is 2880x1800x32, linelength=16384, pages=1
>[    0.339155] efifb: scrolling: redraw
>[    0.339157] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
>[    0.353520] Console: switching to colour frame buffer device 360x112
>[    0.367689] fb0: EFI VGA frame buffer device
>[    0.367714] intel_idle: MWAIT substates: 0x42120
>[    0.367715] intel_idle: v0.4 model 0x46
>[    0.367715] intel_idle: lapic_timer_reliable_states 0xffffffff
>[    0.367985] ACPI: AC Adapter [ADP1] (on-line)
>[    0.368083] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0
>[    0.368133] ACPI: Lid Switch [LID0]
>[    0.368177] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>[    0.368221] ACPI: Power Button [PWRB]
>[    0.368257] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input2
>[    0.368299] ACPI: Sleep Button [SLPB]
>[    0.368334] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
>[    0.368374] ACPI: Power Button [PWRF]
>[    0.368432] [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS
>[    0.368474] ACPI: Video Device [GFX0] (multi-head: yes  rom: yes  post: no)
>[    0.369601] acpi device:02: registered as cooling_device0
>[    0.369662] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input4
>[    0.370183] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>[    0.370556] Non-volatile memory driver v1.3
>[    0.370622] [drm] Initialized drm 1.1.0 20060810
>[    0.370683] [drm:nouveau_display_options] Loading Nouveau with parameters:
>[    0.370684] [drm:nouveau_display_options] ... tv_disable   : 0
>[    0.370685] [drm:nouveau_display_options] ... ignorelid    : 0
>[    0.370686] [drm:nouveau_display_options] ... duallink     : 1
>[    0.370686] [drm:nouveau_display_options] ... nofbaccel    : 0
>[    0.370687] [drm:nouveau_display_options] ... config       : (null)
>[    0.370688] [drm:nouveau_display_options] ... debug        : VBIOS=trace,I2C=debug,DISP=debug,DRM=debug
>[    0.370688] [drm:nouveau_display_options] ... noaccel      : 0
>[    0.370689] [drm:nouveau_display_options] ... modeset      : -1
>[    0.370690] [drm:nouveau_display_options] ... runpm        : -1
>[    0.370690] [drm:nouveau_display_options] ... vram_pushbuf : 0
>[    0.370691] [drm:nouveau_display_options] ... pstate       : 0
>[    0.370705] ACPI Warning: \_SB_.PCI0.P0P2.GFX0._DSM: Argument #4 type mismatch - Found [Buffer], ACPI requires [Package] (20150204/nsarguments-95)
>[    0.370807] ACPI: \_SB_.PCI0.P0P2.GFX0: failed to evaluate _DSM
>[    0.370846] checking generic (80020000 1c20000) vs hw (80000000 10000000)
>[    0.370847] fb: switching to nouveaufb from EFI VGA
>[    0.370877] Console: switching to colour dummy device 80x25
>[    0.371146] nouveau  [  DEVICE][0000:01:00.0] BOOT0  : 0x0e7290a2
>[    0.371149] nouveau  [  DEVICE][0000:01:00.0] Chipset: GK107 (NVE7)
>[    0.371152] nouveau  [  DEVICE][0000:01:00.0] Family : NVE0
>[    0.371165] nouveau D[   VBIOS][0000:01:00.0] trying PRAMIN...
>[    0.371303] nouveau D[   VBIOS][0000:01:00.0] 00000000: type 00, 64000 bytes
>[    0.390463] nouveau D[   VBIOS][0000:01:00.0] 0000fa00: type e0, 25088 bytes
>[    0.398013] nouveau D[   VBIOS][0000:01:00.0] 00015c00: type 70, 2560 bytes
>[    0.398014] nouveau D[   VBIOS][0000:01:00.0] scored 12
>[    0.398015] nouveau D[   VBIOS][0000:01:00.0] trying PROM...
>[    0.398028] nouveau D[   VBIOS][0000:01:00.0] 00000000: ROM signature (ffff) unknown
>[    0.398029] nouveau D[   VBIOS][0000:01:00.0] image 0 invalid
>[    0.398032] nouveau D[   VBIOS][0000:01:00.0] scored 0
>[    0.398033] nouveau D[   VBIOS][0000:01:00.0] trying ACPI...
>[    0.398110] nouveau D[   VBIOS][0000:01:00.0] 00000000: type 00, 64000 bytes
>[    0.398209] nouveau D[   VBIOS][0000:01:00.0] 00000000: checksum failed
>[    0.398211] nouveau D[   VBIOS][0000:01:00.0] 0000fa00: ROM signature (6d33) unknown
>[    0.398212] nouveau D[   VBIOS][0000:01:00.0] image 1 invalid
>[    0.398213] nouveau D[   VBIOS][0000:01:00.0] scored 2
>[    0.398214] nouveau  [   VBIOS][0000:01:00.0] using image from PRAMIN
>[    0.398298] nouveau  [   VBIOS][0000:01:00.0] BIT signature found
>[    0.398301] nouveau  [   VBIOS][0000:01:00.0] version 80.07.bf.00.02
>[    0.398304] nouveau T[   VBIOS][0000:01:00.0] created
>[    0.398507] nouveau T[   VBIOS][0000:01:00.0] use(+1) == 1
>[    0.398509] nouveau T[   VBIOS][0000:01:00.0] initialising...
>[    0.398510] nouveau T[   VBIOS][0000:01:00.0] resetting...
>[    0.398511] nouveau D[   VBIOS][0000:01:00.0] reset
>[    0.398512] nouveau T[   VBIOS][0000:01:00.0] initialised
>[    0.398536] nouveau T[   VBIOS][0000:01:00.0] 0x8d16[ ]: RESERVED 0x8c	
>[    0.398538] nouveau T[   VBIOS][0000:01:00.0] 0x8d17[ ]: ZM_REG	R[0x000200] = 0x00002020
>[    0.398539] nouveau T[   VBIOS][0000:01:00.0] 0x8d20[ ]: REPEAT	0x14
>[    0.398541] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398542] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398543] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x13
>[    0.398545] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398545] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398546] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x12
>[    0.398548] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398548] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398549] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x11
>[    0.398550] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398551] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398552] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x10
>[    0.398553] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398554] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398555] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0f
>[    0.398556] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398557] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398558] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0e
>[    0.398559] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398560] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398561] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0d
>[    0.398562] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398563] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398564] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0c
>[    0.398565] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398566] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398567] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0b
>[    0.398568] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398569] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398570] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0a
>[    0.398571] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398572] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398573] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x09
>[    0.398574] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398575] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398576] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x08
>[    0.398577] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398578] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398579] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x07
>[    0.398580] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398581] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398582] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>[    0.398583] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398584] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398585] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.398586] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398587] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398587] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.398589] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398589] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398590] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.398591] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398592] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398593] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.398594] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398595] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398596] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398597] nouveau T[   VBIOS][0000:01:00.0] 0x8d22[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[    0.398598] nouveau T[   VBIOS][0000:01:00.0] 0x8d2f[ ]: END_REPEAT
>[    0.398599] nouveau T[   VBIOS][0000:01:00.0] 0x8d30[ ]: ZM_REG	R[0x000200] = 0x40012125
>[    0.398601] nouveau T[   VBIOS][0000:01:00.0] 0x8d39[ ]: ZM_REG	R[0x1224c0] = 0x00000000
>[    0.398602] nouveau T[   VBIOS][0000:01:00.0] 0x8d42[ ]: ZM_REG	R[0x122640] = 0x00000000
>[    0.398603] nouveau T[   VBIOS][0000:01:00.0] 0x8d4b[ ]: NV_REG	R[0x022400] &= 0xfffff7ff |= 0x00000800
>[    0.398604] nouveau T[   VBIOS][0000:01:00.0] 0x8d58[ ]: CONDITION	0x0d
>[    0.398606] nouveau T[   VBIOS][0000:01:00.0] 0x8d5a[ ]: 	[0x0d] (R[0x02240c] & 0x00000001) == 0x00000000
>[    0.398607] nouveau T[   VBIOS][0000:01:00.0] 0x8d5a[ ]: SUB_DIRECT	0xf820
>[    0.398608] nouveau T[   VBIOS][0000:01:00.0] 0x8d5d[ ]: NV_REG	R[0x0225dc] &= 0xffffffff |= 0x00000000
>[    0.398609] nouveau T[   VBIOS][0000:01:00.0] 0x8d6a[ ]: CONDITION	0x18
>[    0.398611] nouveau T[   VBIOS][0000:01:00.0] 0x8d6c[ ]: 	[0x18] (R[0x022508] & 0xffffffff) == 0x00000000
>[    0.398612] nouveau T[   VBIOS][0000:01:00.0] 0x8d6c[ ]: ZM_REG	R[0x022588] = 0x00000000
>[    0.398613] nouveau T[   VBIOS][0000:01:00.0] 0x8d75[ ]: RESUME
>[    0.398614] nouveau T[   VBIOS][0000:01:00.0] 0x8d76[ ]: SUB_DIRECT	0x8b01
>[    0.398615] nouveau T[   VBIOS][0000:01:00.0] 0x8d79[ ]: RESERVED 0x8d	
>[    0.398616] nouveau T[   VBIOS][0000:01:00.0] 0x8d7a[ ]: NV_REG	R[0x08d11c] &= 0xfffff0c0 |= 0x0000000c
>[    0.398617] nouveau T[   VBIOS][0000:01:00.0] 0x8d87[ ]: NV_REG	R[0x08d12c] &= 0xfffff0c0 |= 0x00000014
>[    0.398619] nouveau T[   VBIOS][0000:01:00.0] 0x8d94[ ]: NV_REG	R[0x08d128] &= 0xffffffe0 |= 0x00000000
>[    0.398620] nouveau T[   VBIOS][0000:01:00.0] 0x8da1[ ]: NV_REG	R[0x08d138] &= 0xffe0ffe0 |= 0x000a000a
>[    0.398621] nouveau T[   VBIOS][0000:01:00.0] 0x8dae[ ]: NV_REG	R[0x08b900] &= 0xfc00ffff |= 0x03ff0000
>[    0.398622] nouveau T[   VBIOS][0000:01:00.0] 0x8dbb[ ]: REPEAT	0x02
>[    0.398623] nouveau T[   VBIOS][0000:01:00.0] 0x8dbd[ ]: CONDITION	0x22
>[    0.398624] nouveau T[   VBIOS][0000:01:00.0] 0x8dbf[ ]: 	[0x22] (R[0x08c040] & 0x000c0000) == 0x00080000
>[    0.398625] nouveau T[   VBIOS][0000:01:00.0] 0x8dbf[ ]: NOT
>[    0.398627] nouveau T[   VBIOS][0000:01:00.0] 0x8dc0[ ]: INIT_XLAT	R[0x08c040] &= 0xff83ffff |= (X00((R[0x088088] >> 0x14) & 0x0f) << 0x12)
>[    0.398629] nouveau T[   VBIOS][0000:01:00.0] 0x8dd1[ ]: RESUME
>[    0.398629] nouveau T[   VBIOS][0000:01:00.0] 0x8dd2[ ]: END_REPEAT
>[    0.398630] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398631] nouveau T[   VBIOS][0000:01:00.0] 0x8dbd[ ]: CONDITION	0x22
>[    0.398633] nouveau T[   VBIOS][0000:01:00.0] 0x8dbf[ ]: 	[0x22] (R[0x08c040] & 0x000c0000) == 0x00080000
>[    0.398634] nouveau T[   VBIOS][0000:01:00.0] 0x8dbf[ ]: NOT
>[    0.398635] nouveau T[   VBIOS][0000:01:00.0] 0x8dc0[ ]: INIT_XLAT	R[0x08c040] &= 0xff83ffff |= (X00((R[0x088088] >> 0x14) & 0x0f) << 0x12)
>[    0.398636] nouveau T[   VBIOS][0000:01:00.0] 0x8dd1[ ]: RESUME
>[    0.398637] nouveau T[   VBIOS][0000:01:00.0] 0x8dd2[ ]: END_REPEAT
>[    0.398638] nouveau T[   VBIOS][0000:01:00.0] 0x8dd3[ ]: REPEAT	0x02
>[    0.398639] nouveau T[   VBIOS][0000:01:00.0] 0x8dd5[ ]: CONDITION	0x21
>[    0.398640] nouveau T[   VBIOS][0000:01:00.0] 0x8dd7[ ]: 	[0x21] (R[0x088088] & 0x000f0000) == 0x00010000
>[    0.398641] nouveau T[   VBIOS][0000:01:00.0] 0x8dd7[ ]: NOT
>[    0.398642] nouveau T[   VBIOS][0000:01:00.0] 0x8dd8[ ]: NV_REG	R[0x08c040] &= 0xfffffff0 |= 0x00000001
>[    0.398643] nouveau T[   VBIOS][0000:01:00.0] 0x8de5[ ]: CONDITION_TIME	0x23 0xff
>[    0.398644] nouveau T[   VBIOS][0000:01:00.0] 0x8de8[ ]: RESUME
>[    0.398645] nouveau T[   VBIOS][0000:01:00.0] 0x8de9[ ]: END_REPEAT
>[    0.398646] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398647] nouveau T[   VBIOS][0000:01:00.0] 0x8dd5[ ]: CONDITION	0x21
>[    0.398648] nouveau T[   VBIOS][0000:01:00.0] 0x8dd7[ ]: 	[0x21] (R[0x088088] & 0x000f0000) == 0x00010000
>[    0.398649] nouveau T[   VBIOS][0000:01:00.0] 0x8dd7[ ]: NOT
>[    0.398650] nouveau T[   VBIOS][0000:01:00.0] 0x8dd8[ ]: NV_REG	R[0x08c040] &= 0xfffffff0 |= 0x00000001
>[    0.398651] nouveau T[   VBIOS][0000:01:00.0] 0x8de5[ ]: CONDITION_TIME	0x23 0xff
>[    0.398652] nouveau T[   VBIOS][0000:01:00.0] 0x8de8[ ]: RESUME
>[    0.398653] nouveau T[   VBIOS][0000:01:00.0] 0x8de9[ ]: END_REPEAT
>[    0.398654] nouveau T[   VBIOS][0000:01:00.0] 0x8dea[ ]: NV_REG	R[0x08c040] &= 0xfffffff0 |= 0x00000002
>[    0.398655] nouveau T[   VBIOS][0000:01:00.0] 0x8df7[ ]: CONDITION_TIME	0x23 0xff
>[    0.398656] nouveau T[   VBIOS][0000:01:00.0] 0x8dfa[ ]: RESUME
>[    0.398657] nouveau T[   VBIOS][0000:01:00.0] 0x8dfb[ ]: ZM_REG	R[0x1370a8] = 0x00000020
>[    0.398658] nouveau T[   VBIOS][0000:01:00.0] 0x8e04[ ]: CONDITION	0x20
>[    0.398659] nouveau T[   VBIOS][0000:01:00.0] 0x8e06[ ]: 	[0x20] (R[0x000a00] & 0x000ff000) == 0x000a1000
>[    0.398660] nouveau T[   VBIOS][0000:01:00.0] 0x8e06[ ]: SUB_DIRECT	0x94c0
>[    0.398661] nouveau T[   VBIOS][0000:01:00.0] 0x8e09[ ]: RESUME
>[    0.398662] nouveau T[   VBIOS][0000:01:00.0] 0x8e0a[ ]: NV_REG	R[0x13718c] &= 0xfffcfffc |= 0x00030000
>[    0.398663] nouveau T[   VBIOS][0000:01:00.0] 0x8e17[ ]: CONDITION	0x1b
>[    0.398665] nouveau T[   VBIOS][0000:01:00.0] 0x8e19[ ]: 	[0x1b] (R[0x0214c0] & 0x00000007) == 0x00000000
>[    0.398666] nouveau T[   VBIOS][0000:01:00.0] 0x8e19[ ]: ZM_REG	R[0x0204cc] = 0x0000005f
>[    0.398667] nouveau T[   VBIOS][0000:01:00.0] 0x8e22[ ]: NV_REG	R[0x020124] &= 0xfffffbff |= 0x00000000
>[    0.398668] nouveau T[   VBIOS][0000:01:00.0] 0x8e2f[ ]: RESUME
>[    0.398669] nouveau T[   VBIOS][0000:01:00.0] 0x8e30[ ]: CONDITION	0x1a
>[    0.398670] nouveau T[   VBIOS][0000:01:00.0] 0x8e32[ ]: 	[0x1a] (R[0x021288] & 0x000000ff) == 0x00000000
>[    0.398671] nouveau T[   VBIOS][0000:01:00.0] 0x8e32[ ]: ZM_REG	R[0x0204c8] = 0x00000095
>[    0.398672] nouveau T[   VBIOS][0000:01:00.0] 0x8e3b[ ]: NV_REG	R[0x020124] &= 0xfffffdff |= 0x00000000
>[    0.398673] nouveau T[   VBIOS][0000:01:00.0] 0x8e48[ ]: RESUME
>[    0.398674] nouveau T[   VBIOS][0000:01:00.0] 0x8e49[ ]: CONDITION	0x19
>[    0.398675] nouveau T[   VBIOS][0000:01:00.0] 0x8e4b[ ]: 	[0x19] (R[0x021290] & 0x00000001) == 0x00000000
>[    0.398676] nouveau T[   VBIOS][0000:01:00.0] 0x8e4b[ ]: ZM_REG	R[0x020010] = 0x05d903a5
>[    0.398677] nouveau T[   VBIOS][0000:01:00.0] 0x8e54[ ]: ZM_REG	R[0x02000c] = 0x00009c43
>[    0.398679] nouveau T[   VBIOS][0000:01:00.0] 0x8e5d[ ]: TIME	0x2710
>[    0.398680] nouveau T[   VBIOS][0000:01:00.0] 0x8e60[ ]: RESUME
>[    0.398681] nouveau T[   VBIOS][0000:01:00.0] 0x8e61[ ]: ZM_REG	R[0x0200f0] = 0x01750000
>[    0.398682] nouveau T[   VBIOS][0000:01:00.0] 0x8e6a[ ]: ZM_REG	R[0x020008] = 0x00000000
>[    0.398683] nouveau T[   VBIOS][0000:01:00.0] 0x8e73[ ]: ZM_REG_SEQUENCE	0x03
>[    0.398684] nouveau T[   VBIOS][0000:01:00.0] 0x8e79[ ]: 		R[0x020480] = 0x0000006d
>[    0.398685] nouveau T[   VBIOS][0000:01:00.0] 0x8e7d[ ]: 		R[0x020484] = 0x00000003
>[    0.398686] nouveau T[   VBIOS][0000:01:00.0] 0x8e81[ ]: 		R[0x020488] = 0x00000000
>[    0.398687] nouveau T[   VBIOS][0000:01:00.0] 0x8e85[ ]: ZM_MASK_ADD	R[0x020480] &= 0xffffff00 += 0x000000fb
>[    0.398689] nouveau T[   VBIOS][0000:01:00.0] 0x8e92[ ]: ZM_REG	R[0x0204c0] = 0x0000006b
>[    0.398690] nouveau T[   VBIOS][0000:01:00.0] 0x8e9b[ ]: ZM_MASK_ADD	R[0x0204c0] &= 0xffffff00 += 0x000000fb
>[    0.398691] nouveau T[   VBIOS][0000:01:00.0] 0x8ea8[ ]: ZM_REG	R[0x0204d8] = 0x00000068
>[    0.398692] nouveau T[   VBIOS][0000:01:00.0] 0x8eb1[ ]: ZM_MASK_ADD	R[0x0204d8] &= 0xffffff00 += 0x000000fb
>[    0.398693] nouveau T[   VBIOS][0000:01:00.0] 0x8ebe[ ]: ZM_REG	R[0x0204e0] = 0x00000065
>[    0.398694] nouveau T[   VBIOS][0000:01:00.0] 0x8ec7[ ]: ZM_MASK_ADD	R[0x0204e0] &= 0xffffff00 += 0x000000fb
>[    0.398695] nouveau T[   VBIOS][0000:01:00.0] 0x8ed4[ ]: ZM_REG	R[0x0204e8] = 0x00000061
>[    0.398696] nouveau T[   VBIOS][0000:01:00.0] 0x8edd[ ]: ZM_MASK_ADD	R[0x0204e8] &= 0xffffff00 += 0x00000000
>[    0.398697] nouveau T[   VBIOS][0000:01:00.0] 0x8eea[ ]: ZM_REG	R[0x02041c] = 0x00000069
>[    0.398699] nouveau T[   VBIOS][0000:01:00.0] 0x8ef3[ ]: ZM_MASK_ADD	R[0x02041c] &= 0xffffff00 += 0x000000fb
>[    0.398700] nouveau T[   VBIOS][0000:01:00.0] 0x8f00[ ]: ZM_REG_SEQUENCE	0x02
>[    0.398701] nouveau T[   VBIOS][0000:01:00.0] 0x8f06[ ]: 		R[0x02040c] = 0x00000011
>[    0.398702] nouveau T[   VBIOS][0000:01:00.0] 0x8f0a[ ]: 		R[0x020410] = 0x00000005
>[    0.398703] nouveau T[   VBIOS][0000:01:00.0] 0x8f0e[ ]: NV_REG	R[0x00d790] &= 0xfffffeff |= 0x00000100
>[    0.398704] nouveau T[   VBIOS][0000:01:00.0] 0x8f1b[ ]: ZM_REG_SEQUENCE	0x06
>[    0.398705] nouveau T[   VBIOS][0000:01:00.0] 0x8f21[ ]: 		R[0x02010c] = 0x00000016
>[    0.398706] nouveau T[   VBIOS][0000:01:00.0] 0x8f25[ ]: 		R[0x020110] = 0x00000000
>[    0.398708] nouveau T[   VBIOS][0000:01:00.0] 0x8f29[ ]: 		R[0x020114] = 0x00000000
>[    0.398709] nouveau T[   VBIOS][0000:01:00.0] 0x8f2d[ ]: 		R[0x020118] = 0x00000000
>[    0.398710] nouveau T[   VBIOS][0000:01:00.0] 0x8f31[ ]: 		R[0x02011c] = 0x09875430
>[    0.398723] nouveau T[   VBIOS][0000:01:00.0] 0x8f35[ ]: 		R[0x020120] = 0x0000a261
>[    0.398724] nouveau T[   VBIOS][0000:01:00.0] 0x8f39[ ]: ZM_REG_SEQUENCE	0x02
>[    0.398726] nouveau T[   VBIOS][0000:01:00.0] 0x8f3f[ ]: 		R[0x020074] = 0x00666066
>[    0.398727] nouveau T[   VBIOS][0000:01:00.0] 0x8f43[ ]: 		R[0x020078] = 0x01100000
>[    0.398729] nouveau T[   VBIOS][0000:01:00.0] 0x8f47[ ]: ZM_REG	R[0x020094] = 0x00020000
>[    0.398731] nouveau T[   VBIOS][0000:01:00.0] 0x8f50[ ]: ZM_REG	R[0x020138] = 0x00003013
>[    0.398732] nouveau T[   VBIOS][0000:01:00.0] 0x8f59[ ]: ZM_REG_SEQUENCE	0x04
>[    0.398733] nouveau T[   VBIOS][0000:01:00.0] 0x8f5f[ ]: 		R[0x020160] = 0x00020000
>[    0.398734] nouveau T[   VBIOS][0000:01:00.0] 0x8f63[ ]: 		R[0x020164] = 0x00000082
>[    0.398735] nouveau T[   VBIOS][0000:01:00.0] 0x8f67[ ]: 		R[0x020168] = 0x00000080
>[    0.398736] nouveau T[   VBIOS][0000:01:00.0] 0x8f6b[ ]: 		R[0x02016c] = 0x00000080
>[    0.398737] nouveau T[   VBIOS][0000:01:00.0] 0x8f6f[ ]: ZM_REG_SEQUENCE	0x02
>[    0.398738] nouveau T[   VBIOS][0000:01:00.0] 0x8f75[ ]: 		R[0x0201a0] = 0x00004040
>[    0.398739] nouveau T[   VBIOS][0000:01:00.0] 0x8f79[ ]: 		R[0x0201a4] = 0x00004040
>[    0.398740] nouveau T[   VBIOS][0000:01:00.0] 0x8f7d[ ]: ZM_REG	R[0x0203c0] = 0x00000000
>[    0.398741] nouveau T[   VBIOS][0000:01:00.0] 0x8f86[ ]: ZM_REG_SEQUENCE	0x05
>[    0.398742] nouveau T[   VBIOS][0000:01:00.0] 0x8f8c[ ]: 		R[0x0203cc] = 0x00010000
>[    0.398743] nouveau T[   VBIOS][0000:01:00.0] 0x8f90[ ]: 		R[0x0203d0] = 0x00010000
>[    0.398744] nouveau T[   VBIOS][0000:01:00.0] 0x8f94[ ]: 		R[0x0203d4] = 0x00000000
>[    0.398745] nouveau T[   VBIOS][0000:01:00.0] 0x8f98[ ]: 		R[0x0203d8] = 0x00000000
>[    0.398746] nouveau T[   VBIOS][0000:01:00.0] 0x8f9c[ ]: 		R[0x0203dc] = 0x00000000
>[    0.398747] nouveau T[   VBIOS][0000:01:00.0] 0x8fa0[ ]: ZM_REG	R[0x020130] = 0x8107060c
>[    0.398748] nouveau T[   VBIOS][0000:01:00.0] 0x8fa9[ ]: ZM_REG	R[0x020144] = 0x00010000
>[    0.398749] nouveau T[   VBIOS][0000:01:00.0] 0x8fb2[ ]: ZM_REG	R[0x020424] = 0x00000002
>[    0.398750] nouveau T[   VBIOS][0000:01:00.0] 0x8fbb[ ]: SUB_DIRECT	0x695d
>[    0.398751] nouveau T[   VBIOS][0000:01:00.0] 0x8fbe[ ]: SUB_DIRECT	0x8ba2
>[    0.398752] nouveau T[   VBIOS][0000:01:00.0] 0x8fc1[ ]: NV_REG	R[0x00e114] &= 0xff000000 |= 0x0000021c
>[    0.398754] nouveau T[   VBIOS][0000:01:00.0] 0x8fce[ ]: NV_REG	R[0x00e118] &= 0x7f000000 |= 0x8000021c
>[    0.398755] nouveau T[   VBIOS][0000:01:00.0] 0x8fdb[ ]: NV_REG	R[0x00e11c] &= 0xffffffff |= 0x00000000
>[    0.398756] nouveau T[   VBIOS][0000:01:00.0] 0x8fe8[ ]: NV_REG	R[0x00e120] &= 0xfcffffff |= 0x03000000
>[    0.398757] nouveau T[   VBIOS][0000:01:00.0] 0x8ff5[ ]: NV_REG	R[0x020340] &= 0xffffffff |= 0x00000000
>[    0.398758] nouveau T[   VBIOS][0000:01:00.0] 0x9002[ ]: NV_REG	R[0x020344] &= 0xffffffff |= 0x00000000
>[    0.398759] nouveau T[   VBIOS][0000:01:00.0] 0x900f[ ]: NV_REG	R[0x00d630] &= 0xfffb7fff |= 0x00048000
>[    0.398760] nouveau T[   VBIOS][0000:01:00.0] 0x901c[ ]: NV_REG	R[0x00d634] &= 0xfffb7fff |= 0x00048000
>[    0.398761] nouveau T[   VBIOS][0000:01:00.0] 0x9029[ ]: NV_REG	R[0x00d740] &= 0xffffffff |= 0x00000000
>[    0.398762] nouveau T[   VBIOS][0000:01:00.0] 0x9036[ ]: NV_REG	R[0x00d744] &= 0xffffffff |= 0x00000000
>[    0.398764] nouveau T[   VBIOS][0000:01:00.0] 0x9043[ ]: NV_REG	R[0x00d748] &= 0xffffffff |= 0x00000000
>[    0.398765] nouveau T[   VBIOS][0000:01:00.0] 0x9050[ ]: NV_REG	R[0x00d74c] &= 0xffffffff |= 0x00000000
>[    0.398766] nouveau T[   VBIOS][0000:01:00.0] 0x905d[ ]: NV_REG	R[0x00d794] &= 0xfffffeff |= 0x00000100
>[    0.398767] nouveau T[   VBIOS][0000:01:00.0] 0x906a[ ]: NV_REG	R[0x00d798] &= 0xfffffeff |= 0x00000100
>[    0.398768] nouveau T[   VBIOS][0000:01:00.0] 0x9077[ ]: GPIO
>[    0.398769] nouveau T[   VBIOS][0000:01:00.0] 0x9078[ ]: ZM_REG_SEQUENCE	0x02
>[    0.398770] nouveau T[   VBIOS][0000:01:00.0] 0x907e[ ]: 		R[0x020000] = 0x80000000
>[    0.398771] nouveau T[   VBIOS][0000:01:00.0] 0x9082[ ]: 		R[0x020004] = 0x001100eb
>[    0.398772] nouveau T[   VBIOS][0000:01:00.0] 0x9086[ ]: ZM_REG_SEQUENCE	0x02
>[    0.398773] nouveau T[   VBIOS][0000:01:00.0] 0x908c[ ]: 		R[0x0202a0] = 0x00000000
>[    0.398774] nouveau T[   VBIOS][0000:01:00.0] 0x9090[ ]: 		R[0x0202a4] = 0x00000080
>[    0.398775] nouveau T[   VBIOS][0000:01:00.0] 0x9094[ ]: SUB_DIRECT	0x8ceb
>[    0.398776] nouveau T[   VBIOS][0000:01:00.0] 0x9097[ ]: NV_REG	R[0x101000] &= 0xffffffff |= 0x80000000
>[    0.398777] nouveau T[   VBIOS][0000:01:00.0] 0x90a4[ ]: NV_REG	R[0x10100c] &= 0xffffffff |= 0x80000000
>[    0.398779] nouveau T[   VBIOS][0000:01:00.0] 0x90b1[ ]: NV_REG	R[0x02241c] &= 0xffffffff |= 0x00000000
>[    0.398780] nouveau T[   VBIOS][0000:01:00.0] 0x90be[ ]: NV_REG	R[0x08c384] &= 0xffffffee |= 0x00000011
>[    0.398781] nouveau T[   VBIOS][0000:01:00.0] 0x90cb[ ]: NV_REG	R[0x088150] &= 0xfffffe7f |= 0x00000000
>[    0.398782] nouveau T[   VBIOS][0000:01:00.0] 0x90d8[ ]: NV_REG	R[0x08c100] &= 0x000000ff |= 0x00303000
>[    0.398783] nouveau T[   VBIOS][0000:01:00.0] 0x90e5[ ]: NV_REG	R[0x08b470] &= 0x00000000 |= 0x00000500
>[    0.398784] nouveau T[   VBIOS][0000:01:00.0] 0x90f2[ ]: NV_REG	R[0x08b474] &= 0x00000000 |= 0x00000500
>[    0.398785] nouveau T[   VBIOS][0000:01:00.0] 0x90ff[ ]: NV_REG	R[0x08b478] &= 0x00000000 |= 0x00000500
>[    0.398786] nouveau T[   VBIOS][0000:01:00.0] 0x910c[ ]: NV_REG	R[0x08d20c] &= 0xffffff00 |= 0x00000040
>[    0.398788] nouveau T[   VBIOS][0000:01:00.0] 0x9119[ ]: NV_REG	R[0x08d13c] &= 0xfffff000 |= 0x00000d18
>[    0.398789] nouveau T[   VBIOS][0000:01:00.0] 0x9126[ ]: NV_REG	R[0x08d104] &= 0xfffffffd |= 0x00000000
>[    0.398790] nouveau T[   VBIOS][0000:01:00.0] 0x9133[ ]: NV_REG	R[0x08d110] &= 0xffdfffff |= 0x00000000
>[    0.398791] nouveau T[   VBIOS][0000:01:00.0] 0x9140[ ]: SUB_DIRECT	0x8b0a
>[    0.398792] nouveau T[   VBIOS][0000:01:00.0] 0x9143[ ]: CONDITION	0x0c
>[    0.398793] nouveau T[   VBIOS][0000:01:00.0] 0x9145[ ]: 	[0x0c] (R[0x120064] & 0x00000007) == 0x00000005
>[    0.398794] nouveau T[   VBIOS][0000:01:00.0] 0x9145[ ]: NOT
>[    0.398795] nouveau T[   VBIOS][0000:01:00.0] 0x9146[ ]: SUB_DIRECT	0x9485
>[    0.398796] nouveau T[   VBIOS][0000:01:00.0] 0x9149[ ]: RESUME
>[    0.398797] nouveau T[   VBIOS][0000:01:00.0] 0x914a[ ]: CONDITION	0x20
>[    0.398798] nouveau T[   VBIOS][0000:01:00.0] 0x914c[ ]: 	[0x20] (R[0x000a00] & 0x000ff000) == 0x000a1000
>[    0.398799] nouveau T[   VBIOS][0000:01:00.0] 0x914c[ ]: SUB_DIRECT	0x9513
>[    0.398800] nouveau T[   VBIOS][0000:01:00.0] 0x914f[ ]: RESUME
>[    0.398801] nouveau T[   VBIOS][0000:01:00.0] 0x9150[ ]: CONDITION_TIME	0x07 0xff
>[    0.398802] nouveau T[   VBIOS][0000:01:00.0] 0x9153[ ]: RESUME
>[    0.398803] nouveau T[   VBIOS][0000:01:00.0] 0x9154[ ]: CONDITION_TIME	0x09 0xff
>[    0.398804] nouveau T[   VBIOS][0000:01:00.0] 0x9157[ ]: RESUME
>[    0.398805] nouveau T[   VBIOS][0000:01:00.0] 0x9158[ ]: NV_REG	R[0x00e9f8] &= 0xfffffffe |= 0x00000001
>[    0.398806] nouveau T[   VBIOS][0000:01:00.0] 0x9165[ ]: NV_REG	R[0x00e9f8] &= 0xfffffffd |= 0x00000002
>[    0.398807] nouveau T[   VBIOS][0000:01:00.0] 0x9172[ ]: ZM_REG_SEQUENCE	0x03
>[    0.398808] nouveau T[   VBIOS][0000:01:00.0] 0x9178[ ]: 		R[0x137250] = 0x81200000
>[    0.398809] nouveau T[   VBIOS][0000:01:00.0] 0x917c[ ]: 		R[0x137254] = 0x81200000
>[    0.398810] nouveau T[   VBIOS][0000:01:00.0] 0x9180[ ]: 		R[0x137258] = 0x81200000
>[    0.398811] nouveau T[   VBIOS][0000:01:00.0] 0x9184[ ]: ZM_REG_SEQUENCE	0x03
>[    0.398812] nouveau T[   VBIOS][0000:01:00.0] 0x918a[ ]: 		R[0x137140] = 0x81200202
>[    0.398813] nouveau T[   VBIOS][0000:01:00.0] 0x918e[ ]: 		R[0x137144] = 0x81200202
>[    0.398814] nouveau T[   VBIOS][0000:01:00.0] 0x9192[ ]: 		R[0x137148] = 0x81200202
>[    0.398824] nouveau T[   VBIOS][0000:01:00.0] 0x9196[ ]: ZM_REG	R[0x1371ec] = 0x81200000
>[    0.398825] nouveau T[   VBIOS][0000:01:00.0] 0x919f[ ]: ZM_REG	R[0x13715c] = 0x81200202
>[    0.398826] nouveau T[   VBIOS][0000:01:00.0] 0x91a8[ ]: ZM_REG	R[0x137330] = 0x81200606
>[    0.398826] nouveau T[   VBIOS][0000:01:00.0] 0x91b1[ ]: ZM_REG_SEQUENCE	0x02
>[    0.398827] nouveau T[   VBIOS][0000:01:00.0] 0x91b7[ ]: 		R[0x1372c8] = 0x81200000
>[    0.398828] nouveau T[   VBIOS][0000:01:00.0] 0x91bb[ ]: 		R[0x1372cc] = 0x81200000
>[    0.398829] nouveau T[   VBIOS][0000:01:00.0] 0x91bf[ ]: SUB_DIRECT	0x8b1d
>[    0.398830] nouveau T[   VBIOS][0000:01:00.0] 0x91c2[ ]: CONDITION	0x20
>[    0.398831] nouveau T[   VBIOS][0000:01:00.0] 0x91c4[ ]: 	[0x20] (R[0x000a00] & 0x000ff000) == 0x000a1000
>[    0.398832] nouveau T[   VBIOS][0000:01:00.0] 0x91c4[ ]: ZM_REG	R[0x00e9e4] = 0x81201c1c
>[    0.398833] nouveau T[   VBIOS][0000:01:00.0] 0x91cd[ ]: ZM_REG	R[0x00e9f0] = 0x80000d0d
>[    0.398833] nouveau T[   VBIOS][0000:01:00.0] 0x91d6[ ]: NOT
>[    0.398834] nouveau T[   VBIOS][0000:01:00.0] 0x91d7[ ]: ZM_REG	R[0x00e9e4] = 0x81200606
>[    0.398835] nouveau T[   VBIOS][0000:01:00.0] 0x91e0[ ]: ZM_REG	R[0x00e9f0] = 0x80000000
>[    0.398836] nouveau T[   VBIOS][0000:01:00.0] 0x91e9[ ]: RESUME
>[    0.398837] nouveau T[   VBIOS][0000:01:00.0] 0x91ea[ ]: ZM_REG	R[0x1371d0] = 0x81200202
>[    0.398838] nouveau T[   VBIOS][0000:01:00.0] 0x91f3[ ]: ZM_REG	R[0x1371d4] = 0x81200202
>[    0.398839] nouveau T[   VBIOS][0000:01:00.0] 0x91fc[ ]: ZM_REG	R[0x1371d8] = 0x81200202
>[    0.398839] nouveau T[   VBIOS][0000:01:00.0] 0x9205[ ]: SUB_DIRECT	0x8b4a
>[    0.398840] nouveau T[   VBIOS][0000:01:00.0] 0x9208[ ]: ZM_REG	R[0x137310] = 0x81200606
>[    0.398841] nouveau T[   VBIOS][0000:01:00.0] 0x9211[ ]: SUB_DIRECT	0x8b6f
>[    0.398842] nouveau T[   VBIOS][0000:01:00.0] 0x9214[ ]: ZM_REG	R[0x13727c] = 0x81201c1c
>[    0.398843] nouveau T[   VBIOS][0000:01:00.0] 0x921d[ ]: ZM_REG	R[0x137280] = 0x81200808
>[    0.398844] nouveau T[   VBIOS][0000:01:00.0] 0x9226[ ]: ZM_REG	R[0x13726c] = 0x81200202
>[    0.398845] nouveau T[   VBIOS][0000:01:00.0] 0x922f[ ]: ZM_REG	R[0x137270] = 0x81200606
>[    0.398845] nouveau T[   VBIOS][0000:01:00.0] 0x9238[ ]: ZM_REG	R[0x137288] = 0x81200606
>[    0.398846] nouveau T[   VBIOS][0000:01:00.0] 0x9241[ ]: ZM_REG	R[0x00e808] = 0x00000010
>[    0.398847] nouveau T[   VBIOS][0000:01:00.0] 0x924a[ ]: ZM_REG	R[0x00e828] = 0x00000010
>[    0.398848] nouveau T[   VBIOS][0000:01:00.0] 0x9253[ ]: NV_REG	R[0x00e800] &= 0xfffffffe |= 0x00000001
>[    0.398849] nouveau T[   VBIOS][0000:01:00.0] 0x9260[ ]: NV_REG	R[0x00e820] &= 0xfffffffe |= 0x00000001
>[    0.398850] nouveau T[   VBIOS][0000:01:00.0] 0x926d[ ]: NV_REG	R[0x00e830] &= 0x80000000 |= 0x001c1c01
>[    0.398851] nouveau T[   VBIOS][0000:01:00.0] 0x927a[ ]: CONDITION_TIME	0x08 0xff
>[    0.398852] nouveau T[   VBIOS][0000:01:00.0] 0x927d[ ]: RESUME
>[    0.398853] nouveau T[   VBIOS][0000:01:00.0] 0x927e[ ]: CONDITION_TIME	0x0a 0xff
>[    0.398853] nouveau T[   VBIOS][0000:01:00.0] 0x9281[ ]: RESUME
>[    0.398854] nouveau T[   VBIOS][0000:01:00.0] 0x9282[ ]: NV_REG	R[0x00e800] &= 0xfffffffb |= 0x00000004
>[    0.398855] nouveau T[   VBIOS][0000:01:00.0] 0x928f[ ]: NV_REG	R[0x00e820] &= 0xfffffffb |= 0x00000004
>[    0.398856] nouveau T[   VBIOS][0000:01:00.0] 0x929c[ ]: NV_REG	R[0x00e9f8] &= 0xfffffffe |= 0x00000000
>[    0.398857] nouveau T[   VBIOS][0000:01:00.0] 0x92a9[ ]: NV_REG	R[0x00e9f8] &= 0xfffffffd |= 0x00000000
>[    0.398858] nouveau T[   VBIOS][0000:01:00.0] 0x92b6[ ]: NV_REG	R[0x00e82c] &= 0xfffffff7 |= 0x00000000
>[    0.398859] nouveau T[   VBIOS][0000:01:00.0] 0x92c3[ ]: NV_REG	R[0x00e830] &= 0x7fffffff |= 0x00000000
>[    0.398860] nouveau T[   VBIOS][0000:01:00.0] 0x92d0[ ]: NV_REG	R[0x00e82c] &= 0xfffffffb |= 0x00000000
>[    0.398861] nouveau T[   VBIOS][0000:01:00.0] 0x92dd[ ]: ZM_REG	R[0x1371c8] = 0x00000002
>[    0.398862] nouveau T[   VBIOS][0000:01:00.0] 0x92e6[ ]: ZM_REG	R[0x1371cc] = 0x00000000
>[    0.398863] nouveau T[   VBIOS][0000:01:00.0] 0x92ef[ ]: ZM_REG	R[0x137160] = 0x00000003
>[    0.398864] nouveau T[   VBIOS][0000:01:00.0] 0x92f8[ ]: ZM_REG	R[0x137164] = 0x00000003
>[    0.398864] nouveau T[   VBIOS][0000:01:00.0] 0x9301[ ]: ZM_REG	R[0x137168] = 0x00000003
>[    0.398865] nouveau T[   VBIOS][0000:01:00.0] 0x930a[ ]: ZM_REG	R[0x137300] = 0x00000103
>[    0.398866] nouveau T[   VBIOS][0000:01:00.0] 0x9313[ ]: CONDITION	0x20
>[    0.398867] nouveau T[   VBIOS][0000:01:00.0] 0x9315[ ]: 	[0x20] (R[0x000a00] & 0x000ff000) == 0x000a1000
>[    0.398868] nouveau T[   VBIOS][0000:01:00.0] 0x9315[ ]: NV_REG	R[0x13718c] &= 0xfffffefc |= 0x00000003
>[    0.398869] nouveau T[   VBIOS][0000:01:00.0] 0x9322[ ]: RESUME
>[    0.398870] nouveau T[   VBIOS][0000:01:00.0] 0x9323[ ]: ZM_REG	R[0x137190] = 0x00000003
>[    0.398871] nouveau T[   VBIOS][0000:01:00.0] 0x932c[ ]: ZM_REG	R[0x10a020] = 0x0004f1a0
>[    0.398872] nouveau T[   VBIOS][0000:01:00.0] 0x9335[ ]: SUB_DIRECT	0x8b79
>[    0.398872] nouveau T[   VBIOS][0000:01:00.0] 0x9338[ ]: CONDITION	0x20
>[    0.398873] nouveau T[   VBIOS][0000:01:00.0] 0x933a[ ]: 	[0x20] (R[0x000a00] & 0x000ff000) == 0x000a1000
>[    0.398874] nouveau T[   VBIOS][0000:01:00.0] 0x933a[ ]: ZM_REG	R[0x00e9a4] = 0x00000003
>[    0.398875] nouveau T[   VBIOS][0000:01:00.0] 0x9343[ ]: ZM_REG	R[0x00e9b0] = 0x00000003
>[    0.398876] nouveau T[   VBIOS][0000:01:00.0] 0x934c[ ]: NOT
>[    0.398877] nouveau T[   VBIOS][0000:01:00.0] 0x934d[ ]: ZM_REG	R[0x00e9a4] = 0x00030000
>[    0.398878] nouveau T[   VBIOS][0000:01:00.0] 0x9356[ ]: ZM_REG	R[0x00e9b0] = 0x04000002
>[    0.398878] nouveau T[   VBIOS][0000:01:00.0] 0x935f[ ]: RESUME
>[    0.398879] nouveau T[   VBIOS][0000:01:00.0] 0x9360[ ]: NV_REG	R[0x13717c] &= 0x00000000 |= 0x00000003
>[    0.398880] nouveau T[   VBIOS][0000:01:00.0] 0x936d[ ]: NV_REG	R[0x137180] &= 0xfffffefc |= 0x00000003
>[    0.398881] nouveau T[   VBIOS][0000:01:00.0] 0x937a[ ]: NV_REG	R[0x137198] &= 0x00000003 |= 0x00000003
>[    0.398882] nouveau T[   VBIOS][0000:01:00.0] 0x9387[ ]: ZM_REG_SEQUENCE	0x03
>[    0.398883] nouveau T[   VBIOS][0000:01:00.0] 0x938d[ ]: 		R[0x137120] = 0x00000003
>[    0.398884] nouveau T[   VBIOS][0000:01:00.0] 0x9391[ ]: 		R[0x137124] = 0x00000003
>[    0.398885] nouveau T[   VBIOS][0000:01:00.0] 0x9395[ ]: 		R[0x137128] = 0x00000003
>[    0.398886] nouveau T[   VBIOS][0000:01:00.0] 0x9399[ ]: ZM_REG	R[0x13713c] = 0x00000003
>[    0.398887] nouveau T[   VBIOS][0000:01:00.0] 0x93a2[ ]: NV_REG	R[0x132880] &= 0xfffffff6 |= 0x00000009
>[    0.398888] nouveau T[   VBIOS][0000:01:00.0] 0x93af[ ]: ZM_REG	R[0x138000] = 0x00000104
>[    0.398889] nouveau T[   VBIOS][0000:01:00.0] 0x93b8[ ]: NV_REG	R[0x137340] &= 0xffffff78 |= 0x00000001
>[    0.398889] nouveau T[   VBIOS][0000:01:00.0] 0x93c5[ ]: SUB_DIRECT	0x8b83
>[    0.398890] nouveau T[   VBIOS][0000:01:00.0] 0x93c8[ ]: CONDITION	0x27
>[    0.398891] nouveau T[   VBIOS][0000:01:00.0] 0x93ca[ ]: 	[0x27] (R[0x00d68c] & 0x00004000) == 0x00000000
>[    0.398892] nouveau T[   VBIOS][0000:01:00.0] 0x93ca[ ]: NV_REG	R[0x001590] &= 0xfffffff7 |= 0x00000000
>[    0.398893] nouveau T[   VBIOS][0000:01:00.0] 0x93d7[ ]: NOT
>[    0.398894] nouveau T[   VBIOS][0000:01:00.0] 0x93d8[ ]: NV_REG	R[0x001590] &= 0xfffffff7 |= 0x00000008
>[    0.398895] nouveau T[   VBIOS][0000:01:00.0] 0x93e5[ ]: SUB_DIRECT	0x9559
>[    0.398896] nouveau T[   VBIOS][0000:01:00.0] 0x93e8[ ]: RESUME
>[    0.398897] nouveau T[   VBIOS][0000:01:00.0] 0x93e9[ ]: NV_REG	R[0x000200] &= 0x1feffff7 |= 0xe0100008
>[    0.398898] nouveau T[   VBIOS][0000:01:00.0] 0x93f6[ ]: COPY_ZM_REG	R[0x17e8d8] = R[0x120074]
>[    0.398899] nouveau T[   VBIOS][0000:01:00.0] 0x93ff[ ]: COPY_ZM_REG	R[0x100800] = R[0x120074]
>[    0.398900] nouveau T[   VBIOS][0000:01:00.0] 0x9408[ ]: ZM_REG	R[0x088610] = 0x00001001
>[    0.398901] nouveau T[   VBIOS][0000:01:00.0] 0x9411[ ]: ZM_REG	R[0x08c2c0] = 0x060001b2
>[    0.398902] nouveau T[   VBIOS][0000:01:00.0] 0x941a[ ]: NV_REG	R[0x17e8d8] &= 0xffffffff |= 0x00000000
>[    0.398902] nouveau T[   VBIOS][0000:01:00.0] 0x9427[ ]: NV_REG	R[0x100800] &= 0xffffffff |= 0x00000000
>[    0.398903] nouveau T[   VBIOS][0000:01:00.0] 0x9434[ ]: ZM_REG	R[0x122400] = 0x0011ce20
>[    0.398904] nouveau T[   VBIOS][0000:01:00.0] 0x943d[ ]: ZM_REG	R[0x122480] = 0xfe003000
>[    0.398905] nouveau T[   VBIOS][0000:01:00.0] 0x9446[ ]: ZM_REG	R[0x122600] = 0x00000800
>[    0.398907] nouveau T[   VBIOS][0000:01:00.0] 0x944f[ ]: COPY_NV_REG	R[0x1373f8] &= 0xfffffffe |= ((R[0x022554] >> 0x00) & 0x00000001 ^ 0x00000001)
>[    0.398908] nouveau T[   VBIOS][0000:01:00.0] 0x9465[ ]: COPY_NV_REG	R[0x1373f8] &= 0xfffffffb |= ((R[0x022554] << 0x01) & 0x00000004 ^ 0x00000004)
>[    0.398909] nouveau T[   VBIOS][0000:01:00.0] 0x947b[ ]: ZM_REG	R[0x1223b0] = 0x00000400
>[    0.398910] nouveau T[   VBIOS][0000:01:00.0] 0x9484[ ]: DONE
>[    0.398911] nouveau T[   VBIOS][0000:01:00.0] 0x9582[ ]: ZM_REG_GROUP	R[0x00c800] =
>[    0.398912] nouveau T[   VBIOS][0000:01:00.0] 0x9588[ ]: 	0x00000000
>[    0.398913] nouveau T[   VBIOS][0000:01:00.0] 0x958c[ ]: 	0x80028f6b
>[    0.398914] nouveau T[   VBIOS][0000:01:00.0] 0x9590[ ]: CONDITION_TIME	0x0e 0xff
>[    0.398914] nouveau T[   VBIOS][0000:01:00.0] 0x9593[ ]: RESUME
>[    0.398915] nouveau T[   VBIOS][0000:01:00.0] 0x9594[ ]: ZM_REG	R[0x00c804] = 0x00020000
>[    0.398916] nouveau T[   VBIOS][0000:01:00.0] 0x959d[ ]: REPEAT	0x02
>[    0.398917] nouveau T[   VBIOS][0000:01:00.0] 0x959f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398918] nouveau T[   VBIOS][0000:01:00.0] 0x95a8[ ]: END_REPEAT
>[    0.398919] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398919] nouveau T[   VBIOS][0000:01:00.0] 0x959f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398920] nouveau T[   VBIOS][0000:01:00.0] 0x95a8[ ]: END_REPEAT
>[    0.398921] nouveau T[   VBIOS][0000:01:00.0] 0x95a9[ ]: ZM_REG_GROUP	R[0x00c804] =
>[    0.398922] nouveau T[   VBIOS][0000:01:00.0] 0x95af[ ]: 	0x00000008
>[    0.398923] nouveau T[   VBIOS][0000:01:00.0] 0x95b3[ ]: 	0x00000000
>[    0.398923] nouveau T[   VBIOS][0000:01:00.0] 0x95b7[ ]: 	0x00200000
>[    0.398924] nouveau T[   VBIOS][0000:01:00.0] 0x95bb[ ]: REPEAT	0x03
>[    0.398925] nouveau T[   VBIOS][0000:01:00.0] 0x95bd[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398926] nouveau T[   VBIOS][0000:01:00.0] 0x95c6[ ]: END_REPEAT
>[    0.398927] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.398928] nouveau T[   VBIOS][0000:01:00.0] 0x95bd[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398928] nouveau T[   VBIOS][0000:01:00.0] 0x95c6[ ]: END_REPEAT
>[    0.398929] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398930] nouveau T[   VBIOS][0000:01:00.0] 0x95bd[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398931] nouveau T[   VBIOS][0000:01:00.0] 0x95c6[ ]: END_REPEAT
>[    0.398932] nouveau T[   VBIOS][0000:01:00.0] 0x95c7[ ]: ZM_REG	R[0x00c804] = 0x00010000
>[    0.398933] nouveau T[   VBIOS][0000:01:00.0] 0x95d0[ ]: REPEAT	0x02
>[    0.398933] nouveau T[   VBIOS][0000:01:00.0] 0x95d2[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398934] nouveau T[   VBIOS][0000:01:00.0] 0x95db[ ]: END_REPEAT
>[    0.398935] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398936] nouveau T[   VBIOS][0000:01:00.0] 0x95d2[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398937] nouveau T[   VBIOS][0000:01:00.0] 0x95db[ ]: END_REPEAT
>[    0.398937] nouveau T[   VBIOS][0000:01:00.0] 0x95dc[ ]: ZM_REG_GROUP	R[0x00c804] =
>[    0.398938] nouveau T[   VBIOS][0000:01:00.0] 0x95e2[ ]: 	0x00000004
>[    0.398939] nouveau T[   VBIOS][0000:01:00.0] 0x95e6[ ]: 	0x00000800
>[    0.398940] nouveau T[   VBIOS][0000:01:00.0] 0x95ea[ ]: 	0x00000000
>[    0.398941] nouveau T[   VBIOS][0000:01:00.0] 0x95ee[ ]: 	0x20000000
>[    0.398941] nouveau T[   VBIOS][0000:01:00.0] 0x95f2[ ]: REPEAT	0x02
>[    0.398942] nouveau T[   VBIOS][0000:01:00.0] 0x95f4[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398943] nouveau T[   VBIOS][0000:01:00.0] 0x95fd[ ]: END_REPEAT
>[    0.398944] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398945] nouveau T[   VBIOS][0000:01:00.0] 0x95f4[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398946] nouveau T[   VBIOS][0000:01:00.0] 0x95fd[ ]: END_REPEAT
>[    0.398946] nouveau T[   VBIOS][0000:01:00.0] 0x95fe[ ]: ZM_REG	R[0x00c804] = 0x00008000
>[    0.398947] nouveau T[   VBIOS][0000:01:00.0] 0x9607[ ]: REPEAT	0x02
>[    0.398948] nouveau T[   VBIOS][0000:01:00.0] 0x9609[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398949] nouveau T[   VBIOS][0000:01:00.0] 0x9612[ ]: END_REPEAT
>[    0.398950] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398950] nouveau T[   VBIOS][0000:01:00.0] 0x9609[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398951] nouveau T[   VBIOS][0000:01:00.0] 0x9612[ ]: END_REPEAT
>[    0.398952] nouveau T[   VBIOS][0000:01:00.0] 0x9613[ ]: ZM_REG_GROUP	R[0x00c800] =
>[    0.398953] nouveau T[   VBIOS][0000:01:00.0] 0x9619[ ]: 	0x00000000
>[    0.398954] nouveau T[   VBIOS][0000:01:00.0] 0x961d[ ]: 	0x80076f6a
>[    0.398955] nouveau T[   VBIOS][0000:01:00.0] 0x9621[ ]: CONDITION_TIME	0x0e 0xff
>[    0.398955] nouveau T[   VBIOS][0000:01:00.0] 0x9624[ ]: RESUME
>[    0.398956] nouveau T[   VBIOS][0000:01:00.0] 0x9625[ ]: ZM_REG_GROUP	R[0x00c804] =
>[    0.398957] nouveau T[   VBIOS][0000:01:00.0] 0x962b[ ]: 	0x00000000
>[    0.398958] nouveau T[   VBIOS][0000:01:00.0] 0x962f[ ]: 	0x00008000
>[    0.398959] nouveau T[   VBIOS][0000:01:00.0] 0x9633[ ]: REPEAT	0x06
>[    0.398959] nouveau T[   VBIOS][0000:01:00.0] 0x9635[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398960] nouveau T[   VBIOS][0000:01:00.0] 0x963e[ ]: END_REPEAT
>[    0.398961] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.398962] nouveau T[   VBIOS][0000:01:00.0] 0x9635[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398963] nouveau T[   VBIOS][0000:01:00.0] 0x963e[ ]: END_REPEAT
>[    0.398963] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.398964] nouveau T[   VBIOS][0000:01:00.0] 0x9635[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398965] nouveau T[   VBIOS][0000:01:00.0] 0x963e[ ]: END_REPEAT
>[    0.398966] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.398967] nouveau T[   VBIOS][0000:01:00.0] 0x9635[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398967] nouveau T[   VBIOS][0000:01:00.0] 0x963e[ ]: END_REPEAT
>[    0.398968] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.398969] nouveau T[   VBIOS][0000:01:00.0] 0x9635[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398970] nouveau T[   VBIOS][0000:01:00.0] 0x963e[ ]: END_REPEAT
>[    0.398971] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398971] nouveau T[   VBIOS][0000:01:00.0] 0x9635[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398972] nouveau T[   VBIOS][0000:01:00.0] 0x963e[ ]: END_REPEAT
>[    0.398973] nouveau T[   VBIOS][0000:01:00.0] 0x963f[ ]: ZM_REG	R[0x00c804] = 0x20000000
>[    0.398974] nouveau T[   VBIOS][0000:01:00.0] 0x9648[ ]: REPEAT	0x07
>[    0.398975] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398976] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398976] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>[    0.398977] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398978] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398979] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.398980] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398980] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398981] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.398982] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398983] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398984] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.398984] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398985] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398986] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.398987] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398988] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398988] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.398989] nouveau T[   VBIOS][0000:01:00.0] 0x964a[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398990] nouveau T[   VBIOS][0000:01:00.0] 0x9653[ ]: END_REPEAT
>[    0.398991] nouveau T[   VBIOS][0000:01:00.0] 0x9654[ ]: ZM_REG	R[0x00c804] = 0x00000800
>[    0.398992] nouveau T[   VBIOS][0000:01:00.0] 0x965d[ ]: REPEAT	0x0a
>[    0.398993] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398993] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.398994] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x09
>[    0.398995] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398996] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.398997] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x08
>[    0.398997] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.398998] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.398999] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x07
>[    0.399000] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399001] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>[    0.399002] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399003] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399004] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.399005] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399006] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399006] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.399007] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399008] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399009] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.399010] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399010] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399011] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.399012] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399013] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399014] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.399014] nouveau T[   VBIOS][0000:01:00.0] 0x965f[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399015] nouveau T[   VBIOS][0000:01:00.0] 0x9668[ ]: END_REPEAT
>[    0.399016] nouveau T[   VBIOS][0000:01:00.0] 0x9669[ ]: ZM_REG	R[0x00c804] = 0x00010000
>[    0.399017] nouveau T[   VBIOS][0000:01:00.0] 0x9672[ ]: REPEAT	0x06
>[    0.399018] nouveau T[   VBIOS][0000:01:00.0] 0x9674[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399018] nouveau T[   VBIOS][0000:01:00.0] 0x967d[ ]: END_REPEAT
>[    0.399019] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.399020] nouveau T[   VBIOS][0000:01:00.0] 0x9674[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399021] nouveau T[   VBIOS][0000:01:00.0] 0x967d[ ]: END_REPEAT
>[    0.399022] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.399022] nouveau T[   VBIOS][0000:01:00.0] 0x9674[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399023] nouveau T[   VBIOS][0000:01:00.0] 0x967d[ ]: END_REPEAT
>[    0.399024] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.399025] nouveau T[   VBIOS][0000:01:00.0] 0x9674[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399026] nouveau T[   VBIOS][0000:01:00.0] 0x967d[ ]: END_REPEAT
>[    0.399026] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.399027] nouveau T[   VBIOS][0000:01:00.0] 0x9674[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399028] nouveau T[   VBIOS][0000:01:00.0] 0x967d[ ]: END_REPEAT
>[    0.399029] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.399030] nouveau T[   VBIOS][0000:01:00.0] 0x9674[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399030] nouveau T[   VBIOS][0000:01:00.0] 0x967d[ ]: END_REPEAT
>[    0.399031] nouveau T[   VBIOS][0000:01:00.0] 0x967e[ ]: ZM_REG	R[0x00c804] = 0x40000000
>[    0.399032] nouveau T[   VBIOS][0000:01:00.0] 0x9687[ ]: REPEAT	0x03
>[    0.399033] nouveau T[   VBIOS][0000:01:00.0] 0x9689[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399034] nouveau T[   VBIOS][0000:01:00.0] 0x9692[ ]: END_REPEAT
>[    0.399035] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.399035] nouveau T[   VBIOS][0000:01:00.0] 0x9689[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399036] nouveau T[   VBIOS][0000:01:00.0] 0x9692[ ]: END_REPEAT
>[    0.399037] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.399038] nouveau T[   VBIOS][0000:01:00.0] 0x9689[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399039] nouveau T[   VBIOS][0000:01:00.0] 0x9692[ ]: END_REPEAT
>[    0.399040] nouveau T[   VBIOS][0000:01:00.0] 0x9693[ ]: ZM_REG	R[0x00c804] = 0x00200000
>[    0.399040] nouveau T[   VBIOS][0000:01:00.0] 0x969c[ ]: REPEAT	0x07
>[    0.399041] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399042] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399043] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>[    0.399044] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399044] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399045] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.399046] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399047] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399048] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.399048] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399049] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399050] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.399051] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399052] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399052] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.399053] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399054] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399055] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.399056] nouveau T[   VBIOS][0000:01:00.0] 0x969e[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399056] nouveau T[   VBIOS][0000:01:00.0] 0x96a7[ ]: END_REPEAT
>[    0.399057] nouveau T[   VBIOS][0000:01:00.0] 0x96a8[ ]: ZM_REG	R[0x00c804] = 0x00000008
>[    0.399058] nouveau T[   VBIOS][0000:01:00.0] 0x96b1[ ]: REPEAT	0x06
>[    0.399059] nouveau T[   VBIOS][0000:01:00.0] 0x96b3[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399060] nouveau T[   VBIOS][0000:01:00.0] 0x96bc[ ]: END_REPEAT
>[    0.399060] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.399061] nouveau T[   VBIOS][0000:01:00.0] 0x96b3[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399062] nouveau T[   VBIOS][0000:01:00.0] 0x96bc[ ]: END_REPEAT
>[    0.399063] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.399064] nouveau T[   VBIOS][0000:01:00.0] 0x96b3[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399064] nouveau T[   VBIOS][0000:01:00.0] 0x96bc[ ]: END_REPEAT
>[    0.399065] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.399066] nouveau T[   VBIOS][0000:01:00.0] 0x96b3[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399067] nouveau T[   VBIOS][0000:01:00.0] 0x96bc[ ]: END_REPEAT
>[    0.399068] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.399069] nouveau T[   VBIOS][0000:01:00.0] 0x96b3[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399069] nouveau T[   VBIOS][0000:01:00.0] 0x96bc[ ]: END_REPEAT
>[    0.399070] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.399071] nouveau T[   VBIOS][0000:01:00.0] 0x96b3[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399072] nouveau T[   VBIOS][0000:01:00.0] 0x96bc[ ]: END_REPEAT
>[    0.399073] nouveau T[   VBIOS][0000:01:00.0] 0x96bd[ ]: ZM_REG	R[0x00c804] = 0x00020000
>[    0.399073] nouveau T[   VBIOS][0000:01:00.0] 0x96c6[ ]: REPEAT	0x06
>[    0.399074] nouveau T[   VBIOS][0000:01:00.0] 0x96c8[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399075] nouveau T[   VBIOS][0000:01:00.0] 0x96d1[ ]: END_REPEAT
>[    0.399076] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[    0.399077] nouveau T[   VBIOS][0000:01:00.0] 0x96c8[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399077] nouveau T[   VBIOS][0000:01:00.0] 0x96d1[ ]: END_REPEAT
>[    0.399078] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.399079] nouveau T[   VBIOS][0000:01:00.0] 0x96c8[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399080] nouveau T[   VBIOS][0000:01:00.0] 0x96d1[ ]: END_REPEAT
>[    0.399081] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.399081] nouveau T[   VBIOS][0000:01:00.0] 0x96c8[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399082] nouveau T[   VBIOS][0000:01:00.0] 0x96d1[ ]: END_REPEAT
>[    0.399083] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.399084] nouveau T[   VBIOS][0000:01:00.0] 0x96c8[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399085] nouveau T[   VBIOS][0000:01:00.0] 0x96d1[ ]: END_REPEAT
>[    0.399085] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.399086] nouveau T[   VBIOS][0000:01:00.0] 0x96c8[ ]: ZM_REG	R[0x00c804] = 0x00000000
>[    0.399087] nouveau T[   VBIOS][0000:01:00.0] 0x96d1[ ]: END_REPEAT
>[    0.399101] nouveau T[   VBIOS][0000:01:00.0] 0x96d2[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00110050] 0x04 0x01
>[    0.399102] nouveau T[   VBIOS][0000:01:00.0] 0x96d9[ ]: 	R[0x110050] = {
>[    0.399103] nouveau T[   VBIOS][0000:01:00.0] 0x96d9[ ]: 		0xff001045
>[    0.399104] nouveau T[   VBIOS][0000:01:00.0] 0x96dd[ ]: 		0xff001045
>[    0.399104] nouveau T[   VBIOS][0000:01:00.0] 0x96e1[ ]: 		0xff001045 *
>[    0.399105] nouveau T[   VBIOS][0000:01:00.0] 0x96e5[ ]: 		0x7f001045
>[    0.399106] nouveau T[   VBIOS][0000:01:00.0] 0x96e9[ ]: 		0xff001045
>[    0.399107] nouveau T[   VBIOS][0000:01:00.0] 0x96ed[ ]: 		0xff001045
>[    0.399108] nouveau T[   VBIOS][0000:01:00.0] 0x96f1[ ]: 		0xff001045
>[    0.399108] nouveau T[   VBIOS][0000:01:00.0] 0x96f5[ ]: 		0xff001045
>[    0.399109] nouveau T[   VBIOS][0000:01:00.0] 0x96f9[ ]: 	}
>[    0.399110] nouveau T[   VBIOS][0000:01:00.0] 0x96f9[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111050] 0x04 0x01
>[    0.399111] nouveau T[   VBIOS][0000:01:00.0] 0x9700[ ]: 	R[0x111050] = {
>[    0.399112] nouveau T[   VBIOS][0000:01:00.0] 0x9700[ ]: 		0xff001053
>[    0.399113] nouveau T[   VBIOS][0000:01:00.0] 0x9704[ ]: 		0xff001053
>[    0.399114] nouveau T[   VBIOS][0000:01:00.0] 0x9708[ ]: 		0xff001053 *
>[    0.399114] nouveau T[   VBIOS][0000:01:00.0] 0x970c[ ]: 		0x7f001053
>[    0.399115] nouveau T[   VBIOS][0000:01:00.0] 0x9710[ ]: 		0xff001053
>[    0.399116] nouveau T[   VBIOS][0000:01:00.0] 0x9714[ ]: 		0xff001053
>[    0.399117] nouveau T[   VBIOS][0000:01:00.0] 0x9718[ ]: 		0xff001053
>[    0.399117] nouveau T[   VBIOS][0000:01:00.0] 0x971c[ ]: 		0xff001053
>[    0.399118] nouveau T[   VBIOS][0000:01:00.0] 0x9720[ ]: 	}
>[    0.399119] nouveau T[   VBIOS][0000:01:00.0] 0x9720[ ]: ZM_REG	R[0x11e590] = 0x03000304
>[    0.399120] nouveau T[   VBIOS][0000:01:00.0] 0x9729[ ]: ZM_REG	R[0x11e510] = 0x80000000
>[    0.399121] nouveau T[   VBIOS][0000:01:00.0] 0x9732[ ]: ZM_REG	R[0x11e8d8] = 0x00005555
>[    0.399122] nouveau T[   VBIOS][0000:01:00.0] 0x973b[ ]: ZM_REG	R[0x11e8dc] = 0x00000009
>[    0.399123] nouveau T[   VBIOS][0000:01:00.0] 0x9744[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e610] 0x04 0x02
>[    0.399124] nouveau T[   VBIOS][0000:01:00.0] 0x974b[ ]: 	R[0x11e610] = {
>[    0.399125] nouveau T[   VBIOS][0000:01:00.0] 0x974b[ ]: 		0x50055e77
>[    0.399125] nouveau T[   VBIOS][0000:01:00.0] 0x974f[ ]: 		0x50055e77
>[    0.399126] nouveau T[   VBIOS][0000:01:00.0] 0x9753[ ]: 		0x50055e77 *
>[    0.399127] nouveau T[   VBIOS][0000:01:00.0] 0x9757[ ]: 		0x50055e77
>[    0.399128] nouveau T[   VBIOS][0000:01:00.0] 0x975b[ ]: 		0x50055e77
>[    0.399128] nouveau T[   VBIOS][0000:01:00.0] 0x975f[ ]: 		0x50055e77
>[    0.399129] nouveau T[   VBIOS][0000:01:00.0] 0x9763[ ]: 		0x50055e77
>[    0.399130] nouveau T[   VBIOS][0000:01:00.0] 0x9767[ ]: 		0x50055e77
>[    0.399131] nouveau T[   VBIOS][0000:01:00.0] 0x976b[ ]: 	}
>[    0.399132] nouveau T[   VBIOS][0000:01:00.0] 0x976b[ ]: 	R[0x11e614] = {
>[    0.399132] nouveau T[   VBIOS][0000:01:00.0] 0x976b[ ]: 		0x50055e77
>[    0.399133] nouveau T[   VBIOS][0000:01:00.0] 0x976f[ ]: 		0x50055e77
>[    0.399134] nouveau T[   VBIOS][0000:01:00.0] 0x9773[ ]: 		0x50055e77 *
>[    0.399135] nouveau T[   VBIOS][0000:01:00.0] 0x9777[ ]: 		0x50055e77
>[    0.399136] nouveau T[   VBIOS][0000:01:00.0] 0x977b[ ]: 		0x50055e77
>[    0.399136] nouveau T[   VBIOS][0000:01:00.0] 0x977f[ ]: 		0x50055e77
>[    0.399137] nouveau T[   VBIOS][0000:01:00.0] 0x9783[ ]: 		0x50055e77
>[    0.399138] nouveau T[   VBIOS][0000:01:00.0] 0x9787[ ]: 		0x50055e77
>[    0.399139] nouveau T[   VBIOS][0000:01:00.0] 0x978b[ ]: 	}
>[    0.399140] nouveau T[   VBIOS][0000:01:00.0] 0x978b[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100778] 0x04 0x01
>[    0.399141] nouveau T[   VBIOS][0000:01:00.0] 0x9792[ ]: 	R[0x100778] = {
>[    0.399141] nouveau T[   VBIOS][0000:01:00.0] 0x9792[ ]: 		0x00000555
>[    0.399142] nouveau T[   VBIOS][0000:01:00.0] 0x9796[ ]: 		0x00000555
>[    0.399143] nouveau T[   VBIOS][0000:01:00.0] 0x979a[ ]: 		0x00000555 *
>[    0.399144] nouveau T[   VBIOS][0000:01:00.0] 0x979e[ ]: 		0x00000555
>[    0.399144] nouveau T[   VBIOS][0000:01:00.0] 0x97a2[ ]: 		0x00000555
>[    0.399145] nouveau T[   VBIOS][0000:01:00.0] 0x97a6[ ]: 		0x00000555
>[    0.399146] nouveau T[   VBIOS][0000:01:00.0] 0x97aa[ ]: 		0x00000555
>[    0.399147] nouveau T[   VBIOS][0000:01:00.0] 0x97ae[ ]: 		0x00000555
>[    0.399148] nouveau T[   VBIOS][0000:01:00.0] 0x97b2[ ]: 	}
>[    0.399149] nouveau T[   VBIOS][0000:01:00.0] 0x97b2[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011eec4] 0x04 0x02
>[    0.399149] nouveau T[   VBIOS][0000:01:00.0] 0x97b9[ ]: 	R[0x11eec4] = {
>[    0.399150] nouveau T[   VBIOS][0000:01:00.0] 0x97b9[ ]: 		0x00140a05
>[    0.399151] nouveau T[   VBIOS][0000:01:00.0] 0x97bd[ ]: 		0x00140a05
>[    0.399152] nouveau T[   VBIOS][0000:01:00.0] 0x97c1[ ]: 		0x00140a05 *
>[    0.399153] nouveau T[   VBIOS][0000:01:00.0] 0x97c5[ ]: 		0x00140a05
>[    0.399153] nouveau T[   VBIOS][0000:01:00.0] 0x97c9[ ]: 		0x00140a05
>[    0.399154] nouveau T[   VBIOS][0000:01:00.0] 0x97cd[ ]: 		0x00140a05
>[    0.399155] nouveau T[   VBIOS][0000:01:00.0] 0x97d1[ ]: 		0x00140a05
>[    0.399156] nouveau T[   VBIOS][0000:01:00.0] 0x97d5[ ]: 		0x00140a05
>[    0.399156] nouveau T[   VBIOS][0000:01:00.0] 0x97d9[ ]: 	}
>[    0.399157] nouveau T[   VBIOS][0000:01:00.0] 0x97d9[ ]: 	R[0x11eec8] = {
>[    0.399158] nouveau T[   VBIOS][0000:01:00.0] 0x97d9[ ]: 		0x00000003
>[    0.399159] nouveau T[   VBIOS][0000:01:00.0] 0x97dd[ ]: 		0x00000003
>[    0.399160] nouveau T[   VBIOS][0000:01:00.0] 0x97e1[ ]: 		0x00000003 *
>[    0.399160] nouveau T[   VBIOS][0000:01:00.0] 0x97e5[ ]: 		0x00000003
>[    0.399161] nouveau T[   VBIOS][0000:01:00.0] 0x97e9[ ]: 		0x00000003
>[    0.399162] nouveau T[   VBIOS][0000:01:00.0] 0x97ed[ ]: 		0x00000003
>[    0.399163] nouveau T[   VBIOS][0000:01:00.0] 0x97f1[ ]: 		0x00000003
>[    0.399163] nouveau T[   VBIOS][0000:01:00.0] 0x97f5[ ]: 		0x00000003
>[    0.399164] nouveau T[   VBIOS][0000:01:00.0] 0x97f9[ ]: 	}
>[    0.399165] nouveau T[   VBIOS][0000:01:00.0] 0x97f9[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00131c40] 0x04 0x01
>[    0.399166] nouveau T[   VBIOS][0000:01:00.0] 0x9800[ ]: 	R[0x131c40] = {
>[    0.399167] nouveau T[   VBIOS][0000:01:00.0] 0x9800[ ]: 		0x00000000
>[    0.399168] nouveau T[   VBIOS][0000:01:00.0] 0x9804[ ]: 		0x00000000
>[    0.399168] nouveau T[   VBIOS][0000:01:00.0] 0x9808[ ]: 		0x00000000 *
>[    0.399169] nouveau T[   VBIOS][0000:01:00.0] 0x980c[ ]: 		0x00000000
>[    0.399170] nouveau T[   VBIOS][0000:01:00.0] 0x9810[ ]: 		0x00000000
>[    0.399171] nouveau T[   VBIOS][0000:01:00.0] 0x9814[ ]: 		0x00000000
>[    0.399171] nouveau T[   VBIOS][0000:01:00.0] 0x9818[ ]: 		0x00000000
>[    0.399172] nouveau T[   VBIOS][0000:01:00.0] 0x981c[ ]: 		0x00000000
>[    0.399173] nouveau T[   VBIOS][0000:01:00.0] 0x9820[ ]: 	}
>[    0.399174] nouveau T[   VBIOS][0000:01:00.0] 0x9820[ ]: ZM_REG	R[0x11e61c] = 0x01110111
>[    0.399175] nouveau T[   VBIOS][0000:01:00.0] 0x9829[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100770] 0x04 0x01
>[    0.399176] nouveau T[   VBIOS][0000:01:00.0] 0x9830[ ]: 	R[0x100770] = {
>[    0.399176] nouveau T[   VBIOS][0000:01:00.0] 0x9830[ ]: 		0x00000006
>[    0.399177] nouveau T[   VBIOS][0000:01:00.0] 0x9834[ ]: 		0x00000006
>[    0.399178] nouveau T[   VBIOS][0000:01:00.0] 0x9838[ ]: 		0x00000006 *
>[    0.399179] nouveau T[   VBIOS][0000:01:00.0] 0x983c[ ]: 		0x00000006
>[    0.399180] nouveau T[   VBIOS][0000:01:00.0] 0x9840[ ]: 		0x00000006
>[    0.399180] nouveau T[   VBIOS][0000:01:00.0] 0x9844[ ]: 		0x00000006
>[    0.399181] nouveau T[   VBIOS][0000:01:00.0] 0x9848[ ]: 		0x00000004
>[    0.399182] nouveau T[   VBIOS][0000:01:00.0] 0x984c[ ]: 		0x00000004
>[    0.399183] nouveau T[   VBIOS][0000:01:00.0] 0x9850[ ]: 	}
>[    0.399184] nouveau T[   VBIOS][0000:01:00.0] 0x9850[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00110d70] 0x04 0x0a
>[    0.399184] nouveau T[   VBIOS][0000:01:00.0] 0x9857[ ]: 	R[0x110d70] = {
>[    0.399185] nouveau T[   VBIOS][0000:01:00.0] 0x9857[ ]: 		0x00000000
>[    0.399186] nouveau T[   VBIOS][0000:01:00.0] 0x985b[ ]: 		0x30303030
>[    0.399187] nouveau T[   VBIOS][0000:01:00.0] 0x985f[ ]: 		0x1a1a1a1a *
>[    0.399188] nouveau T[   VBIOS][0000:01:00.0] 0x9863[ ]: 		0x00000000
>[    0.399188] nouveau T[   VBIOS][0000:01:00.0] 0x9867[ ]: 		0x1a1a1a1a
>[    0.399189] nouveau T[   VBIOS][0000:01:00.0] 0x986b[ ]: 		0x20202020
>[    0.399190] nouveau T[   VBIOS][0000:01:00.0] 0x986f[ ]: 		0x00000000
>[    0.399191] nouveau T[   VBIOS][0000:01:00.0] 0x9873[ ]: 		0x00000000
>[    0.399191] nouveau T[   VBIOS][0000:01:00.0] 0x9877[ ]: 	}
>[    0.399192] nouveau T[   VBIOS][0000:01:00.0] 0x9877[ ]: 	R[0x110d74] = {
>[    0.399193] nouveau T[   VBIOS][0000:01:00.0] 0x9877[ ]: 		0x00000000
>[    0.399194] nouveau T[   VBIOS][0000:01:00.0] 0x987b[ ]: 		0x30303030
>[    0.399195] nouveau T[   VBIOS][0000:01:00.0] 0x987f[ ]: 		0x1a1a1a1a *
>[    0.399195] nouveau T[   VBIOS][0000:01:00.0] 0x9883[ ]: 		0x00000000
>[    0.399196] nouveau T[   VBIOS][0000:01:00.0] 0x9887[ ]: 		0x1a1a1a1a
>[    0.399197] nouveau T[   VBIOS][0000:01:00.0] 0x988b[ ]: 		0x20202020
>[    0.399198] nouveau T[   VBIOS][0000:01:00.0] 0x988f[ ]: 		0x00000000
>[    0.399198] nouveau T[   VBIOS][0000:01:00.0] 0x9893[ ]: 		0x00000000
>[    0.399199] nouveau T[   VBIOS][0000:01:00.0] 0x9897[ ]: 	}
>[    0.399200] nouveau T[   VBIOS][0000:01:00.0] 0x9897[ ]: 	R[0x110d78] = {
>[    0.399201] nouveau T[   VBIOS][0000:01:00.0] 0x9897[ ]: 		0x00000000
>[    0.399202] nouveau T[   VBIOS][0000:01:00.0] 0x989b[ ]: 		0x30303030
>[    0.399202] nouveau T[   VBIOS][0000:01:00.0] 0x989f[ ]: 		0x1a1a1a1a *
>[    0.399203] nouveau T[   VBIOS][0000:01:00.0] 0x98a3[ ]: 		0x00000000
>[    0.399204] nouveau T[   VBIOS][0000:01:00.0] 0x98a7[ ]: 		0x1a1a1a1a
>[    0.399205] nouveau T[   VBIOS][0000:01:00.0] 0x98ab[ ]: 		0x20202020
>[    0.399205] nouveau T[   VBIOS][0000:01:00.0] 0x98af[ ]: 		0x00000000
>[    0.399206] nouveau T[   VBIOS][0000:01:00.0] 0x98b3[ ]: 		0x00000000
>[    0.399207] nouveau T[   VBIOS][0000:01:00.0] 0x98b7[ ]: 	}
>[    0.399208] nouveau T[   VBIOS][0000:01:00.0] 0x98b7[ ]: 	R[0x110d7c] = {
>[    0.399209] nouveau T[   VBIOS][0000:01:00.0] 0x98b7[ ]: 		0x00000000
>[    0.399209] nouveau T[   VBIOS][0000:01:00.0] 0x98bb[ ]: 		0x30303030
>[    0.399210] nouveau T[   VBIOS][0000:01:00.0] 0x98bf[ ]: 		0x1a1a1a1a *
>[    0.399211] nouveau T[   VBIOS][0000:01:00.0] 0x98c3[ ]: 		0x00000000
>[    0.399212] nouveau T[   VBIOS][0000:01:00.0] 0x98c7[ ]: 		0x1a1a1a1a
>[    0.399213] nouveau T[   VBIOS][0000:01:00.0] 0x98cb[ ]: 		0x20202020
>[    0.399213] nouveau T[   VBIOS][0000:01:00.0] 0x98cf[ ]: 		0x00000000
>[    0.399214] nouveau T[   VBIOS][0000:01:00.0] 0x98d3[ ]: 		0x00000000
>[    0.399215] nouveau T[   VBIOS][0000:01:00.0] 0x98d7[ ]: 	}
>[    0.399216] nouveau T[   VBIOS][0000:01:00.0] 0x98d7[ ]: 	R[0x110d80] = {
>[    0.399216] nouveau T[   VBIOS][0000:01:00.0] 0x98d7[ ]: 		0x00000000
>[    0.399217] nouveau T[   VBIOS][0000:01:00.0] 0x98db[ ]: 		0x30303030
>[    0.399218] nouveau T[   VBIOS][0000:01:00.0] 0x98df[ ]: 		0x1a1a1a1a *
>[    0.399219] nouveau T[   VBIOS][0000:01:00.0] 0x98e3[ ]: 		0x00000000
>[    0.399220] nouveau T[   VBIOS][0000:01:00.0] 0x98e7[ ]: 		0x1a1a1a1a
>[    0.399220] nouveau T[   VBIOS][0000:01:00.0] 0x98eb[ ]: 		0x20202020
>[    0.399221] nouveau T[   VBIOS][0000:01:00.0] 0x98ef[ ]: 		0x00000000
>[    0.399222] nouveau T[   VBIOS][0000:01:00.0] 0x98f3[ ]: 		0x00000000
>[    0.399223] nouveau T[   VBIOS][0000:01:00.0] 0x98f7[ ]: 	}
>[    0.399223] nouveau T[   VBIOS][0000:01:00.0] 0x98f7[ ]: 	R[0x110d84] = {
>[    0.399224] nouveau T[   VBIOS][0000:01:00.0] 0x98f7[ ]: 		0x00000000
>[    0.399225] nouveau T[   VBIOS][0000:01:00.0] 0x98fb[ ]: 		0x30303030
>[    0.399226] nouveau T[   VBIOS][0000:01:00.0] 0x98ff[ ]: 		0x1a1a1a1a *
>[    0.399227] nouveau T[   VBIOS][0000:01:00.0] 0x9903[ ]: 		0x00000000
>[    0.399227] nouveau T[   VBIOS][0000:01:00.0] 0x9907[ ]: 		0x1a1a1a1a
>[    0.399228] nouveau T[   VBIOS][0000:01:00.0] 0x990b[ ]: 		0x20202020
>[    0.399229] nouveau T[   VBIOS][0000:01:00.0] 0x990f[ ]: 		0x00000000
>[    0.399230] nouveau T[   VBIOS][0000:01:00.0] 0x9913[ ]: 		0x00000000
>[    0.399230] nouveau T[   VBIOS][0000:01:00.0] 0x9917[ ]: 	}
>[    0.399231] nouveau T[   VBIOS][0000:01:00.0] 0x9917[ ]: 	R[0x110d88] = {
>[    0.399232] nouveau T[   VBIOS][0000:01:00.0] 0x9917[ ]: 		0x00000000
>[    0.399233] nouveau T[   VBIOS][0000:01:00.0] 0x991b[ ]: 		0x30303030
>[    0.399234] nouveau T[   VBIOS][0000:01:00.0] 0x991f[ ]: 		0x1a1a1a1a *
>[    0.399234] nouveau T[   VBIOS][0000:01:00.0] 0x9923[ ]: 		0x00000000
>[    0.399235] nouveau T[   VBIOS][0000:01:00.0] 0x9927[ ]: 		0x1a1a1a1a
>[    0.399236] nouveau T[   VBIOS][0000:01:00.0] 0x992b[ ]: 		0x20202020
>[    0.399237] nouveau T[   VBIOS][0000:01:00.0] 0x992f[ ]: 		0x00000000
>[    0.399237] nouveau T[   VBIOS][0000:01:00.0] 0x9933[ ]: 		0x00000000
>[    0.399238] nouveau T[   VBIOS][0000:01:00.0] 0x9937[ ]: 	}
>[    0.399239] nouveau T[   VBIOS][0000:01:00.0] 0x9937[ ]: 	R[0x110d8c] = {
>[    0.399240] nouveau T[   VBIOS][0000:01:00.0] 0x9937[ ]: 		0x00000000
>[    0.399241] nouveau T[   VBIOS][0000:01:00.0] 0x993b[ ]: 		0x30303030
>[    0.399241] nouveau T[   VBIOS][0000:01:00.0] 0x993f[ ]: 		0x1a1a1a1a *
>[    0.399242] nouveau T[   VBIOS][0000:01:00.0] 0x9943[ ]: 		0x00000000
>[    0.399243] nouveau T[   VBIOS][0000:01:00.0] 0x9947[ ]: 		0x1a1a1a1a
>[    0.399244] nouveau T[   VBIOS][0000:01:00.0] 0x994b[ ]: 		0x20202020
>[    0.399245] nouveau T[   VBIOS][0000:01:00.0] 0x994f[ ]: 		0x00000000
>[    0.399245] nouveau T[   VBIOS][0000:01:00.0] 0x9953[ ]: 		0x00000000
>[    0.399246] nouveau T[   VBIOS][0000:01:00.0] 0x9957[ ]: 	}
>[    0.399247] nouveau T[   VBIOS][0000:01:00.0] 0x9957[ ]: 	R[0x110d90] = {
>[    0.399248] nouveau T[   VBIOS][0000:01:00.0] 0x9957[ ]: 		0x00000000
>[    0.399248] nouveau T[   VBIOS][0000:01:00.0] 0x995b[ ]: 		0x30303030
>[    0.399249] nouveau T[   VBIOS][0000:01:00.0] 0x995f[ ]: 		0x1a1a1a1a *
>[    0.399250] nouveau T[   VBIOS][0000:01:00.0] 0x9963[ ]: 		0x00000000
>[    0.399251] nouveau T[   VBIOS][0000:01:00.0] 0x9967[ ]: 		0x1a1a1a1a
>[    0.399252] nouveau T[   VBIOS][0000:01:00.0] 0x996b[ ]: 		0x20202020
>[    0.399252] nouveau T[   VBIOS][0000:01:00.0] 0x996f[ ]: 		0x00000000
>[    0.399253] nouveau T[   VBIOS][0000:01:00.0] 0x9973[ ]: 		0x00000000
>[    0.399254] nouveau T[   VBIOS][0000:01:00.0] 0x9977[ ]: 	}
>[    0.399255] nouveau T[   VBIOS][0000:01:00.0] 0x9977[ ]: 	R[0x110d94] = {
>[    0.399255] nouveau T[   VBIOS][0000:01:00.0] 0x9977[ ]: 		0x00000000
>[    0.399256] nouveau T[   VBIOS][0000:01:00.0] 0x997b[ ]: 		0x30303030
>[    0.399257] nouveau T[   VBIOS][0000:01:00.0] 0x997f[ ]: 		0x1a1a1a1a *
>[    0.399258] nouveau T[   VBIOS][0000:01:00.0] 0x9983[ ]: 		0x00000000
>[    0.399259] nouveau T[   VBIOS][0000:01:00.0] 0x9987[ ]: 		0x1a1a1a1a
>[    0.399259] nouveau T[   VBIOS][0000:01:00.0] 0x998b[ ]: 		0x20202020
>[    0.399260] nouveau T[   VBIOS][0000:01:00.0] 0x998f[ ]: 		0x00000000
>[    0.399261] nouveau T[   VBIOS][0000:01:00.0] 0x9993[ ]: 		0x00000000
>[    0.399262] nouveau T[   VBIOS][0000:01:00.0] 0x9997[ ]: 	}
>[    0.399263] nouveau T[   VBIOS][0000:01:00.0] 0x9997[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111d70] 0x04 0x0a
>[    0.399263] nouveau T[   VBIOS][0000:01:00.0] 0x999e[ ]: 	R[0x111d70] = {
>[    0.399264] nouveau T[   VBIOS][0000:01:00.0] 0x999e[ ]: 		0x00000000
>[    0.399265] nouveau T[   VBIOS][0000:01:00.0] 0x99a2[ ]: 		0x30303030
>[    0.399266] nouveau T[   VBIOS][0000:01:00.0] 0x99a6[ ]: 		0x1a1a1a1a *
>[    0.399267] nouveau T[   VBIOS][0000:01:00.0] 0x99aa[ ]: 		0x00000000
>[    0.399267] nouveau T[   VBIOS][0000:01:00.0] 0x99ae[ ]: 		0x1a1a1a1a
>[    0.399268] nouveau T[   VBIOS][0000:01:00.0] 0x99b2[ ]: 		0x20202020
>[    0.399269] nouveau T[   VBIOS][0000:01:00.0] 0x99b6[ ]: 		0x00000000
>[    0.399270] nouveau T[   VBIOS][0000:01:00.0] 0x99ba[ ]: 		0x00000000
>[    0.399270] nouveau T[   VBIOS][0000:01:00.0] 0x99be[ ]: 	}
>[    0.399271] nouveau T[   VBIOS][0000:01:00.0] 0x99be[ ]: 	R[0x111d74] = {
>[    0.399272] nouveau T[   VBIOS][0000:01:00.0] 0x99be[ ]: 		0x00000000
>[    0.399273] nouveau T[   VBIOS][0000:01:00.0] 0x99c2[ ]: 		0x30303030
>[    0.399274] nouveau T[   VBIOS][0000:01:00.0] 0x99c6[ ]: 		0x1a1a1a1a *
>[    0.399274] nouveau T[   VBIOS][0000:01:00.0] 0x99ca[ ]: 		0x00000000
>[    0.399275] nouveau T[   VBIOS][0000:01:00.0] 0x99ce[ ]: 		0x1a1a1a1a
>[    0.399276] nouveau T[   VBIOS][0000:01:00.0] 0x99d2[ ]: 		0x20202020
>[    0.399277] nouveau T[   VBIOS][0000:01:00.0] 0x99d6[ ]: 		0x00000000
>[    0.399277] nouveau T[   VBIOS][0000:01:00.0] 0x99da[ ]: 		0x00000000
>[    0.399278] nouveau T[   VBIOS][0000:01:00.0] 0x99de[ ]: 	}
>[    0.399279] nouveau T[   VBIOS][0000:01:00.0] 0x99de[ ]: 	R[0x111d78] = {
>[    0.399280] nouveau T[   VBIOS][0000:01:00.0] 0x99de[ ]: 		0x00000000
>[    0.399281] nouveau T[   VBIOS][0000:01:00.0] 0x99e2[ ]: 		0x30303030
>[    0.399281] nouveau T[   VBIOS][0000:01:00.0] 0x99e6[ ]: 		0x1a1a1a1a *
>[    0.399282] nouveau T[   VBIOS][0000:01:00.0] 0x99ea[ ]: 		0x00000000
>[    0.399283] nouveau T[   VBIOS][0000:01:00.0] 0x99ee[ ]: 		0x1a1a1a1a
>[    0.399284] nouveau T[   VBIOS][0000:01:00.0] 0x99f2[ ]: 		0x20202020
>[    0.399285] nouveau T[   VBIOS][0000:01:00.0] 0x99f6[ ]: 		0x00000000
>[    0.399285] nouveau T[   VBIOS][0000:01:00.0] 0x99fa[ ]: 		0x00000000
>[    0.399286] nouveau T[   VBIOS][0000:01:00.0] 0x99fe[ ]: 	}
>[    0.399287] nouveau T[   VBIOS][0000:01:00.0] 0x99fe[ ]: 	R[0x111d7c] = {
>[    0.399288] nouveau T[   VBIOS][0000:01:00.0] 0x99fe[ ]: 		0x00000000
>[    0.399288] nouveau T[   VBIOS][0000:01:00.0] 0x9a02[ ]: 		0x30303030
>[    0.399289] nouveau T[   VBIOS][0000:01:00.0] 0x9a06[ ]: 		0x1a1a1a1a *
>[    0.399290] nouveau T[   VBIOS][0000:01:00.0] 0x9a0a[ ]: 		0x00000000
>[    0.399291] nouveau T[   VBIOS][0000:01:00.0] 0x9a0e[ ]: 		0x1a1a1a1a
>[    0.399292] nouveau T[   VBIOS][0000:01:00.0] 0x9a12[ ]: 		0x20202020
>[    0.399292] nouveau T[   VBIOS][0000:01:00.0] 0x9a16[ ]: 		0x00000000
>[    0.399293] nouveau T[   VBIOS][0000:01:00.0] 0x9a1a[ ]: 		0x00000000
>[    0.399294] nouveau T[   VBIOS][0000:01:00.0] 0x9a1e[ ]: 	}
>[    0.399295] nouveau T[   VBIOS][0000:01:00.0] 0x9a1e[ ]: 	R[0x111d80] = {
>[    0.399295] nouveau T[   VBIOS][0000:01:00.0] 0x9a1e[ ]: 		0x00000000
>[    0.399296] nouveau T[   VBIOS][0000:01:00.0] 0x9a22[ ]: 		0x30303030
>[    0.399297] nouveau T[   VBIOS][0000:01:00.0] 0x9a26[ ]: 		0x1a1a1a1a *
>[    0.399298] nouveau T[   VBIOS][0000:01:00.0] 0x9a2a[ ]: 		0x00000000
>[    0.399299] nouveau T[   VBIOS][0000:01:00.0] 0x9a2e[ ]: 		0x1a1a1a1a
>[    0.399299] nouveau T[   VBIOS][0000:01:00.0] 0x9a32[ ]: 		0x20202020
>[    0.399300] nouveau T[   VBIOS][0000:01:00.0] 0x9a36[ ]: 		0x00000000
>[    0.399301] nouveau T[   VBIOS][0000:01:00.0] 0x9a3a[ ]: 		0x00000000
>[    0.399302] nouveau T[   VBIOS][0000:01:00.0] 0x9a3e[ ]: 	}
>[    0.399302] nouveau T[   VBIOS][0000:01:00.0] 0x9a3e[ ]: 	R[0x111d84] = {
>[    0.399303] nouveau T[   VBIOS][0000:01:00.0] 0x9a3e[ ]: 		0x00000000
>[    0.399304] nouveau T[   VBIOS][0000:01:00.0] 0x9a42[ ]: 		0x30303030
>[    0.399305] nouveau T[   VBIOS][0000:01:00.0] 0x9a46[ ]: 		0x1a1a1a1a *
>[    0.399306] nouveau T[   VBIOS][0000:01:00.0] 0x9a4a[ ]: 		0x00000000
>[    0.399306] nouveau T[   VBIOS][0000:01:00.0] 0x9a4e[ ]: 		0x1a1a1a1a
>[    0.399307] nouveau T[   VBIOS][0000:01:00.0] 0x9a52[ ]: 		0x20202020
>[    0.399308] nouveau T[   VBIOS][0000:01:00.0] 0x9a56[ ]: 		0x00000000
>[    0.399309] nouveau T[   VBIOS][0000:01:00.0] 0x9a5a[ ]: 		0x00000000
>[    0.399309] nouveau T[   VBIOS][0000:01:00.0] 0x9a5e[ ]: 	}
>[    0.399310] nouveau T[   VBIOS][0000:01:00.0] 0x9a5e[ ]: 	R[0x111d88] = {
>[    0.399311] nouveau T[   VBIOS][0000:01:00.0] 0x9a5e[ ]: 		0x00000000
>[    0.399312] nouveau T[   VBIOS][0000:01:00.0] 0x9a62[ ]: 		0x30303030
>[    0.399313] nouveau T[   VBIOS][0000:01:00.0] 0x9a66[ ]: 		0x1a1a1a1a *
>[    0.399313] nouveau T[   VBIOS][0000:01:00.0] 0x9a6a[ ]: 		0x00000000
>[    0.399314] nouveau T[   VBIOS][0000:01:00.0] 0x9a6e[ ]: 		0x1a1a1a1a
>[    0.399315] nouveau T[   VBIOS][0000:01:00.0] 0x9a72[ ]: 		0x20202020
>[    0.399316] nouveau T[   VBIOS][0000:01:00.0] 0x9a76[ ]: 		0x00000000
>[    0.399317] nouveau T[   VBIOS][0000:01:00.0] 0x9a7a[ ]: 		0x00000000
>[    0.399317] nouveau T[   VBIOS][0000:01:00.0] 0x9a7e[ ]: 	}
>[    0.399318] nouveau T[   VBIOS][0000:01:00.0] 0x9a7e[ ]: 	R[0x111d8c] = {
>[    0.399319] nouveau T[   VBIOS][0000:01:00.0] 0x9a7e[ ]: 		0x00000000
>[    0.399320] nouveau T[   VBIOS][0000:01:00.0] 0x9a82[ ]: 		0x30303030
>[    0.399320] nouveau T[   VBIOS][0000:01:00.0] 0x9a86[ ]: 		0x1a1a1a1a *
>[    0.399321] nouveau T[   VBIOS][0000:01:00.0] 0x9a8a[ ]: 		0x00000000
>[    0.399322] nouveau T[   VBIOS][0000:01:00.0] 0x9a8e[ ]: 		0x1a1a1a1a
>[    0.399323] nouveau T[   VBIOS][0000:01:00.0] 0x9a92[ ]: 		0x20202020
>[    0.399324] nouveau T[   VBIOS][0000:01:00.0] 0x9a96[ ]: 		0x00000000
>[    0.399324] nouveau T[   VBIOS][0000:01:00.0] 0x9a9a[ ]: 		0x00000000
>[    0.399325] nouveau T[   VBIOS][0000:01:00.0] 0x9a9e[ ]: 	}
>[    0.399326] nouveau T[   VBIOS][0000:01:00.0] 0x9a9e[ ]: 	R[0x111d90] = {
>[    0.399327] nouveau T[   VBIOS][0000:01:00.0] 0x9a9e[ ]: 		0x00000000
>[    0.399327] nouveau T[   VBIOS][0000:01:00.0] 0x9aa2[ ]: 		0x30303030
>[    0.399328] nouveau T[   VBIOS][0000:01:00.0] 0x9aa6[ ]: 		0x1a1a1a1a *
>[    0.399329] nouveau T[   VBIOS][0000:01:00.0] 0x9aaa[ ]: 		0x00000000
>[    0.399330] nouveau T[   VBIOS][0000:01:00.0] 0x9aae[ ]: 		0x1a1a1a1a
>[    0.399331] nouveau T[   VBIOS][0000:01:00.0] 0x9ab2[ ]: 		0x20202020
>[    0.399331] nouveau T[   VBIOS][0000:01:00.0] 0x9ab6[ ]: 		0x00000000
>[    0.399332] nouveau T[   VBIOS][0000:01:00.0] 0x9aba[ ]: 		0x00000000
>[    0.399333] nouveau T[   VBIOS][0000:01:00.0] 0x9abe[ ]: 	}
>[    0.399334] nouveau T[   VBIOS][0000:01:00.0] 0x9abe[ ]: 	R[0x111d94] = {
>[    0.399334] nouveau T[   VBIOS][0000:01:00.0] 0x9abe[ ]: 		0x00000000
>[    0.399335] nouveau T[   VBIOS][0000:01:00.0] 0x9ac2[ ]: 		0x30303030
>[    0.399336] nouveau T[   VBIOS][0000:01:00.0] 0x9ac6[ ]: 		0x1a1a1a1a *
>[    0.399337] nouveau T[   VBIOS][0000:01:00.0] 0x9aca[ ]: 		0x00000000
>[    0.399338] nouveau T[   VBIOS][0000:01:00.0] 0x9ace[ ]: 		0x1a1a1a1a
>[    0.399338] nouveau T[   VBIOS][0000:01:00.0] 0x9ad2[ ]: 		0x20202020
>[    0.399339] nouveau T[   VBIOS][0000:01:00.0] 0x9ad6[ ]: 		0x00000000
>[    0.399340] nouveau T[   VBIOS][0000:01:00.0] 0x9ada[ ]: 		0x00000000
>[    0.399341] nouveau T[   VBIOS][0000:01:00.0] 0x9ade[ ]: 	}
>[    0.399342] nouveau T[   VBIOS][0000:01:00.0] 0x9ade[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011ed98] 0x04 0x06
>[    0.399342] nouveau T[   VBIOS][0000:01:00.0] 0x9ae5[ ]: 	R[0x11ed98] = {
>[    0.399343] nouveau T[   VBIOS][0000:01:00.0] 0x9ae5[ ]: 		0x22222222
>[    0.399344] nouveau T[   VBIOS][0000:01:00.0] 0x9ae9[ ]: 		0x11111111
>[    0.399345] nouveau T[   VBIOS][0000:01:00.0] 0x9aed[ ]: 		0x22222222 *
>[    0.399346] nouveau T[   VBIOS][0000:01:00.0] 0x9af1[ ]: 		0x22222222
>[    0.399346] nouveau T[   VBIOS][0000:01:00.0] 0x9af5[ ]: 		0x11111111
>[    0.399347] nouveau T[   VBIOS][0000:01:00.0] 0x9af9[ ]: 		0x11111111
>[    0.399348] nouveau T[   VBIOS][0000:01:00.0] 0x9afd[ ]: 		0x22222222
>[    0.399349] nouveau T[   VBIOS][0000:01:00.0] 0x9b01[ ]: 		0x22222222
>[    0.399349] nouveau T[   VBIOS][0000:01:00.0] 0x9b05[ ]: 	}
>[    0.399350] nouveau T[   VBIOS][0000:01:00.0] 0x9b05[ ]: 	R[0x11ed9c] = {
>[    0.399351] nouveau T[   VBIOS][0000:01:00.0] 0x9b05[ ]: 		0x22222222
>[    0.399352] nouveau T[   VBIOS][0000:01:00.0] 0x9b09[ ]: 		0x11111111
>[    0.399353] nouveau T[   VBIOS][0000:01:00.0] 0x9b0d[ ]: 		0x22222222 *
>[    0.399353] nouveau T[   VBIOS][0000:01:00.0] 0x9b11[ ]: 		0x22222222
>[    0.399354] nouveau T[   VBIOS][0000:01:00.0] 0x9b15[ ]: 		0x11111111
>[    0.399355] nouveau T[   VBIOS][0000:01:00.0] 0x9b19[ ]: 		0x11111111
>[    0.399356] nouveau T[   VBIOS][0000:01:00.0] 0x9b1d[ ]: 		0x22222222
>[    0.399356] nouveau T[   VBIOS][0000:01:00.0] 0x9b21[ ]: 		0x22222222
>[    0.399357] nouveau T[   VBIOS][0000:01:00.0] 0x9b25[ ]: 	}
>[    0.399358] nouveau T[   VBIOS][0000:01:00.0] 0x9b25[ ]: 	R[0x11eda0] = {
>[    0.399359] nouveau T[   VBIOS][0000:01:00.0] 0x9b25[ ]: 		0x00000222
>[    0.399360] nouveau T[   VBIOS][0000:01:00.0] 0x9b29[ ]: 		0x00000111
>[    0.399360] nouveau T[   VBIOS][0000:01:00.0] 0x9b2d[ ]: 		0x00000222 *
>[    0.399361] nouveau T[   VBIOS][0000:01:00.0] 0x9b31[ ]: 		0x00000222
>[    0.399362] nouveau T[   VBIOS][0000:01:00.0] 0x9b35[ ]: 		0x00000111
>[    0.399363] nouveau T[   VBIOS][0000:01:00.0] 0x9b39[ ]: 		0x00000111
>[    0.399363] nouveau T[   VBIOS][0000:01:00.0] 0x9b3d[ ]: 		0x00000222
>[    0.399364] nouveau T[   VBIOS][0000:01:00.0] 0x9b41[ ]: 		0x00000222
>[    0.399365] nouveau T[   VBIOS][0000:01:00.0] 0x9b45[ ]: 	}
>[    0.399366] nouveau T[   VBIOS][0000:01:00.0] 0x9b45[ ]: 	R[0x11eda4] = {
>[    0.399367] nouveau T[   VBIOS][0000:01:00.0] 0x9b45[ ]: 		0x22222222
>[    0.399367] nouveau T[   VBIOS][0000:01:00.0] 0x9b49[ ]: 		0x11111111
>[    0.399368] nouveau T[   VBIOS][0000:01:00.0] 0x9b4d[ ]: 		0x22222222 *
>[    0.399369] nouveau T[   VBIOS][0000:01:00.0] 0x9b51[ ]: 		0x22222222
>[    0.399370] nouveau T[   VBIOS][0000:01:00.0] 0x9b55[ ]: 		0x11111111
>[    0.399370] nouveau T[   VBIOS][0000:01:00.0] 0x9b59[ ]: 		0x11111111
>[    0.399371] nouveau T[   VBIOS][0000:01:00.0] 0x9b5d[ ]: 		0x22222222
>[    0.399372] nouveau T[   VBIOS][0000:01:00.0] 0x9b61[ ]: 		0x22222222
>[    0.399373] nouveau T[   VBIOS][0000:01:00.0] 0x9b65[ ]: 	}
>[    0.399374] nouveau T[   VBIOS][0000:01:00.0] 0x9b65[ ]: 	R[0x11eda8] = {
>[    0.399374] nouveau T[   VBIOS][0000:01:00.0] 0x9b65[ ]: 		0x22222222
>[    0.399375] nouveau T[   VBIOS][0000:01:00.0] 0x9b69[ ]: 		0x11111111
>[    0.399376] nouveau T[   VBIOS][0000:01:00.0] 0x9b6d[ ]: 		0x22222222 *
>[    0.399377] nouveau T[   VBIOS][0000:01:00.0] 0x9b71[ ]: 		0x22222222
>[    0.399378] nouveau T[   VBIOS][0000:01:00.0] 0x9b75[ ]: 		0x11111111
>[    0.399378] nouveau T[   VBIOS][0000:01:00.0] 0x9b79[ ]: 		0x11111111
>[    0.399379] nouveau T[   VBIOS][0000:01:00.0] 0x9b7d[ ]: 		0x22222222
>[    0.399380] nouveau T[   VBIOS][0000:01:00.0] 0x9b81[ ]: 		0x22222222
>[    0.399381] nouveau T[   VBIOS][0000:01:00.0] 0x9b85[ ]: 	}
>[    0.399381] nouveau T[   VBIOS][0000:01:00.0] 0x9b85[ ]: 	R[0x11edac] = {
>[    0.399382] nouveau T[   VBIOS][0000:01:00.0] 0x9b85[ ]: 		0x00000222
>[    0.399383] nouveau T[   VBIOS][0000:01:00.0] 0x9b89[ ]: 		0x00000111
>[    0.399384] nouveau T[   VBIOS][0000:01:00.0] 0x9b8d[ ]: 		0x00000222 *
>[    0.399385] nouveau T[   VBIOS][0000:01:00.0] 0x9b91[ ]: 		0x00000222
>[    0.399385] nouveau T[   VBIOS][0000:01:00.0] 0x9b95[ ]: 		0x00000111
>[    0.399386] nouveau T[   VBIOS][0000:01:00.0] 0x9b99[ ]: 		0x00000111
>[    0.399387] nouveau T[   VBIOS][0000:01:00.0] 0x9b9d[ ]: 		0x00000222
>[    0.399388] nouveau T[   VBIOS][0000:01:00.0] 0x9ba1[ ]: 		0x00000222
>[    0.399388] nouveau T[   VBIOS][0000:01:00.0] 0x9ba5[ ]: 	}
>[    0.399389] nouveau T[   VBIOS][0000:01:00.0] 0x9ba5[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e694] 0x04 0x03
>[    0.399390] nouveau T[   VBIOS][0000:01:00.0] 0x9bac[ ]: 	R[0x11e694] = {
>[    0.399391] nouveau T[   VBIOS][0000:01:00.0] 0x9bac[ ]: 		0x06050605
>[    0.399392] nouveau T[   VBIOS][0000:01:00.0] 0x9bb0[ ]: 		0x06050605
>[    0.399393] nouveau T[   VBIOS][0000:01:00.0] 0x9bb4[ ]: 		0x06050605 *
>[    0.399393] nouveau T[   VBIOS][0000:01:00.0] 0x9bb8[ ]: 		0x06050605
>[    0.399394] nouveau T[   VBIOS][0000:01:00.0] 0x9bbc[ ]: 		0x06080608
>[    0.399395] nouveau T[   VBIOS][0000:01:00.0] 0x9bc0[ ]: 		0x060c060c
>[    0.399396] nouveau T[   VBIOS][0000:01:00.0] 0x9bc4[ ]: 		0x06050605
>[    0.399396] nouveau T[   VBIOS][0000:01:00.0] 0x9bc8[ ]: 		0x06050605
>[    0.399397] nouveau T[   VBIOS][0000:01:00.0] 0x9bcc[ ]: 	}
>[    0.399398] nouveau T[   VBIOS][0000:01:00.0] 0x9bcc[ ]: 	R[0x11e698] = {
>[    0.399399] nouveau T[   VBIOS][0000:01:00.0] 0x9bcc[ ]: 		0x06060606
>[    0.399400] nouveau T[   VBIOS][0000:01:00.0] 0x9bd0[ ]: 		0x06060606
>[    0.399400] nouveau T[   VBIOS][0000:01:00.0] 0x9bd4[ ]: 		0x06060606 *
>[    0.399401] nouveau T[   VBIOS][0000:01:00.0] 0x9bd8[ ]: 		0x06060606
>[    0.399402] nouveau T[   VBIOS][0000:01:00.0] 0x9bdc[ ]: 		0x06060606
>[    0.399403] nouveau T[   VBIOS][0000:01:00.0] 0x9be0[ ]: 		0x06060606
>[    0.399404] nouveau T[   VBIOS][0000:01:00.0] 0x9be4[ ]: 		0x06060606
>[    0.399404] nouveau T[   VBIOS][0000:01:00.0] 0x9be8[ ]: 		0x06060606
>[    0.399405] nouveau T[   VBIOS][0000:01:00.0] 0x9bec[ ]: 	}
>[    0.399406] nouveau T[   VBIOS][0000:01:00.0] 0x9bec[ ]: 	R[0x11e69c] = {
>[    0.399407] nouveau T[   VBIOS][0000:01:00.0] 0x9bec[ ]: 		0x06060606
>[    0.399407] nouveau T[   VBIOS][0000:01:00.0] 0x9bf0[ ]: 		0x06060606
>[    0.399408] nouveau T[   VBIOS][0000:01:00.0] 0x9bf4[ ]: 		0x06060606 *
>[    0.399409] nouveau T[   VBIOS][0000:01:00.0] 0x9bf8[ ]: 		0x06060606
>[    0.399410] nouveau T[   VBIOS][0000:01:00.0] 0x9bfc[ ]: 		0x06060606
>[    0.399411] nouveau T[   VBIOS][0000:01:00.0] 0x9c00[ ]: 		0x06060606
>[    0.399411] nouveau T[   VBIOS][0000:01:00.0] 0x9c04[ ]: 		0x06060606
>[    0.399412] nouveau T[   VBIOS][0000:01:00.0] 0x9c08[ ]: 		0x06060606
>[    0.399413] nouveau T[   VBIOS][0000:01:00.0] 0x9c0c[ ]: 	}
>[    0.399414] nouveau T[   VBIOS][0000:01:00.0] 0x9c0c[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e650] 0x04 0x01
>[    0.399415] nouveau T[   VBIOS][0000:01:00.0] 0x9c13[ ]: 	R[0x11e650] = {
>[    0.399415] nouveau T[   VBIOS][0000:01:00.0] 0x9c13[ ]: 		0x870001b0
>[    0.399416] nouveau T[   VBIOS][0000:01:00.0] 0x9c17[ ]: 		0x870001b0
>[    0.399417] nouveau T[   VBIOS][0000:01:00.0] 0x9c1b[ ]: 		0x870001b0 *
>[    0.399418] nouveau T[   VBIOS][0000:01:00.0] 0x9c1f[ ]: 		0x870001b0
>[    0.399419] nouveau T[   VBIOS][0000:01:00.0] 0x9c23[ ]: 		0x870001b0
>[    0.399419] nouveau T[   VBIOS][0000:01:00.0] 0x9c27[ ]: 		0x870001b0
>[    0.399420] nouveau T[   VBIOS][0000:01:00.0] 0x9c2b[ ]: 		0x870001b0
>[    0.399421] nouveau T[   VBIOS][0000:01:00.0] 0x9c2f[ ]: 		0x870001b0
>[    0.399422] nouveau T[   VBIOS][0000:01:00.0] 0x9c33[ ]: 	}
>[    0.399423] nouveau T[   VBIOS][0000:01:00.0] 0x9c33[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e66c] 0x04 0x01
>[    0.399423] nouveau T[   VBIOS][0000:01:00.0] 0x9c3a[ ]: 	R[0x11e66c] = {
>[    0.399424] nouveau T[   VBIOS][0000:01:00.0] 0x9c3a[ ]: 		0x000001b0
>[    0.399425] nouveau T[   VBIOS][0000:01:00.0] 0x9c3e[ ]: 		0x000001b0
>[    0.399426] nouveau T[   VBIOS][0000:01:00.0] 0x9c42[ ]: 		0x000001b0 *
>[    0.399427] nouveau T[   VBIOS][0000:01:00.0] 0x9c46[ ]: 		0x000001bf
>[    0.399427] nouveau T[   VBIOS][0000:01:00.0] 0x9c4a[ ]: 		0x000001b0
>[    0.399428] nouveau T[   VBIOS][0000:01:00.0] 0x9c4e[ ]: 		0x000001b0
>[    0.399429] nouveau T[   VBIOS][0000:01:00.0] 0x9c52[ ]: 		0x000001b0
>[    0.399430] nouveau T[   VBIOS][0000:01:00.0] 0x9c56[ ]: 		0x000001b0
>[    0.399430] nouveau T[   VBIOS][0000:01:00.0] 0x9c5a[ ]: 	}
>[    0.399431] nouveau T[   VBIOS][0000:01:00.0] 0x9c5a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e604] 0x04 0x01
>[    0.399432] nouveau T[   VBIOS][0000:01:00.0] 0x9c61[ ]: 	R[0x11e604] = {
>[    0.399433] nouveau T[   VBIOS][0000:01:00.0] 0x9c61[ ]: 		0x70000200
>[    0.399434] nouveau T[   VBIOS][0000:01:00.0] 0x9c65[ ]: 		0x70000200
>[    0.399435] nouveau T[   VBIOS][0000:01:00.0] 0x9c69[ ]: 		0x70000200 *
>[    0.399435] nouveau T[   VBIOS][0000:01:00.0] 0x9c6d[ ]: 		0x70000200
>[    0.399436] nouveau T[   VBIOS][0000:01:00.0] 0x9c71[ ]: 		0x70000200
>[    0.399437] nouveau T[   VBIOS][0000:01:00.0] 0x9c75[ ]: 		0x70000200
>[    0.399438] nouveau T[   VBIOS][0000:01:00.0] 0x9c79[ ]: 		0x70000000
>[    0.399438] nouveau T[   VBIOS][0000:01:00.0] 0x9c7d[ ]: 		0x70000000
>[    0.399439] nouveau T[   VBIOS][0000:01:00.0] 0x9c81[ ]: 	}
>[    0.399440] nouveau T[   VBIOS][0000:01:00.0] 0x9c81[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e830] 0x04 0x01
>[    0.399441] nouveau T[   VBIOS][0000:01:00.0] 0x9c88[ ]: 	R[0x11e830] = {
>[    0.399442] nouveau T[   VBIOS][0000:01:00.0] 0x9c88[ ]: 		0x00271011
>[    0.399443] nouveau T[   VBIOS][0000:01:00.0] 0x9c8c[ ]: 		0x00271011
>[    0.399443] nouveau T[   VBIOS][0000:01:00.0] 0x9c90[ ]: 		0x00271011 *
>[    0.399444] nouveau T[   VBIOS][0000:01:00.0] 0x9c94[ ]: 		0x00271011
>[    0.399445] nouveau T[   VBIOS][0000:01:00.0] 0x9c98[ ]: 		0x00271011
>[    0.399446] nouveau T[   VBIOS][0000:01:00.0] 0x9c9c[ ]: 		0x00271011
>[    0.399447] nouveau T[   VBIOS][0000:01:00.0] 0x9ca0[ ]: 		0x00276011
>[    0.399447] nouveau T[   VBIOS][0000:01:00.0] 0x9ca4[ ]: 		0x00276011
>[    0.399448] nouveau T[   VBIOS][0000:01:00.0] 0x9ca8[ ]: 	}
>[    0.399449] nouveau T[   VBIOS][0000:01:00.0] 0x9ca8[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e800] 0x04 0x01
>[    0.399450] nouveau T[   VBIOS][0000:01:00.0] 0x9caf[ ]: 	R[0x11e800] = {
>[    0.399451] nouveau T[   VBIOS][0000:01:00.0] 0x9caf[ ]: 		0x00000004
>[    0.399451] nouveau T[   VBIOS][0000:01:00.0] 0x9cb3[ ]: 		0x00000004
>[    0.399452] nouveau T[   VBIOS][0000:01:00.0] 0x9cb7[ ]: 		0x00000004 *
>[    0.399453] nouveau T[   VBIOS][0000:01:00.0] 0x9cbb[ ]: 		0x00000004
>[    0.399454] nouveau T[   VBIOS][0000:01:00.0] 0x9cbf[ ]: 		0x00000004
>[    0.399455] nouveau T[   VBIOS][0000:01:00.0] 0x9cc3[ ]: 		0x00000004
>[    0.399455] nouveau T[   VBIOS][0000:01:00.0] 0x9cc7[ ]: 		0x00000014
>[    0.399456] nouveau T[   VBIOS][0000:01:00.0] 0x9ccb[ ]: 		0x00000014
>[    0.399457] nouveau T[   VBIOS][0000:01:00.0] 0x9ccf[ ]: 	}
>[    0.399458] nouveau T[   VBIOS][0000:01:00.0] 0x9ccf[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e594] 0x04 0x01
>[    0.399459] nouveau T[   VBIOS][0000:01:00.0] 0x9cd6[ ]: 	R[0x11e594] = {
>[    0.399460] nouveau T[   VBIOS][0000:01:00.0] 0x9cd6[ ]: 		0x00000101
>[    0.399460] nouveau T[   VBIOS][0000:01:00.0] 0x9cda[ ]: 		0x00000101
>[    0.399461] nouveau T[   VBIOS][0000:01:00.0] 0x9cde[ ]: 		0x00000101 *
>[    0.399462] nouveau T[   VBIOS][0000:01:00.0] 0x9ce2[ ]: 		0x00000101
>[    0.399463] nouveau T[   VBIOS][0000:01:00.0] 0x9ce6[ ]: 		0x00000101
>[    0.399463] nouveau T[   VBIOS][0000:01:00.0] 0x9cea[ ]: 		0x00000101
>[    0.399464] nouveau T[   VBIOS][0000:01:00.0] 0x9cee[ ]: 		0x00000101
>[    0.399465] nouveau T[   VBIOS][0000:01:00.0] 0x9cf2[ ]: 		0x00000101
>[    0.399466] nouveau T[   VBIOS][0000:01:00.0] 0x9cf6[ ]: 	}
>[    0.399467] nouveau T[   VBIOS][0000:01:00.0] 0x9cf6[ ]: NV_REG	R[0x11e65c] &= 0x000000f0 |= 0x00000000
>[    0.399468] nouveau T[   VBIOS][0000:01:00.0] 0x9d03[ ]: SUB_DIRECT	0xac87
>[    0.399469] nouveau T[   VBIOS][0000:01:00.0] 0x9d06[ ]: NV_REG	R[0x11e65c] &= 0x0000000f |= 0x00000000
>[    0.399470] nouveau T[   VBIOS][0000:01:00.0] 0x9d13[ ]: ZM_REG	R[0x11e508] = 0x8000000a
>[    0.399471] nouveau T[   VBIOS][0000:01:00.0] 0x9d1c[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011ea20] 0x04 0x28
>[    0.399471] nouveau T[   VBIOS][0000:01:00.0] 0x9d23[ ]: 	R[0x11ea20] = {
>[    0.399472] nouveau T[   VBIOS][0000:01:00.0] 0x9d23[ ]: 		0x88888888
>[    0.399473] nouveau T[   VBIOS][0000:01:00.0] 0x9d27[ ]: 		0x88888888
>[    0.399474] nouveau T[   VBIOS][0000:01:00.0] 0x9d2b[ ]: 		0x88888888 *
>[    0.399475] nouveau T[   VBIOS][0000:01:00.0] 0x9d2f[ ]: 		0x88888888
>[    0.399476] nouveau T[   VBIOS][0000:01:00.0] 0x9d33[ ]: 		0x88888888
>[    0.399476] nouveau T[   VBIOS][0000:01:00.0] 0x9d37[ ]: 		0x88888888
>[    0.399477] nouveau T[   VBIOS][0000:01:00.0] 0x9d3b[ ]: 		0x88888888
>[    0.399478] nouveau T[   VBIOS][0000:01:00.0] 0x9d3f[ ]: 		0x88888888
>[    0.399479] nouveau T[   VBIOS][0000:01:00.0] 0x9d43[ ]: 	}
>[    0.399479] nouveau T[   VBIOS][0000:01:00.0] 0x9d43[ ]: 	R[0x11ea24] = {
>[    0.399480] nouveau T[   VBIOS][0000:01:00.0] 0x9d43[ ]: 		0x88888888
>[    0.399481] nouveau T[   VBIOS][0000:01:00.0] 0x9d47[ ]: 		0x88888888
>[    0.399482] nouveau T[   VBIOS][0000:01:00.0] 0x9d4b[ ]: 		0x88888888 *
>[    0.399483] nouveau T[   VBIOS][0000:01:00.0] 0x9d4f[ ]: 		0x88888888
>[    0.399483] nouveau T[   VBIOS][0000:01:00.0] 0x9d53[ ]: 		0x88888888
>[    0.399484] nouveau T[   VBIOS][0000:01:00.0] 0x9d57[ ]: 		0x88888888
>[    0.399485] nouveau T[   VBIOS][0000:01:00.0] 0x9d5b[ ]: 		0x88888888
>[    0.399486] nouveau T[   VBIOS][0000:01:00.0] 0x9d5f[ ]: 		0x88888888
>[    0.399486] nouveau T[   VBIOS][0000:01:00.0] 0x9d63[ ]: 	}
>[    0.399487] nouveau T[   VBIOS][0000:01:00.0] 0x9d63[ ]: 	R[0x11ea28] = {
>[    0.399488] nouveau T[   VBIOS][0000:01:00.0] 0x9d63[ ]: 		0x88888888
>[    0.399489] nouveau T[   VBIOS][0000:01:00.0] 0x9d67[ ]: 		0x88888888
>[    0.399490] nouveau T[   VBIOS][0000:01:00.0] 0x9d6b[ ]: 		0x88888888 *
>[    0.399490] nouveau T[   VBIOS][0000:01:00.0] 0x9d6f[ ]: 		0x88888888
>[    0.399491] nouveau T[   VBIOS][0000:01:00.0] 0x9d73[ ]: 		0x88888888
>[    0.399492] nouveau T[   VBIOS][0000:01:00.0] 0x9d77[ ]: 		0x88888888
>[    0.399493] nouveau T[   VBIOS][0000:01:00.0] 0x9d7b[ ]: 		0x88888888
>[    0.399493] nouveau T[   VBIOS][0000:01:00.0] 0x9d7f[ ]: 		0x88888888
>[    0.399494] nouveau T[   VBIOS][0000:01:00.0] 0x9d83[ ]: 	}
>[    0.399495] nouveau T[   VBIOS][0000:01:00.0] 0x9d83[ ]: 	R[0x11ea2c] = {
>[    0.399496] nouveau T[   VBIOS][0000:01:00.0] 0x9d83[ ]: 		0x88888888
>[    0.399497] nouveau T[   VBIOS][0000:01:00.0] 0x9d87[ ]: 		0x88888888
>[    0.399497] nouveau T[   VBIOS][0000:01:00.0] 0x9d8b[ ]: 		0x88888888 *
>[    0.399498] nouveau T[   VBIOS][0000:01:00.0] 0x9d8f[ ]: 		0x88888888
>[    0.399499] nouveau T[   VBIOS][0000:01:00.0] 0x9d93[ ]: 		0x88888888
>[    0.399500] nouveau T[   VBIOS][0000:01:00.0] 0x9d97[ ]: 		0x88888888
>[    0.399501] nouveau T[   VBIOS][0000:01:00.0] 0x9d9b[ ]: 		0x88888888
>[    0.399501] nouveau T[   VBIOS][0000:01:00.0] 0x9d9f[ ]: 		0x88888888
>[    0.399502] nouveau T[   VBIOS][0000:01:00.0] 0x9da3[ ]: 	}
>[    0.399503] nouveau T[   VBIOS][0000:01:00.0] 0x9da3[ ]: 	R[0x11ea30] = {
>[    0.399504] nouveau T[   VBIOS][0000:01:00.0] 0x9da3[ ]: 		0x88888888
>[    0.399504] nouveau T[   VBIOS][0000:01:00.0] 0x9da7[ ]: 		0x88888888
>[    0.399505] nouveau T[   VBIOS][0000:01:00.0] 0x9dab[ ]: 		0x88888888 *
>[    0.399506] nouveau T[   VBIOS][0000:01:00.0] 0x9daf[ ]: 		0x88888888
>[    0.399507] nouveau T[   VBIOS][0000:01:00.0] 0x9db3[ ]: 		0x88888888
>[    0.399508] nouveau T[   VBIOS][0000:01:00.0] 0x9db7[ ]: 		0x88888888
>[    0.399508] nouveau T[   VBIOS][0000:01:00.0] 0x9dbb[ ]: 		0x88888888
>[    0.399509] nouveau T[   VBIOS][0000:01:00.0] 0x9dbf[ ]: 		0x88888888
>[    0.399510] nouveau T[   VBIOS][0000:01:00.0] 0x9dc3[ ]: 	}
>[    0.399511] nouveau T[   VBIOS][0000:01:00.0] 0x9dc3[ ]: 	R[0x11ea34] = {
>[    0.399511] nouveau T[   VBIOS][0000:01:00.0] 0x9dc3[ ]: 		0x88888888
>[    0.399512] nouveau T[   VBIOS][0000:01:00.0] 0x9dc7[ ]: 		0x88888888
>[    0.399513] nouveau T[   VBIOS][0000:01:00.0] 0x9dcb[ ]: 		0x88888888 *
>[    0.399514] nouveau T[   VBIOS][0000:01:00.0] 0x9dcf[ ]: 		0x88888888
>[    0.399515] nouveau T[   VBIOS][0000:01:00.0] 0x9dd3[ ]: 		0x88888888
>[    0.399515] nouveau T[   VBIOS][0000:01:00.0] 0x9dd7[ ]: 		0x88888888
>[    0.399516] nouveau T[   VBIOS][0000:01:00.0] 0x9ddb[ ]: 		0x88888888
>[    0.399517] nouveau T[   VBIOS][0000:01:00.0] 0x9ddf[ ]: 		0x88888888
>[    0.399518] nouveau T[   VBIOS][0000:01:00.0] 0x9de3[ ]: 	}
>[    0.399518] nouveau T[   VBIOS][0000:01:00.0] 0x9de3[ ]: 	R[0x11ea38] = {
>[    0.399519] nouveau T[   VBIOS][0000:01:00.0] 0x9de3[ ]: 		0x88888888
>[    0.399520] nouveau T[   VBIOS][0000:01:00.0] 0x9de7[ ]: 		0x88888888
>[    0.399521] nouveau T[   VBIOS][0000:01:00.0] 0x9deb[ ]: 		0x88888888 *
>[    0.399522] nouveau T[   VBIOS][0000:01:00.0] 0x9def[ ]: 		0x88888888
>[    0.399522] nouveau T[   VBIOS][0000:01:00.0] 0x9df3[ ]: 		0x88888888
>[    0.399523] nouveau T[   VBIOS][0000:01:00.0] 0x9df7[ ]: 		0x88888888
>[    0.399524] nouveau T[   VBIOS][0000:01:00.0] 0x9dfb[ ]: 		0x88888888
>[    0.399525] nouveau T[   VBIOS][0000:01:00.0] 0x9dff[ ]: 		0x88888888
>[    0.399525] nouveau T[   VBIOS][0000:01:00.0] 0x9e03[ ]: 	}
>[    0.399526] nouveau T[   VBIOS][0000:01:00.0] 0x9e03[ ]: 	R[0x11ea3c] = {
>[    0.399527] nouveau T[   VBIOS][0000:01:00.0] 0x9e03[ ]: 		0x88888888
>[    0.399528] nouveau T[   VBIOS][0000:01:00.0] 0x9e07[ ]: 		0x88888888
>[    0.399529] nouveau T[   VBIOS][0000:01:00.0] 0x9e0b[ ]: 		0x88888888 *
>[    0.399529] nouveau T[   VBIOS][0000:01:00.0] 0x9e0f[ ]: 		0x88888888
>[    0.399530] nouveau T[   VBIOS][0000:01:00.0] 0x9e13[ ]: 		0x88888888
>[    0.399531] nouveau T[   VBIOS][0000:01:00.0] 0x9e17[ ]: 		0x88888888
>[    0.399532] nouveau T[   VBIOS][0000:01:00.0] 0x9e1b[ ]: 		0x88888888
>[    0.399532] nouveau T[   VBIOS][0000:01:00.0] 0x9e1f[ ]: 		0x88888888
>[    0.399533] nouveau T[   VBIOS][0000:01:00.0] 0x9e23[ ]: 	}
>[    0.399534] nouveau T[   VBIOS][0000:01:00.0] 0x9e23[ ]: 	R[0x11ea40] = {
>[    0.399535] nouveau T[   VBIOS][0000:01:00.0] 0x9e23[ ]: 		0x88888888
>[    0.399536] nouveau T[   VBIOS][0000:01:00.0] 0x9e27[ ]: 		0x88888888
>[    0.399536] nouveau T[   VBIOS][0000:01:00.0] 0x9e2b[ ]: 		0x88888888 *
>[    0.399537] nouveau T[   VBIOS][0000:01:00.0] 0x9e2f[ ]: 		0x88888888
>[    0.399538] nouveau T[   VBIOS][0000:01:00.0] 0x9e33[ ]: 		0x88888888
>[    0.399539] nouveau T[   VBIOS][0000:01:00.0] 0x9e37[ ]: 		0x88888888
>[    0.399539] nouveau T[   VBIOS][0000:01:00.0] 0x9e3b[ ]: 		0x88888888
>[    0.399540] nouveau T[   VBIOS][0000:01:00.0] 0x9e3f[ ]: 		0x88888888
>[    0.399541] nouveau T[   VBIOS][0000:01:00.0] 0x9e43[ ]: 	}
>[    0.399542] nouveau T[   VBIOS][0000:01:00.0] 0x9e43[ ]: 	R[0x11ea44] = {
>[    0.399543] nouveau T[   VBIOS][0000:01:00.0] 0x9e43[ ]: 		0x88888888
>[    0.399543] nouveau T[   VBIOS][0000:01:00.0] 0x9e47[ ]: 		0x88888888
>[    0.399544] nouveau T[   VBIOS][0000:01:00.0] 0x9e4b[ ]: 		0x88888888 *
>[    0.399545] nouveau T[   VBIOS][0000:01:00.0] 0x9e4f[ ]: 		0x88888888
>[    0.399546] nouveau T[   VBIOS][0000:01:00.0] 0x9e53[ ]: 		0x88888888
>[    0.399546] nouveau T[   VBIOS][0000:01:00.0] 0x9e57[ ]: 		0x88888888
>[    0.399547] nouveau T[   VBIOS][0000:01:00.0] 0x9e5b[ ]: 		0x88888888
>[    0.399548] nouveau T[   VBIOS][0000:01:00.0] 0x9e5f[ ]: 		0x88888888
>[    0.399549] nouveau T[   VBIOS][0000:01:00.0] 0x9e63[ ]: 	}
>[    0.399550] nouveau T[   VBIOS][0000:01:00.0] 0x9e63[ ]: 	R[0x11ea48] = {
>[    0.399550] nouveau T[   VBIOS][0000:01:00.0] 0x9e63[ ]: 		0x88888888
>[    0.399551] nouveau T[   VBIOS][0000:01:00.0] 0x9e67[ ]: 		0x88888888
>[    0.399552] nouveau T[   VBIOS][0000:01:00.0] 0x9e6b[ ]: 		0x88888888 *
>[    0.399553] nouveau T[   VBIOS][0000:01:00.0] 0x9e6f[ ]: 		0x88888888
>[    0.399553] nouveau T[   VBIOS][0000:01:00.0] 0x9e73[ ]: 		0x88888888
>[    0.399554] nouveau T[   VBIOS][0000:01:00.0] 0x9e77[ ]: 		0x88888888
>[    0.399555] nouveau T[   VBIOS][0000:01:00.0] 0x9e7b[ ]: 		0x88888888
>[    0.399556] nouveau T[   VBIOS][0000:01:00.0] 0x9e7f[ ]: 		0x88888888
>[    0.399556] nouveau T[   VBIOS][0000:01:00.0] 0x9e83[ ]: 	}
>[    0.399557] nouveau T[   VBIOS][0000:01:00.0] 0x9e83[ ]: 	R[0x11ea4c] = {
>[    0.399558] nouveau T[   VBIOS][0000:01:00.0] 0x9e83[ ]: 		0x88888888
>[    0.399559] nouveau T[   VBIOS][0000:01:00.0] 0x9e87[ ]: 		0x88888888
>[    0.399560] nouveau T[   VBIOS][0000:01:00.0] 0x9e8b[ ]: 		0x88888888 *
>[    0.399560] nouveau T[   VBIOS][0000:01:00.0] 0x9e8f[ ]: 		0x88888888
>[    0.399561] nouveau T[   VBIOS][0000:01:00.0] 0x9e93[ ]: 		0x88888888
>[    0.399562] nouveau T[   VBIOS][0000:01:00.0] 0x9e97[ ]: 		0x88888888
>[    0.399563] nouveau T[   VBIOS][0000:01:00.0] 0x9e9b[ ]: 		0x88888888
>[    0.399563] nouveau T[   VBIOS][0000:01:00.0] 0x9e9f[ ]: 		0x88888888
>[    0.399564] nouveau T[   VBIOS][0000:01:00.0] 0x9ea3[ ]: 	}
>[    0.399565] nouveau T[   VBIOS][0000:01:00.0] 0x9ea3[ ]: 	R[0x11ea50] = {
>[    0.399566] nouveau T[   VBIOS][0000:01:00.0] 0x9ea3[ ]: 		0x88888888
>[    0.399567] nouveau T[   VBIOS][0000:01:00.0] 0x9ea7[ ]: 		0x88888888
>[    0.399567] nouveau T[   VBIOS][0000:01:00.0] 0x9eab[ ]: 		0x88888888 *
>[    0.399568] nouveau T[   VBIOS][0000:01:00.0] 0x9eaf[ ]: 		0x88888888
>[    0.399569] nouveau T[   VBIOS][0000:01:00.0] 0x9eb3[ ]: 		0x88888888
>[    0.399570] nouveau T[   VBIOS][0000:01:00.0] 0x9eb7[ ]: 		0x88888888
>[    0.399571] nouveau T[   VBIOS][0000:01:00.0] 0x9ebb[ ]: 		0x88888888
>[    0.399571] nouveau T[   VBIOS][0000:01:00.0] 0x9ebf[ ]: 		0x88888888
>[    0.399572] nouveau T[   VBIOS][0000:01:00.0] 0x9ec3[ ]: 	}
>[    0.399573] nouveau T[   VBIOS][0000:01:00.0] 0x9ec3[ ]: 	R[0x11ea54] = {
>[    0.399574] nouveau T[   VBIOS][0000:01:00.0] 0x9ec3[ ]: 		0x88888888
>[    0.399574] nouveau T[   VBIOS][0000:01:00.0] 0x9ec7[ ]: 		0x88888888
>[    0.399575] nouveau T[   VBIOS][0000:01:00.0] 0x9ecb[ ]: 		0x88888888 *
>[    0.399576] nouveau T[   VBIOS][0000:01:00.0] 0x9ecf[ ]: 		0x88888888
>[    0.399577] nouveau T[   VBIOS][0000:01:00.0] 0x9ed3[ ]: 		0x88888888
>[    0.399578] nouveau T[   VBIOS][0000:01:00.0] 0x9ed7[ ]: 		0x88888888
>[    0.399578] nouveau T[   VBIOS][0000:01:00.0] 0x9edb[ ]: 		0x88888888
>[    0.399579] nouveau T[   VBIOS][0000:01:00.0] 0x9edf[ ]: 		0x88888888
>[    0.399580] nouveau T[   VBIOS][0000:01:00.0] 0x9ee3[ ]: 	}
>[    0.399581] nouveau T[   VBIOS][0000:01:00.0] 0x9ee3[ ]: 	R[0x11ea58] = {
>[    0.399581] nouveau T[   VBIOS][0000:01:00.0] 0x9ee3[ ]: 		0x88888888
>[    0.399582] nouveau T[   VBIOS][0000:01:00.0] 0x9ee7[ ]: 		0x88888888
>[    0.399583] nouveau T[   VBIOS][0000:01:00.0] 0x9eeb[ ]: 		0x88888888 *
>[    0.399584] nouveau T[   VBIOS][0000:01:00.0] 0x9eef[ ]: 		0x88888888
>[    0.399585] nouveau T[   VBIOS][0000:01:00.0] 0x9ef3[ ]: 		0x88888888
>[    0.399585] nouveau T[   VBIOS][0000:01:00.0] 0x9ef7[ ]: 		0x88888888
>[    0.399586] nouveau T[   VBIOS][0000:01:00.0] 0x9efb[ ]: 		0x88888888
>[    0.399587] nouveau T[   VBIOS][0000:01:00.0] 0x9eff[ ]: 		0x88888888
>[    0.399588] nouveau T[   VBIOS][0000:01:00.0] 0x9f03[ ]: 	}
>[    0.399588] nouveau T[   VBIOS][0000:01:00.0] 0x9f03[ ]: 	R[0x11ea5c] = {
>[    0.399589] nouveau T[   VBIOS][0000:01:00.0] 0x9f03[ ]: 		0x88888888
>[    0.399590] nouveau T[   VBIOS][0000:01:00.0] 0x9f07[ ]: 		0x88888888
>[    0.399591] nouveau T[   VBIOS][0000:01:00.0] 0x9f0b[ ]: 		0x88888888 *
>[    0.399592] nouveau T[   VBIOS][0000:01:00.0] 0x9f0f[ ]: 		0x88888888
>[    0.399592] nouveau T[   VBIOS][0000:01:00.0] 0x9f13[ ]: 		0x88888888
>[    0.399593] nouveau T[   VBIOS][0000:01:00.0] 0x9f17[ ]: 		0x88888888
>[    0.399594] nouveau T[   VBIOS][0000:01:00.0] 0x9f1b[ ]: 		0x88888888
>[    0.399595] nouveau T[   VBIOS][0000:01:00.0] 0x9f1f[ ]: 		0x88888888
>[    0.399595] nouveau T[   VBIOS][0000:01:00.0] 0x9f23[ ]: 	}
>[    0.399596] nouveau T[   VBIOS][0000:01:00.0] 0x9f23[ ]: 	R[0x11ea60] = {
>[    0.399597] nouveau T[   VBIOS][0000:01:00.0] 0x9f23[ ]: 		0x88888888
>[    0.399598] nouveau T[   VBIOS][0000:01:00.0] 0x9f27[ ]: 		0x88888888
>[    0.399599] nouveau T[   VBIOS][0000:01:00.0] 0x9f2b[ ]: 		0x88888888 *
>[    0.399599] nouveau T[   VBIOS][0000:01:00.0] 0x9f2f[ ]: 		0x88888888
>[    0.399600] nouveau T[   VBIOS][0000:01:00.0] 0x9f33[ ]: 		0x88888888
>[    0.399601] nouveau T[   VBIOS][0000:01:00.0] 0x9f37[ ]: 		0x88888888
>[    0.399602] nouveau T[   VBIOS][0000:01:00.0] 0x9f3b[ ]: 		0x88888888
>[    0.399602] nouveau T[   VBIOS][0000:01:00.0] 0x9f3f[ ]: 		0x88888888
>[    0.399603] nouveau T[   VBIOS][0000:01:00.0] 0x9f43[ ]: 	}
>[    0.399604] nouveau T[   VBIOS][0000:01:00.0] 0x9f43[ ]: 	R[0x11ea64] = {
>[    0.399605] nouveau T[   VBIOS][0000:01:00.0] 0x9f43[ ]: 		0x88888888
>[    0.399606] nouveau T[   VBIOS][0000:01:00.0] 0x9f47[ ]: 		0x88888888
>[    0.399606] nouveau T[   VBIOS][0000:01:00.0] 0x9f4b[ ]: 		0x88888888 *
>[    0.399607] nouveau T[   VBIOS][0000:01:00.0] 0x9f4f[ ]: 		0x88888888
>[    0.399608] nouveau T[   VBIOS][0000:01:00.0] 0x9f53[ ]: 		0x88888888
>[    0.399609] nouveau T[   VBIOS][0000:01:00.0] 0x9f57[ ]: 		0x88888888
>[    0.399609] nouveau T[   VBIOS][0000:01:00.0] 0x9f5b[ ]: 		0x88888888
>[    0.399610] nouveau T[   VBIOS][0000:01:00.0] 0x9f5f[ ]: 		0x88888888
>[    0.399611] nouveau T[   VBIOS][0000:01:00.0] 0x9f63[ ]: 	}
>[    0.399612] nouveau T[   VBIOS][0000:01:00.0] 0x9f63[ ]: 	R[0x11ea68] = {
>[    0.399613] nouveau T[   VBIOS][0000:01:00.0] 0x9f63[ ]: 		0x00008888
>[    0.399613] nouveau T[   VBIOS][0000:01:00.0] 0x9f67[ ]: 		0x00008888
>[    0.399614] nouveau T[   VBIOS][0000:01:00.0] 0x9f6b[ ]: 		0x00008888 *
>[    0.399615] nouveau T[   VBIOS][0000:01:00.0] 0x9f6f[ ]: 		0x00008888
>[    0.399616] nouveau T[   VBIOS][0000:01:00.0] 0x9f73[ ]: 		0x00008888
>[    0.399616] nouveau T[   VBIOS][0000:01:00.0] 0x9f77[ ]: 		0x00008888
>[    0.399617] nouveau T[   VBIOS][0000:01:00.0] 0x9f7b[ ]: 		0x00008888
>[    0.399618] nouveau T[   VBIOS][0000:01:00.0] 0x9f7f[ ]: 		0x00008888
>[    0.399619] nouveau T[   VBIOS][0000:01:00.0] 0x9f83[ ]: 	}
>[    0.399620] nouveau T[   VBIOS][0000:01:00.0] 0x9f83[ ]: 	R[0x11ea6c] = {
>[    0.399620] nouveau T[   VBIOS][0000:01:00.0] 0x9f83[ ]: 		0x00008888
>[    0.399621] nouveau T[   VBIOS][0000:01:00.0] 0x9f87[ ]: 		0x00008888
>[    0.399622] nouveau T[   VBIOS][0000:01:00.0] 0x9f8b[ ]: 		0x00008888 *
>[    0.399623] nouveau T[   VBIOS][0000:01:00.0] 0x9f8f[ ]: 		0x00008888
>[    0.399623] nouveau T[   VBIOS][0000:01:00.0] 0x9f93[ ]: 		0x00008888
>[    0.399624] nouveau T[   VBIOS][0000:01:00.0] 0x9f97[ ]: 		0x00008888
>[    0.399625] nouveau T[   VBIOS][0000:01:00.0] 0x9f9b[ ]: 		0x00008888
>[    0.399626] nouveau T[   VBIOS][0000:01:00.0] 0x9f9f[ ]: 		0x00008888
>[    0.399626] nouveau T[   VBIOS][0000:01:00.0] 0x9fa3[ ]: 	}
>[    0.399627] nouveau T[   VBIOS][0000:01:00.0] 0x9fa3[ ]: 	R[0x11ea70] = {
>[    0.399628] nouveau T[   VBIOS][0000:01:00.0] 0x9fa3[ ]: 		0x00000000
>[    0.399629] nouveau T[   VBIOS][0000:01:00.0] 0x9fa7[ ]: 		0x00000000
>[    0.399630] nouveau T[   VBIOS][0000:01:00.0] 0x9fab[ ]: 		0x00000000 *
>[    0.399630] nouveau T[   VBIOS][0000:01:00.0] 0x9faf[ ]: 		0x00000000
>[    0.399631] nouveau T[   VBIOS][0000:01:00.0] 0x9fb3[ ]: 		0x00000000
>[    0.399632] nouveau T[   VBIOS][0000:01:00.0] 0x9fb7[ ]: 		0x00000000
>[    0.399633] nouveau T[   VBIOS][0000:01:00.0] 0x9fbb[ ]: 		0x00000000
>[    0.399633] nouveau T[   VBIOS][0000:01:00.0] 0x9fbf[ ]: 		0x00000000
>[    0.399634] nouveau T[   VBIOS][0000:01:00.0] 0x9fc3[ ]: 	}
>[    0.399635] nouveau T[   VBIOS][0000:01:00.0] 0x9fc3[ ]: 	R[0x11ea74] = {
>[    0.399636] nouveau T[   VBIOS][0000:01:00.0] 0x9fc3[ ]: 		0x00000000
>[    0.399637] nouveau T[   VBIOS][0000:01:00.0] 0x9fc7[ ]: 		0x00000000
>[    0.399637] nouveau T[   VBIOS][0000:01:00.0] 0x9fcb[ ]: 		0x00000000 *
>[    0.399638] nouveau T[   VBIOS][0000:01:00.0] 0x9fcf[ ]: 		0x00000000
>[    0.399639] nouveau T[   VBIOS][0000:01:00.0] 0x9fd3[ ]: 		0x00000000
>[    0.399640] nouveau T[   VBIOS][0000:01:00.0] 0x9fd7[ ]: 		0x00000000
>[    0.399640] nouveau T[   VBIOS][0000:01:00.0] 0x9fdb[ ]: 		0x00000000
>[    0.399641] nouveau T[   VBIOS][0000:01:00.0] 0x9fdf[ ]: 		0x00000000
>[    0.399642] nouveau T[   VBIOS][0000:01:00.0] 0x9fe3[ ]: 	}
>[    0.399643] nouveau T[   VBIOS][0000:01:00.0] 0x9fe3[ ]: 	R[0x11ea78] = {
>[    0.399643] nouveau T[   VBIOS][0000:01:00.0] 0x9fe3[ ]: 		0x00000000
>[    0.399644] nouveau T[   VBIOS][0000:01:00.0] 0x9fe7[ ]: 		0x00000000
>[    0.399645] nouveau T[   VBIOS][0000:01:00.0] 0x9feb[ ]: 		0x00000000 *
>[    0.399646] nouveau T[   VBIOS][0000:01:00.0] 0x9fef[ ]: 		0x00000000
>[    0.399647] nouveau T[   VBIOS][0000:01:00.0] 0x9ff3[ ]: 		0x00000000
>[    0.399647] nouveau T[   VBIOS][0000:01:00.0] 0x9ff7[ ]: 		0x00000000
>[    0.399648] nouveau T[   VBIOS][0000:01:00.0] 0x9ffb[ ]: 		0x00000000
>[    0.399649] nouveau T[   VBIOS][0000:01:00.0] 0x9fff[ ]: 		0x00000000
>[    0.399650] nouveau T[   VBIOS][0000:01:00.0] 0xa003[ ]: 	}
>[    0.399650] nouveau T[   VBIOS][0000:01:00.0] 0xa003[ ]: 	R[0x11ea7c] = {
>[    0.399651] nouveau T[   VBIOS][0000:01:00.0] 0xa003[ ]: 		0x00000000
>[    0.399652] nouveau T[   VBIOS][0000:01:00.0] 0xa007[ ]: 		0x00000000
>[    0.399653] nouveau T[   VBIOS][0000:01:00.0] 0xa00b[ ]: 		0x00000000 *
>[    0.399653] nouveau T[   VBIOS][0000:01:00.0] 0xa00f[ ]: 		0x00000000
>[    0.399654] nouveau T[   VBIOS][0000:01:00.0] 0xa013[ ]: 		0x00000000
>[    0.399655] nouveau T[   VBIOS][0000:01:00.0] 0xa017[ ]: 		0x00000000
>[    0.399656] nouveau T[   VBIOS][0000:01:00.0] 0xa01b[ ]: 		0x00000000
>[    0.399656] nouveau T[   VBIOS][0000:01:00.0] 0xa01f[ ]: 		0x00000000
>[    0.399657] nouveau T[   VBIOS][0000:01:00.0] 0xa023[ ]: 	}
>[    0.399658] nouveau T[   VBIOS][0000:01:00.0] 0xa023[ ]: 	R[0x11ea80] = {
>[    0.399659] nouveau T[   VBIOS][0000:01:00.0] 0xa023[ ]: 		0x00000000
>[    0.399660] nouveau T[   VBIOS][0000:01:00.0] 0xa027[ ]: 		0x00000000
>[    0.399660] nouveau T[   VBIOS][0000:01:00.0] 0xa02b[ ]: 		0x00000000 *
>[    0.399661] nouveau T[   VBIOS][0000:01:00.0] 0xa02f[ ]: 		0x00000000
>[    0.399662] nouveau T[   VBIOS][0000:01:00.0] 0xa033[ ]: 		0x00000000
>[    0.399663] nouveau T[   VBIOS][0000:01:00.0] 0xa037[ ]: 		0x00000000
>[    0.399663] nouveau T[   VBIOS][0000:01:00.0] 0xa03b[ ]: 		0x00000000
>[    0.399664] nouveau T[   VBIOS][0000:01:00.0] 0xa03f[ ]: 		0x00000000
>[    0.399665] nouveau T[   VBIOS][0000:01:00.0] 0xa043[ ]: 	}
>[    0.399666] nouveau T[   VBIOS][0000:01:00.0] 0xa043[ ]: 	R[0x11ea84] = {
>[    0.399667] nouveau T[   VBIOS][0000:01:00.0] 0xa043[ ]: 		0x00000000
>[    0.399667] nouveau T[   VBIOS][0000:01:00.0] 0xa047[ ]: 		0x00000000
>[    0.399668] nouveau T[   VBIOS][0000:01:00.0] 0xa04b[ ]: 		0x00000000 *
>[    0.399669] nouveau T[   VBIOS][0000:01:00.0] 0xa04f[ ]: 		0x00000000
>[    0.399670] nouveau T[   VBIOS][0000:01:00.0] 0xa053[ ]: 		0x00000000
>[    0.399670] nouveau T[   VBIOS][0000:01:00.0] 0xa057[ ]: 		0x00000000
>[    0.399671] nouveau T[   VBIOS][0000:01:00.0] 0xa05b[ ]: 		0x00000000
>[    0.399672] nouveau T[   VBIOS][0000:01:00.0] 0xa05f[ ]: 		0x00000000
>[    0.399673] nouveau T[   VBIOS][0000:01:00.0] 0xa063[ ]: 	}
>[    0.399673] nouveau T[   VBIOS][0000:01:00.0] 0xa063[ ]: 	R[0x11ea88] = {
>[    0.399674] nouveau T[   VBIOS][0000:01:00.0] 0xa063[ ]: 		0x00000000
>[    0.399675] nouveau T[   VBIOS][0000:01:00.0] 0xa067[ ]: 		0x00000000
>[    0.399676] nouveau T[   VBIOS][0000:01:00.0] 0xa06b[ ]: 		0x00000000 *
>[    0.399677] nouveau T[   VBIOS][0000:01:00.0] 0xa06f[ ]: 		0x00000000
>[    0.399677] nouveau T[   VBIOS][0000:01:00.0] 0xa073[ ]: 		0x00000000
>[    0.399678] nouveau T[   VBIOS][0000:01:00.0] 0xa077[ ]: 		0x00000000
>[    0.399679] nouveau T[   VBIOS][0000:01:00.0] 0xa07b[ ]: 		0x00000000
>[    0.399680] nouveau T[   VBIOS][0000:01:00.0] 0xa07f[ ]: 		0x00000000
>[    0.399680] nouveau T[   VBIOS][0000:01:00.0] 0xa083[ ]: 	}
>[    0.399681] nouveau T[   VBIOS][0000:01:00.0] 0xa083[ ]: 	R[0x11ea8c] = {
>[    0.399682] nouveau T[   VBIOS][0000:01:00.0] 0xa083[ ]: 		0x00000000
>[    0.399683] nouveau T[   VBIOS][0000:01:00.0] 0xa087[ ]: 		0x00000000
>[    0.399683] nouveau T[   VBIOS][0000:01:00.0] 0xa08b[ ]: 		0x00000000 *
>[    0.399684] nouveau T[   VBIOS][0000:01:00.0] 0xa08f[ ]: 		0x00000000
>[    0.399685] nouveau T[   VBIOS][0000:01:00.0] 0xa093[ ]: 		0x00000000
>[    0.399686] nouveau T[   VBIOS][0000:01:00.0] 0xa097[ ]: 		0x00000000
>[    0.399687] nouveau T[   VBIOS][0000:01:00.0] 0xa09b[ ]: 		0x00000000
>[    0.399687] nouveau T[   VBIOS][0000:01:00.0] 0xa09f[ ]: 		0x00000000
>[    0.399688] nouveau T[   VBIOS][0000:01:00.0] 0xa0a3[ ]: 	}
>[    0.399689] nouveau T[   VBIOS][0000:01:00.0] 0xa0a3[ ]: 	R[0x11ea90] = {
>[    0.399690] nouveau T[   VBIOS][0000:01:00.0] 0xa0a3[ ]: 		0x00000000
>[    0.399690] nouveau T[   VBIOS][0000:01:00.0] 0xa0a7[ ]: 		0x00000000
>[    0.399691] nouveau T[   VBIOS][0000:01:00.0] 0xa0ab[ ]: 		0x00000000 *
>[    0.399692] nouveau T[   VBIOS][0000:01:00.0] 0xa0af[ ]: 		0x00000000
>[    0.399693] nouveau T[   VBIOS][0000:01:00.0] 0xa0b3[ ]: 		0x00000000
>[    0.399693] nouveau T[   VBIOS][0000:01:00.0] 0xa0b7[ ]: 		0x00000000
>[    0.399694] nouveau T[   VBIOS][0000:01:00.0] 0xa0bb[ ]: 		0x00000000
>[    0.399695] nouveau T[   VBIOS][0000:01:00.0] 0xa0bf[ ]: 		0x00000000
>[    0.399696] nouveau T[   VBIOS][0000:01:00.0] 0xa0c3[ ]: 	}
>[    0.399697] nouveau T[   VBIOS][0000:01:00.0] 0xa0c3[ ]: 	R[0x11ea94] = {
>[    0.399697] nouveau T[   VBIOS][0000:01:00.0] 0xa0c3[ ]: 		0x00000000
>[    0.399698] nouveau T[   VBIOS][0000:01:00.0] 0xa0c7[ ]: 		0x00000000
>[    0.399699] nouveau T[   VBIOS][0000:01:00.0] 0xa0cb[ ]: 		0x00000000 *
>[    0.399700] nouveau T[   VBIOS][0000:01:00.0] 0xa0cf[ ]: 		0x00000000
>[    0.399700] nouveau T[   VBIOS][0000:01:00.0] 0xa0d3[ ]: 		0x00000000
>[    0.399701] nouveau T[   VBIOS][0000:01:00.0] 0xa0d7[ ]: 		0x00000000
>[    0.399702] nouveau T[   VBIOS][0000:01:00.0] 0xa0db[ ]: 		0x00000000
>[    0.399703] nouveau T[   VBIOS][0000:01:00.0] 0xa0df[ ]: 		0x00000000
>[    0.399703] nouveau T[   VBIOS][0000:01:00.0] 0xa0e3[ ]: 	}
>[    0.399704] nouveau T[   VBIOS][0000:01:00.0] 0xa0e3[ ]: 	R[0x11ea98] = {
>[    0.399705] nouveau T[   VBIOS][0000:01:00.0] 0xa0e3[ ]: 		0x00000000
>[    0.399706] nouveau T[   VBIOS][0000:01:00.0] 0xa0e7[ ]: 		0x00000000
>[    0.399707] nouveau T[   VBIOS][0000:01:00.0] 0xa0eb[ ]: 		0x00000000 *
>[    0.399707] nouveau T[   VBIOS][0000:01:00.0] 0xa0ef[ ]: 		0x00000000
>[    0.399708] nouveau T[   VBIOS][0000:01:00.0] 0xa0f3[ ]: 		0x00000000
>[    0.399709] nouveau T[   VBIOS][0000:01:00.0] 0xa0f7[ ]: 		0x00000000
>[    0.399710] nouveau T[   VBIOS][0000:01:00.0] 0xa0fb[ ]: 		0x00000000
>[    0.399711] nouveau T[   VBIOS][0000:01:00.0] 0xa0ff[ ]: 		0x00000000
>[    0.399740] nouveau T[   VBIOS][0000:01:00.0] 0xa103[ ]: 	}
>[    0.399742] nouveau T[   VBIOS][0000:01:00.0] 0xa103[ ]: 	R[0x11ea9c] = {
>[    0.399743] nouveau T[   VBIOS][0000:01:00.0] 0xa103[ ]: 		0x00000000
>[    0.399744] nouveau T[   VBIOS][0000:01:00.0] 0xa107[ ]: 		0x00000000
>[    0.399746] nouveau T[   VBIOS][0000:01:00.0] 0xa10b[ ]: 		0x00000000 *
>[    0.399747] nouveau T[   VBIOS][0000:01:00.0] 0xa10f[ ]: 		0x00000000
>[    0.399748] nouveau T[   VBIOS][0000:01:00.0] 0xa113[ ]: 		0x00000000
>[    0.399749] nouveau T[   VBIOS][0000:01:00.0] 0xa117[ ]: 		0x00000000
>[    0.399750] nouveau T[   VBIOS][0000:01:00.0] 0xa11b[ ]: 		0x00000000
>[    0.399751] nouveau T[   VBIOS][0000:01:00.0] 0xa11f[ ]: 		0x00000000
>[    0.399751] nouveau T[   VBIOS][0000:01:00.0] 0xa123[ ]: 	}
>[    0.399752] nouveau T[   VBIOS][0000:01:00.0] 0xa123[ ]: 	R[0x11eaa0] = {
>[    0.399753] nouveau T[   VBIOS][0000:01:00.0] 0xa123[ ]: 		0x00000000
>[    0.399754] nouveau T[   VBIOS][0000:01:00.0] 0xa127[ ]: 		0x00000000
>[    0.399755] nouveau T[   VBIOS][0000:01:00.0] 0xa12b[ ]: 		0x00000000 *
>[    0.399755] nouveau T[   VBIOS][0000:01:00.0] 0xa12f[ ]: 		0x00000000
>[    0.399756] nouveau T[   VBIOS][0000:01:00.0] 0xa133[ ]: 		0x00000000
>[    0.399757] nouveau T[   VBIOS][0000:01:00.0] 0xa137[ ]: 		0x00000000
>[    0.399758] nouveau T[   VBIOS][0000:01:00.0] 0xa13b[ ]: 		0x00000000
>[    0.399758] nouveau T[   VBIOS][0000:01:00.0] 0xa13f[ ]: 		0x00000000
>[    0.399759] nouveau T[   VBIOS][0000:01:00.0] 0xa143[ ]: 	}
>[    0.399760] nouveau T[   VBIOS][0000:01:00.0] 0xa143[ ]: 	R[0x11eaa4] = {
>[    0.399761] nouveau T[   VBIOS][0000:01:00.0] 0xa143[ ]: 		0x00000000
>[    0.399762] nouveau T[   VBIOS][0000:01:00.0] 0xa147[ ]: 		0x00000000
>[    0.399762] nouveau T[   VBIOS][0000:01:00.0] 0xa14b[ ]: 		0x00000000 *
>[    0.399763] nouveau T[   VBIOS][0000:01:00.0] 0xa14f[ ]: 		0x00000000
>[    0.399764] nouveau T[   VBIOS][0000:01:00.0] 0xa153[ ]: 		0x00000000
>[    0.399765] nouveau T[   VBIOS][0000:01:00.0] 0xa157[ ]: 		0x00000000
>[    0.399766] nouveau T[   VBIOS][0000:01:00.0] 0xa15b[ ]: 		0x00000000
>[    0.399766] nouveau T[   VBIOS][0000:01:00.0] 0xa15f[ ]: 		0x00000000
>[    0.399767] nouveau T[   VBIOS][0000:01:00.0] 0xa163[ ]: 	}
>[    0.399768] nouveau T[   VBIOS][0000:01:00.0] 0xa163[ ]: 	R[0x11eaa8] = {
>[    0.399769] nouveau T[   VBIOS][0000:01:00.0] 0xa163[ ]: 		0x00000000
>[    0.399770] nouveau T[   VBIOS][0000:01:00.0] 0xa167[ ]: 		0x00000000
>[    0.399770] nouveau T[   VBIOS][0000:01:00.0] 0xa16b[ ]: 		0x00000000 *
>[    0.399771] nouveau T[   VBIOS][0000:01:00.0] 0xa16f[ ]: 		0x00000000
>[    0.399772] nouveau T[   VBIOS][0000:01:00.0] 0xa173[ ]: 		0x00000000
>[    0.399773] nouveau T[   VBIOS][0000:01:00.0] 0xa177[ ]: 		0x00000000
>[    0.399774] nouveau T[   VBIOS][0000:01:00.0] 0xa17b[ ]: 		0x00000000
>[    0.399784] nouveau T[   VBIOS][0000:01:00.0] 0xa17f[ ]: 		0x00000000
>[    0.399784] nouveau T[   VBIOS][0000:01:00.0] 0xa183[ ]: 	}
>[    0.399785] nouveau T[   VBIOS][0000:01:00.0] 0xa183[ ]: 	R[0x11eaac] = {
>[    0.399786] nouveau T[   VBIOS][0000:01:00.0] 0xa183[ ]: 		0x00000000
>[    0.399787] nouveau T[   VBIOS][0000:01:00.0] 0xa187[ ]: 		0x00000000
>[    0.399788] nouveau T[   VBIOS][0000:01:00.0] 0xa18b[ ]: 		0x00000000 *
>[    0.399788] nouveau T[   VBIOS][0000:01:00.0] 0xa18f[ ]: 		0x00000000
>[    0.399789] nouveau T[   VBIOS][0000:01:00.0] 0xa193[ ]: 		0x00000000
>[    0.399790] nouveau T[   VBIOS][0000:01:00.0] 0xa197[ ]: 		0x00000000
>[    0.399791] nouveau T[   VBIOS][0000:01:00.0] 0xa19b[ ]: 		0x00000000
>[    0.399791] nouveau T[   VBIOS][0000:01:00.0] 0xa19f[ ]: 		0x00000000
>[    0.399792] nouveau T[   VBIOS][0000:01:00.0] 0xa1a3[ ]: 	}
>[    0.399793] nouveau T[   VBIOS][0000:01:00.0] 0xa1a3[ ]: 	R[0x11eab0] = {
>[    0.399794] nouveau T[   VBIOS][0000:01:00.0] 0xa1a3[ ]: 		0x00000000
>[    0.399794] nouveau T[   VBIOS][0000:01:00.0] 0xa1a7[ ]: 		0x00000000
>[    0.399795] nouveau T[   VBIOS][0000:01:00.0] 0xa1ab[ ]: 		0x00000000 *
>[    0.399796] nouveau T[   VBIOS][0000:01:00.0] 0xa1af[ ]: 		0x00000000
>[    0.399797] nouveau T[   VBIOS][0000:01:00.0] 0xa1b3[ ]: 		0x00000000
>[    0.399797] nouveau T[   VBIOS][0000:01:00.0] 0xa1b7[ ]: 		0x00000000
>[    0.399798] nouveau T[   VBIOS][0000:01:00.0] 0xa1bb[ ]: 		0x00000000
>[    0.399799] nouveau T[   VBIOS][0000:01:00.0] 0xa1bf[ ]: 		0x00000000
>[    0.399800] nouveau T[   VBIOS][0000:01:00.0] 0xa1c3[ ]: 	}
>[    0.399801] nouveau T[   VBIOS][0000:01:00.0] 0xa1c3[ ]: 	R[0x11eab4] = {
>[    0.399801] nouveau T[   VBIOS][0000:01:00.0] 0xa1c3[ ]: 		0x00000000
>[    0.399802] nouveau T[   VBIOS][0000:01:00.0] 0xa1c7[ ]: 		0x00000000
>[    0.399803] nouveau T[   VBIOS][0000:01:00.0] 0xa1cb[ ]: 		0x00000000 *
>[    0.399804] nouveau T[   VBIOS][0000:01:00.0] 0xa1cf[ ]: 		0x00000000
>[    0.399804] nouveau T[   VBIOS][0000:01:00.0] 0xa1d3[ ]: 		0x00000000
>[    0.399805] nouveau T[   VBIOS][0000:01:00.0] 0xa1d7[ ]: 		0x00000000
>[    0.399806] nouveau T[   VBIOS][0000:01:00.0] 0xa1db[ ]: 		0x00000000
>[    0.399807] nouveau T[   VBIOS][0000:01:00.0] 0xa1df[ ]: 		0x00000000
>[    0.399807] nouveau T[   VBIOS][0000:01:00.0] 0xa1e3[ ]: 	}
>[    0.399808] nouveau T[   VBIOS][0000:01:00.0] 0xa1e3[ ]: 	R[0x11eab8] = {
>[    0.399809] nouveau T[   VBIOS][0000:01:00.0] 0xa1e3[ ]: 		0x00000000
>[    0.399810] nouveau T[   VBIOS][0000:01:00.0] 0xa1e7[ ]: 		0x00000000
>[    0.399811] nouveau T[   VBIOS][0000:01:00.0] 0xa1eb[ ]: 		0x00000000 *
>[    0.399811] nouveau T[   VBIOS][0000:01:00.0] 0xa1ef[ ]: 		0x00000000
>[    0.399812] nouveau T[   VBIOS][0000:01:00.0] 0xa1f3[ ]: 		0x00000000
>[    0.399813] nouveau T[   VBIOS][0000:01:00.0] 0xa1f7[ ]: 		0x00000000
>[    0.399814] nouveau T[   VBIOS][0000:01:00.0] 0xa1fb[ ]: 		0x00000000
>[    0.399814] nouveau T[   VBIOS][0000:01:00.0] 0xa1ff[ ]: 		0x00000000
>[    0.399815] nouveau T[   VBIOS][0000:01:00.0] 0xa203[ ]: 	}
>[    0.399816] nouveau T[   VBIOS][0000:01:00.0] 0xa203[ ]: 	R[0x11eabc] = {
>[    0.399817] nouveau T[   VBIOS][0000:01:00.0] 0xa203[ ]: 		0x00000000
>[    0.399817] nouveau T[   VBIOS][0000:01:00.0] 0xa207[ ]: 		0x00000000
>[    0.399818] nouveau T[   VBIOS][0000:01:00.0] 0xa20b[ ]: 		0x00000000 *
>[    0.399819] nouveau T[   VBIOS][0000:01:00.0] 0xa20f[ ]: 		0x00000000
>[    0.399820] nouveau T[   VBIOS][0000:01:00.0] 0xa213[ ]: 		0x00000000
>[    0.399821] nouveau T[   VBIOS][0000:01:00.0] 0xa217[ ]: 		0x00000000
>[    0.399821] nouveau T[   VBIOS][0000:01:00.0] 0xa21b[ ]: 		0x00000000
>[    0.399822] nouveau T[   VBIOS][0000:01:00.0] 0xa21f[ ]: 		0x00000000
>[    0.399823] nouveau T[   VBIOS][0000:01:00.0] 0xa223[ ]: 	}
>[    0.399824] nouveau T[   VBIOS][0000:01:00.0] 0xa223[ ]: ZM_REG	R[0x131c18] = 0x1000d000
>[    0.399825] nouveau T[   VBIOS][0000:01:00.0] 0xa22c[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001373ec] 0x04 0x01
>[    0.399826] nouveau T[   VBIOS][0000:01:00.0] 0xa233[ ]: 	R[0x1373ec] = {
>[    0.399826] nouveau T[   VBIOS][0000:01:00.0] 0xa233[ ]: 		0x00010000
>[    0.399827] nouveau T[   VBIOS][0000:01:00.0] 0xa237[ ]: 		0x00010000
>[    0.399828] nouveau T[   VBIOS][0000:01:00.0] 0xa23b[ ]: 		0x00010000 *
>[    0.399829] nouveau T[   VBIOS][0000:01:00.0] 0xa23f[ ]: 		0x00010000
>[    0.399830] nouveau T[   VBIOS][0000:01:00.0] 0xa243[ ]: 		0x00010000
>[    0.399830] nouveau T[   VBIOS][0000:01:00.0] 0xa247[ ]: 		0x00010000
>[    0.399831] nouveau T[   VBIOS][0000:01:00.0] 0xa24b[ ]: 		0x00000000
>[    0.399832] nouveau T[   VBIOS][0000:01:00.0] 0xa24f[ ]: 		0x00000000
>[    0.399833] nouveau T[   VBIOS][0000:01:00.0] 0xa253[ ]: 	}
>[    0.399834] nouveau T[   VBIOS][0000:01:00.0] 0xa253[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e82c] 0x04 0x01
>[    0.399835] nouveau T[   VBIOS][0000:01:00.0] 0xa25a[ ]: 	R[0x11e82c] = {
>[    0.399835] nouveau T[   VBIOS][0000:01:00.0] 0xa25a[ ]: 		0x00150000
>[    0.399836] nouveau T[   VBIOS][0000:01:00.0] 0xa25e[ ]: 		0x00150000
>[    0.399837] nouveau T[   VBIOS][0000:01:00.0] 0xa262[ ]: 		0x00150000 *
>[    0.399838] nouveau T[   VBIOS][0000:01:00.0] 0xa266[ ]: 		0x00150000
>[    0.399838] nouveau T[   VBIOS][0000:01:00.0] 0xa26a[ ]: 		0x00150000
>[    0.399839] nouveau T[   VBIOS][0000:01:00.0] 0xa26e[ ]: 		0x00150000
>[    0.399840] nouveau T[   VBIOS][0000:01:00.0] 0xa272[ ]: 		0x00150000
>[    0.399841] nouveau T[   VBIOS][0000:01:00.0] 0xa276[ ]: 		0x00150000
>[    0.399841] nouveau T[   VBIOS][0000:01:00.0] 0xa27a[ ]: 	}
>[    0.399842] nouveau T[   VBIOS][0000:01:00.0] 0xa27a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e870] 0x04 0x01
>[    0.399843] nouveau T[   VBIOS][0000:01:00.0] 0xa281[ ]: 	R[0x11e870] = {
>[    0.399844] nouveau T[   VBIOS][0000:01:00.0] 0xa281[ ]: 		0x33333333
>[    0.399845] nouveau T[   VBIOS][0000:01:00.0] 0xa285[ ]: 		0x33333333
>[    0.399846] nouveau T[   VBIOS][0000:01:00.0] 0xa289[ ]: 		0x33333333 *
>[    0.399846] nouveau T[   VBIOS][0000:01:00.0] 0xa28d[ ]: 		0x33333333
>[    0.399847] nouveau T[   VBIOS][0000:01:00.0] 0xa291[ ]: 		0x33333333
>[    0.399848] nouveau T[   VBIOS][0000:01:00.0] 0xa295[ ]: 		0x33333333
>[    0.399849] nouveau T[   VBIOS][0000:01:00.0] 0xa299[ ]: 		0x33333333
>[    0.399849] nouveau T[   VBIOS][0000:01:00.0] 0xa29d[ ]: 		0x33333333
>[    0.399850] nouveau T[   VBIOS][0000:01:00.0] 0xa2a1[ ]: 	}
>[    0.399851] nouveau T[   VBIOS][0000:01:00.0] 0xa2a1[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011eecc] 0x04 0x01
>[    0.399852] nouveau T[   VBIOS][0000:01:00.0] 0xa2a8[ ]: 	R[0x11eecc] = {
>[    0.399853] nouveau T[   VBIOS][0000:01:00.0] 0xa2a8[ ]: 		0x0000021e
>[    0.399854] nouveau T[   VBIOS][0000:01:00.0] 0xa2ac[ ]: 		0x0000021e
>[    0.399854] nouveau T[   VBIOS][0000:01:00.0] 0xa2b0[ ]: 		0x0000021e *
>[    0.399855] nouveau T[   VBIOS][0000:01:00.0] 0xa2b4[ ]: 		0x0000021e
>[    0.399856] nouveau T[   VBIOS][0000:01:00.0] 0xa2b8[ ]: 		0x0000021e
>[    0.399857] nouveau T[   VBIOS][0000:01:00.0] 0xa2bc[ ]: 		0x0000021e
>[    0.399858] nouveau T[   VBIOS][0000:01:00.0] 0xa2c0[ ]: 		0x0000021e
>[    0.399858] nouveau T[   VBIOS][0000:01:00.0] 0xa2c4[ ]: 		0x0000021e
>[    0.399859] nouveau T[   VBIOS][0000:01:00.0] 0xa2c8[ ]: 	}
>[    0.399860] nouveau T[   VBIOS][0000:01:00.0] 0xa2c8[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e60c] 0x04 0x01
>[    0.399861] nouveau T[   VBIOS][0000:01:00.0] 0xa2cf[ ]: 	R[0x11e60c] = {
>[    0.399862] nouveau T[   VBIOS][0000:01:00.0] 0xa2cf[ ]: 		0xfd000050
>[    0.399862] nouveau T[   VBIOS][0000:01:00.0] 0xa2d3[ ]: 		0xfd000050
>[    0.399863] nouveau T[   VBIOS][0000:01:00.0] 0xa2d7[ ]: 		0xfd000050 *
>[    0.399864] nouveau T[   VBIOS][0000:01:00.0] 0xa2db[ ]: 		0xfd000050
>[    0.399865] nouveau T[   VBIOS][0000:01:00.0] 0xa2df[ ]: 		0xfd000050
>[    0.399866] nouveau T[   VBIOS][0000:01:00.0] 0xa2e3[ ]: 		0xfd000050
>[    0.399866] nouveau T[   VBIOS][0000:01:00.0] 0xa2e7[ ]: 		0xfd000050
>[    0.399867] nouveau T[   VBIOS][0000:01:00.0] 0xa2eb[ ]: 		0xfd000050
>[    0.399868] nouveau T[   VBIOS][0000:01:00.0] 0xa2ef[ ]: 	}
>[    0.399869] nouveau T[   VBIOS][0000:01:00.0] 0xa2ef[ ]: CONDITION	0x28
>[    0.399870] nouveau T[   VBIOS][0000:01:00.0] 0xa2f1[ ]: 	[0x28] (R[0x001590] & 0x00000008) == 0x00000008
>[    0.399871] nouveau T[   VBIOS][0000:01:00.0] 0xa2f1[ ]: NOT
>[    0.399872] nouveau T[   VBIOS][0000:01:00.0] 0xa2f2[ ]: NV_REG	R[0x11e60c] &= 0xffffffef |= 0x00000010
>[    0.399872] nouveau T[   VBIOS][0000:01:00.0] 0xa2ff[ ]: RESUME
>[    0.399874] nouveau T[   VBIOS][0000:01:00.0] 0xa300[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e824] 0x04 0x01
>[    0.399874] nouveau T[   VBIOS][0000:01:00.0] 0xa307[ ]: 	R[0x11e824] = {
>[    0.399875] nouveau T[   VBIOS][0000:01:00.0] 0xa307[ ]: 		0x4080ffe7
>[    0.399876] nouveau T[   VBIOS][0000:01:00.0] 0xa30b[ ]: 		0x4080ffe7
>[    0.399877] nouveau T[   VBIOS][0000:01:00.0] 0xa30f[ ]: 		0x4080ffe7 *
>[    0.399877] nouveau T[   VBIOS][0000:01:00.0] 0xa313[ ]: 		0x4080ffe7
>[    0.399878] nouveau T[   VBIOS][0000:01:00.0] 0xa317[ ]: 		0x4080ffe7
>[    0.399879] nouveau T[   VBIOS][0000:01:00.0] 0xa31b[ ]: 		0x4080ffe7
>[    0.399880] nouveau T[   VBIOS][0000:01:00.0] 0xa31f[ ]: 		0x4088fde7
>[    0.399881] nouveau T[   VBIOS][0000:01:00.0] 0xa323[ ]: 		0x4088fde7
>[    0.399881] nouveau T[   VBIOS][0000:01:00.0] 0xa327[ ]: 	}
>[    0.399882] nouveau T[   VBIOS][0000:01:00.0] 0xa327[ ]: ZM_REG	R[0x11e060] = 0x0000000f
>[    0.399883] nouveau T[   VBIOS][0000:01:00.0] 0xa330[ ]: ZM_REG	R[0x11ed34] = 0x00080008
>[    0.399884] nouveau T[   VBIOS][0000:01:00.0] 0xa339[ ]: NV_REG	R[0x137330] &= 0x7fffffc0 |= 0x80000034
>[    0.399885] nouveau T[   VBIOS][0000:01:00.0] 0xa346[ ]: NV_REG	R[0x137320] &= 0xfffcfffc |= 0x00000000
>[    0.399886] nouveau T[   VBIOS][0000:01:00.0] 0xa353[ ]: CONDITION_TIME	0x10 0xff
>[    0.399887] nouveau T[   VBIOS][0000:01:00.0] 0xa356[ ]: RESUME
>[    0.399888] nouveau T[   VBIOS][0000:01:00.0] 0xa357[ ]: ZM_REG	R[0x131c24] = 0x00032501
>[    0.399889] nouveau T[   VBIOS][0000:01:00.0] 0xa360[ ]: NV_REG	R[0x131c2c] &= 0xfffffcff |= 0x00000300
>[    0.399890] nouveau T[   VBIOS][0000:01:00.0] 0xa36d[ ]: CONDITION	0x1f
>[    0.399891] nouveau T[   VBIOS][0000:01:00.0] 0xa36f[ ]: 	[0x1f] (R[0x131c2c] & 0x00000300) == 0x00000300
>[    0.399892] nouveau T[   VBIOS][0000:01:00.0] 0xa36f[ ]: ZM_REG	R[0x131c30] = 0x08e40004
>[    0.399893] nouveau T[   VBIOS][0000:01:00.0] 0xa378[ ]: ZM_REG	R[0x131c34] = 0x02d908e4
>[    0.399893] nouveau T[   VBIOS][0000:01:00.0] 0xa381[ ]: RESUME
>[    0.399894] nouveau T[   VBIOS][0000:01:00.0] 0xa382[ ]: ZM_REG	R[0x131c20] = 0x00000001
>[    0.399895] nouveau T[   VBIOS][0000:01:00.0] 0xa38b[ ]: CONDITION_TIME	0x12 0xff
>[    0.399896] nouveau T[   VBIOS][0000:01:00.0] 0xa38e[ ]: RESUME
>[    0.399897] nouveau T[   VBIOS][0000:01:00.0] 0xa38f[ ]: NV_REG	R[0x137360] &= 0xfffffffd |= 0x00000000
>[    0.399898] nouveau T[   VBIOS][0000:01:00.0] 0xa39c[ ]: NV_REG	R[0x137380] &= 0xfffffffd |= 0x00000002
>[    0.399899] nouveau T[   VBIOS][0000:01:00.0] 0xa3a9[ ]: NV_REG	R[0x1373f4] &= 0xfffefeef |= 0x00010110
>[    0.399900] nouveau T[   VBIOS][0000:01:00.0] 0xa3b6[ ]: NV_REG	R[0x1373f4] &= 0xfffffffc |= 0x00000001
>[    0.399901] nouveau T[   VBIOS][0000:01:00.0] 0xa3c3[ ]: NV_REG	R[0x1373f4] &= 0xfffefeef |= 0x00000000
>[    0.399902] nouveau T[   VBIOS][0000:01:00.0] 0xa3d0[ ]: ZM_REG	R[0x11e080] = 0x00000000
>[    0.399903] nouveau T[   VBIOS][0000:01:00.0] 0xa3d9[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e290] 0x04 0x08
>[    0.399904] nouveau T[   VBIOS][0000:01:00.0] 0xa3e0[ ]: 	R[0x11e290] = {
>[    0.399904] nouveau T[   VBIOS][0000:01:00.0] 0xa3e0[ ]: 		0x04121a0d
>[    0.399905] nouveau T[   VBIOS][0000:01:00.0] 0xa3e4[ ]: 		0x04121a0d
>[    0.399906] nouveau T[   VBIOS][0000:01:00.0] 0xa3e8[ ]: 		0x040e1a0b *
>[    0.399907] nouveau T[   VBIOS][0000:01:00.0] 0xa3ec[ ]: 		0x040e1a0b
>[    0.399908] nouveau T[   VBIOS][0000:01:00.0] 0xa3f0[ ]: 		0x04121a0d
>[    0.399908] nouveau T[   VBIOS][0000:01:00.0] 0xa3f4[ ]: 		0x040c0c0a
>[    0.399909] nouveau T[   VBIOS][0000:01:00.0] 0xa3f8[ ]: 		0x040e1a0b
>[    0.399910] nouveau T[   VBIOS][0000:01:00.0] 0xa3fc[ ]: 		0x040e1a0b
>[    0.399911] nouveau T[   VBIOS][0000:01:00.0] 0xa400[ ]: 	}
>[    0.399911] nouveau T[   VBIOS][0000:01:00.0] 0xa400[ ]: 	R[0x11e294] = {
>[    0.399912] nouveau T[   VBIOS][0000:01:00.0] 0xa400[ ]: 		0x2c414289
>[    0.399913] nouveau T[   VBIOS][0000:01:00.0] 0xa404[ ]: 		0x2c414289
>[    0.399914] nouveau T[   VBIOS][0000:01:00.0] 0xa408[ ]: 		0x2c310289 *
>[    0.399915] nouveau T[   VBIOS][0000:01:00.0] 0xa40c[ ]: 		0x2c310289
>[    0.399915] nouveau T[   VBIOS][0000:01:00.0] 0xa410[ ]: 		0x2c414289
>[    0.399916] nouveau T[   VBIOS][0000:01:00.0] 0xa414[ ]: 		0x2c110287
>[    0.399917] nouveau T[   VBIOS][0000:01:00.0] 0xa418[ ]: 		0x2c310289
>[    0.399918] nouveau T[   VBIOS][0000:01:00.0] 0xa41c[ ]: 		0x2c310289
>[    0.399918] nouveau T[   VBIOS][0000:01:00.0] 0xa420[ ]: 	}
>[    0.399919] nouveau T[   VBIOS][0000:01:00.0] 0xa420[ ]: 	R[0x11e298] = {
>[    0.399920] nouveau T[   VBIOS][0000:01:00.0] 0xa420[ ]: 		0x8c050411
>[    0.399921] nouveau T[   VBIOS][0000:01:00.0] 0xa424[ ]: 		0x8c050411
>[    0.399922] nouveau T[   VBIOS][0000:01:00.0] 0xa428[ ]: 		0x8c040311 *
>[    0.399922] nouveau T[   VBIOS][0000:01:00.0] 0xa42c[ ]: 		0x8c040311
>[    0.399923] nouveau T[   VBIOS][0000:01:00.0] 0xa430[ ]: 		0x8c050411
>[    0.399924] nouveau T[   VBIOS][0000:01:00.0] 0xa434[ ]: 		0x8c040211
>[    0.399925] nouveau T[   VBIOS][0000:01:00.0] 0xa438[ ]: 		0x8c040311
>[    0.399925] nouveau T[   VBIOS][0000:01:00.0] 0xa43c[ ]: 		0x8c040311
>[    0.399926] nouveau T[   VBIOS][0000:01:00.0] 0xa440[ ]: 	}
>[    0.399927] nouveau T[   VBIOS][0000:01:00.0] 0xa440[ ]: 	R[0x11e29c] = {
>[    0.399928] nouveau T[   VBIOS][0000:01:00.0] 0xa440[ ]: 		0x2200138c
>[    0.399929] nouveau T[   VBIOS][0000:01:00.0] 0xa444[ ]: 		0x2200138c
>[    0.399929] nouveau T[   VBIOS][0000:01:00.0] 0xa448[ ]: 		0x2200136a *
>[    0.399930] nouveau T[   VBIOS][0000:01:00.0] 0xa44c[ ]: 		0x2200136a
>[    0.399931] nouveau T[   VBIOS][0000:01:00.0] 0xa450[ ]: 		0x2200138c
>[    0.399932] nouveau T[   VBIOS][0000:01:00.0] 0xa454[ ]: 		0x2200114a
>[    0.399933] nouveau T[   VBIOS][0000:01:00.0] 0xa458[ ]: 		0x2200136a
>[    0.399933] nouveau T[   VBIOS][0000:01:00.0] 0xa45c[ ]: 		0x2200136a
>[    0.399934] nouveau T[   VBIOS][0000:01:00.0] 0xa460[ ]: 	}
>[    0.399935] nouveau T[   VBIOS][0000:01:00.0] 0xa460[ ]: 	R[0x11e2a0] = {
>[    0.399936] nouveau T[   VBIOS][0000:01:00.0] 0xa460[ ]: 		0x4361001a
>[    0.399936] nouveau T[   VBIOS][0000:01:00.0] 0xa464[ ]: 		0x4361001a
>[    0.399937] nouveau T[   VBIOS][0000:01:00.0] 0xa468[ ]: 		0x4361001a *
>[    0.399938] nouveau T[   VBIOS][0000:01:00.0] 0xa46c[ ]: 		0x4361001a
>[    0.399939] nouveau T[   VBIOS][0000:01:00.0] 0xa470[ ]: 		0x4361001a
>[    0.399940] nouveau T[   VBIOS][0000:01:00.0] 0xa474[ ]: 		0x43610033
>[    0.399940] nouveau T[   VBIOS][0000:01:00.0] 0xa478[ ]: 		0x4361001a
>[    0.399941] nouveau T[   VBIOS][0000:01:00.0] 0xa47c[ ]: 		0x4361001a
>[    0.399942] nouveau T[   VBIOS][0000:01:00.0] 0xa480[ ]: 	}
>[    0.399943] nouveau T[   VBIOS][0000:01:00.0] 0xa480[ ]: 	R[0x11e2a4] = {
>[    0.399943] nouveau T[   VBIOS][0000:01:00.0] 0xa480[ ]: 		0xa6b270e2
>[    0.399944] nouveau T[   VBIOS][0000:01:00.0] 0xa484[ ]: 		0xa6b270e2
>[    0.399945] nouveau T[   VBIOS][0000:01:00.0] 0xa488[ ]: 		0xa6b27072 *
>[    0.399946] nouveau T[   VBIOS][0000:01:00.0] 0xa48c[ ]: 		0xa6b27072
>[    0.399947] nouveau T[   VBIOS][0000:01:00.0] 0xa490[ ]: 		0xa6b270e2
>[    0.399947] nouveau T[   VBIOS][0000:01:00.0] 0xa494[ ]: 		0xa6b270c2
>[    0.399948] nouveau T[   VBIOS][0000:01:00.0] 0xa498[ ]: 		0xa6b27072
>[    0.399949] nouveau T[   VBIOS][0000:01:00.0] 0xa49c[ ]: 		0xa6b27072
>[    0.399950] nouveau T[   VBIOS][0000:01:00.0] 0xa4a0[ ]: 	}
>[    0.399950] nouveau T[   VBIOS][0000:01:00.0] 0xa4a0[ ]: 	R[0x11e2a8] = {
>[    0.399951] nouveau T[   VBIOS][0000:01:00.0] 0xa4a0[ ]: 		0x0000860b
>[    0.399952] nouveau T[   VBIOS][0000:01:00.0] 0xa4a4[ ]: 		0x0000860b
>[    0.399953] nouveau T[   VBIOS][0000:01:00.0] 0xa4a8[ ]: 		0x0000860b *
>[    0.399954] nouveau T[   VBIOS][0000:01:00.0] 0xa4ac[ ]: 		0x0000860b
>[    0.399954] nouveau T[   VBIOS][0000:01:00.0] 0xa4b0[ ]: 		0x0000860b
>[    0.399955] nouveau T[   VBIOS][0000:01:00.0] 0xa4b4[ ]: 		0x0000860b
>[    0.399956] nouveau T[   VBIOS][0000:01:00.0] 0xa4b8[ ]: 		0x0000860b
>[    0.399957] nouveau T[   VBIOS][0000:01:00.0] 0xa4bc[ ]: 		0x0000860b
>[    0.399957] nouveau T[   VBIOS][0000:01:00.0] 0xa4c0[ ]: 	}
>[    0.399958] nouveau T[   VBIOS][0000:01:00.0] 0xa4c0[ ]: 	R[0x11e2ac] = {
>[    0.399959] nouveau T[   VBIOS][0000:01:00.0] 0xa4c0[ ]: 		0x00c35000
>[    0.399960] nouveau T[   VBIOS][0000:01:00.0] 0xa4c4[ ]: 		0x00c35000
>[    0.399961] nouveau T[   VBIOS][0000:01:00.0] 0xa4c8[ ]: 		0x00c35000 *
>[    0.399961] nouveau T[   VBIOS][0000:01:00.0] 0xa4cc[ ]: 		0x00c35000
>[    0.399962] nouveau T[   VBIOS][0000:01:00.0] 0xa4d0[ ]: 		0x00c35000
>[    0.399963] nouveau T[   VBIOS][0000:01:00.0] 0xa4d4[ ]: 		0x00c35000
>[    0.399964] nouveau T[   VBIOS][0000:01:00.0] 0xa4d8[ ]: 		0x00c35000
>[    0.399964] nouveau T[   VBIOS][0000:01:00.0] 0xa4dc[ ]: 		0x00c35000
>[    0.399965] nouveau T[   VBIOS][0000:01:00.0] 0xa4e0[ ]: 	}
>[    0.399966] nouveau T[   VBIOS][0000:01:00.0] 0xa4e0[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e2cc] 0x04 0x01
>[    0.399967] nouveau T[   VBIOS][0000:01:00.0] 0xa4e7[ ]: 	R[0x11e2cc] = {
>[    0.399968] nouveau T[   VBIOS][0000:01:00.0] 0xa4e7[ ]: 		0x0c0a3900
>[    0.399969] nouveau T[   VBIOS][0000:01:00.0] 0xa4eb[ ]: 		0x0c0a3900
>[    0.399969] nouveau T[   VBIOS][0000:01:00.0] 0xa4ef[ ]: 		0x0c0a3900 *
>[    0.399970] nouveau T[   VBIOS][0000:01:00.0] 0xa4f3[ ]: 		0x0c0a3900
>[    0.399971] nouveau T[   VBIOS][0000:01:00.0] 0xa4f7[ ]: 		0x0c0a3900
>[    0.399972] nouveau T[   VBIOS][0000:01:00.0] 0xa4fb[ ]: 		0x0a053900
>[    0.399973] nouveau T[   VBIOS][0000:01:00.0] 0xa4ff[ ]: 		0x0c0a3900
>[    0.399973] nouveau T[   VBIOS][0000:01:00.0] 0xa503[ ]: 		0x0c0a3900
>[    0.399974] nouveau T[   VBIOS][0000:01:00.0] 0xa507[ ]: 	}
>[    0.399975] nouveau T[   VBIOS][0000:01:00.0] 0xa507[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e2e8] 0x04 0x01
>[    0.399976] nouveau T[   VBIOS][0000:01:00.0] 0xa50e[ ]: 	R[0x11e2e8] = {
>[    0.399977] nouveau T[   VBIOS][0000:01:00.0] 0xa50e[ ]: 		0x00000006
>[    0.399978] nouveau T[   VBIOS][0000:01:00.0] 0xa512[ ]: 		0x00000006
>[    0.399978] nouveau T[   VBIOS][0000:01:00.0] 0xa516[ ]: 		0x00000006 *
>[    0.399979] nouveau T[   VBIOS][0000:01:00.0] 0xa51a[ ]: 		0x00000006
>[    0.399980] nouveau T[   VBIOS][0000:01:00.0] 0xa51e[ ]: 		0x00000006
>[    0.399981] nouveau T[   VBIOS][0000:01:00.0] 0xa522[ ]: 		0x00000006
>[    0.399981] nouveau T[   VBIOS][0000:01:00.0] 0xa526[ ]: 		0x00000006
>[    0.399982] nouveau T[   VBIOS][0000:01:00.0] 0xa52a[ ]: 		0x00000006
>[    0.399983] nouveau T[   VBIOS][0000:01:00.0] 0xa52e[ ]: 	}
>[    0.399984] nouveau T[   VBIOS][0000:01:00.0] 0xa52e[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e224] 0x04 0x01
>[    0.399985] nouveau T[   VBIOS][0000:01:00.0] 0xa535[ ]: 	R[0x11e224] = {
>[    0.399986] nouveau T[   VBIOS][0000:01:00.0] 0xa535[ ]: 		0x0b020a0a
>[    0.399986] nouveau T[   VBIOS][0000:01:00.0] 0xa539[ ]: 		0x0b020a0a
>[    0.399987] nouveau T[   VBIOS][0000:01:00.0] 0xa53d[ ]: 		0x0a02090a *
>[    0.399988] nouveau T[   VBIOS][0000:01:00.0] 0xa541[ ]: 		0x0d020a09
>[    0.399989] nouveau T[   VBIOS][0000:01:00.0] 0xa545[ ]: 		0x0b020a0a
>[    0.399989] nouveau T[   VBIOS][0000:01:00.0] 0xa549[ ]: 		0x0b020a0a
>[    0.399990] nouveau T[   VBIOS][0000:01:00.0] 0xa54d[ ]: 		0x0b020c09
>[    0.399991] nouveau T[   VBIOS][0000:01:00.0] 0xa551[ ]: 		0x0b020c09
>[    0.399992] nouveau T[   VBIOS][0000:01:00.0] 0xa555[ ]: 	}
>[    0.399993] nouveau T[   VBIOS][0000:01:00.0] 0xa555[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e248] 0x04 0x04
>[    0.399994] nouveau T[   VBIOS][0000:01:00.0] 0xa55c[ ]: 	R[0x11e248] = {
>[    0.399994] nouveau T[   VBIOS][0000:01:00.0] 0xa55c[ ]: 		0x0d1e55d7
>[    0.399995] nouveau T[   VBIOS][0000:01:00.0] 0xa560[ ]: 		0x0d1e55d7
>[    0.399996] nouveau T[   VBIOS][0000:01:00.0] 0xa564[ ]: 		0x0e0c55a7 *
>[    0.399997] nouveau T[   VBIOS][0000:01:00.0] 0xa568[ ]: 		0x0e0c55a7
>[    0.399998] nouveau T[   VBIOS][0000:01:00.0] 0xa56c[ ]: 		0x0d1e55d7
>[    0.399998] nouveau T[   VBIOS][0000:01:00.0] 0xa570[ ]: 		0x0d1444d5
>[    0.399999] nouveau T[   VBIOS][0000:01:00.0] 0xa574[ ]: 		0x0e0c55a7
>[    0.400000] nouveau T[   VBIOS][0000:01:00.0] 0xa578[ ]: 		0x0e0c55a7
>[    0.400001] nouveau T[   VBIOS][0000:01:00.0] 0xa57c[ ]: 	}
>[    0.400001] nouveau T[   VBIOS][0000:01:00.0] 0xa57c[ ]: 	R[0x11e24c] = {
>[    0.400002] nouveau T[   VBIOS][0000:01:00.0] 0xa57c[ ]: 		0x0d0435ae
>[    0.400003] nouveau T[   VBIOS][0000:01:00.0] 0xa580[ ]: 		0x0d0435ae
>[    0.400004] nouveau T[   VBIOS][0000:01:00.0] 0xa584[ ]: 		0x32043dce *
>[    0.400005] nouveau T[   VBIOS][0000:01:00.0] 0xa588[ ]: 		0x320435ae
>[    0.400005] nouveau T[   VBIOS][0000:01:00.0] 0xa58c[ ]: 		0x0d0439ce
>[    0.400006] nouveau T[   VBIOS][0000:01:00.0] 0xa590[ ]: 		0x0d04362e
>[    0.400007] nouveau T[   VBIOS][0000:01:00.0] 0xa594[ ]: 		0x320435ae
>[    0.400008] nouveau T[   VBIOS][0000:01:00.0] 0xa598[ ]: 		0x320435ae
>[    0.400008] nouveau T[   VBIOS][0000:01:00.0] 0xa59c[ ]: 	}
>[    0.400009] nouveau T[   VBIOS][0000:01:00.0] 0xa59c[ ]: 	R[0x11e250] = {
>[    0.400010] nouveau T[   VBIOS][0000:01:00.0] 0xa59c[ ]: 		0x000000a2
>[    0.400011] nouveau T[   VBIOS][0000:01:00.0] 0xa5a0[ ]: 		0x000000a2
>[    0.400012] nouveau T[   VBIOS][0000:01:00.0] 0xa5a4[ ]: 		0x000000a2 *
>[    0.400012] nouveau T[   VBIOS][0000:01:00.0] 0xa5a8[ ]: 		0x000000a2
>[    0.400013] nouveau T[   VBIOS][0000:01:00.0] 0xa5ac[ ]: 		0x000000a2
>[    0.400014] nouveau T[   VBIOS][0000:01:00.0] 0xa5b0[ ]: 		0x00000053
>[    0.400015] nouveau T[   VBIOS][0000:01:00.0] 0xa5b4[ ]: 		0x000000a2
>[    0.400016] nouveau T[   VBIOS][0000:01:00.0] 0xa5b8[ ]: 		0x000000a2
>[    0.400016] nouveau T[   VBIOS][0000:01:00.0] 0xa5bc[ ]: 	}
>[    0.400017] nouveau T[   VBIOS][0000:01:00.0] 0xa5bc[ ]: 	R[0x11e254] = {
>[    0.400018] nouveau T[   VBIOS][0000:01:00.0] 0xa5bc[ ]: 		0x002d1919
>[    0.400019] nouveau T[   VBIOS][0000:01:00.0] 0xa5c0[ ]: 		0x002d1919
>[    0.400019] nouveau T[   VBIOS][0000:01:00.0] 0xa5c4[ ]: 		0x001d1919 *
>[    0.400020] nouveau T[   VBIOS][0000:01:00.0] 0xa5c8[ ]: 		0x001d1919
>[    0.400021] nouveau T[   VBIOS][0000:01:00.0] 0xa5cc[ ]: 		0x002d1919
>[    0.400022] nouveau T[   VBIOS][0000:01:00.0] 0xa5d0[ ]: 		0x00151519
>[    0.400023] nouveau T[   VBIOS][0000:01:00.0] 0xa5d4[ ]: 		0x001d1919
>[    0.400023] nouveau T[   VBIOS][0000:01:00.0] 0xa5d8[ ]: 		0x001d1919
>[    0.400024] nouveau T[   VBIOS][0000:01:00.0] 0xa5dc[ ]: 	}
>[    0.400025] nouveau T[   VBIOS][0000:01:00.0] 0xa5dc[ ]: NV_REG	R[0x11e670] &= 0xff000000 |= 0x00081306
>[    0.400026] nouveau T[   VBIOS][0000:01:00.0] 0xa5e9[ ]: ZM_REG	R[0x11e2fc] = 0x0000005a
>[    0.400027] nouveau T[   VBIOS][0000:01:00.0] 0xa5f2[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e200] 0x04 0x01
>[    0.400028] nouveau T[   VBIOS][0000:01:00.0] 0xa5f9[ ]: 	R[0x11e200] = {
>[    0.400029] nouveau T[   VBIOS][0000:01:00.0] 0xa5f9[ ]: 		0x008f9000
>[    0.400030] nouveau T[   VBIOS][0000:01:00.0] 0xa5fd[ ]: 		0x028f9000
>[    0.400030] nouveau T[   VBIOS][0000:01:00.0] 0xa601[ ]: 		0x028f9000 *
>[    0.400031] nouveau T[   VBIOS][0000:01:00.0] 0xa605[ ]: 		0x028f9000
>[    0.400032] nouveau T[   VBIOS][0000:01:00.0] 0xa609[ ]: 		0x028f9000
>[    0.400033] nouveau T[   VBIOS][0000:01:00.0] 0xa60d[ ]: 		0x028f9000
>[    0.400033] nouveau T[   VBIOS][0000:01:00.0] 0xa611[ ]: 		0x02cf9000
>[    0.400034] nouveau T[   VBIOS][0000:01:00.0] 0xa615[ ]: 		0x02cf9000
>[    0.400035] nouveau T[   VBIOS][0000:01:00.0] 0xa619[ ]: 	}
>[    0.400036] nouveau T[   VBIOS][0000:01:00.0] 0xa619[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e204] 0x04 0x01
>[    0.400037] nouveau T[   VBIOS][0000:01:00.0] 0xa620[ ]: 	R[0x11e204] = {
>[    0.400038] nouveau T[   VBIOS][0000:01:00.0] 0xa620[ ]: 		0x02559000
>[    0.400038] nouveau T[   VBIOS][0000:01:00.0] 0xa624[ ]: 		0x02559000
>[    0.400039] nouveau T[   VBIOS][0000:01:00.0] 0xa628[ ]: 		0x02669000 *
>[    0.400040] nouveau T[   VBIOS][0000:01:00.0] 0xa62c[ ]: 		0x02449000
>[    0.400041] nouveau T[   VBIOS][0000:01:00.0] 0xa630[ ]: 		0x02559000
>[    0.400041] nouveau T[   VBIOS][0000:01:00.0] 0xa634[ ]: 		0x02559000
>[    0.400042] nouveau T[   VBIOS][0000:01:00.0] 0xa638[ ]: 		0x0244a000
>[    0.400043] nouveau T[   VBIOS][0000:01:00.0] 0xa63c[ ]: 		0x0244a000
>[    0.400044] nouveau T[   VBIOS][0000:01:00.0] 0xa640[ ]: 	}
>[    0.400045] nouveau T[   VBIOS][0000:01:00.0] 0xa640[ ]: ZM_REG_SEQUENCE	0x02
>[    0.400046] nouveau T[   VBIOS][0000:01:00.0] 0xa646[ ]: 		R[0x11eb04] = 0x55550000
>[    0.400046] nouveau T[   VBIOS][0000:01:00.0] 0xa64a[ ]: 		R[0x11eb08] = 0x55550000
>[    0.400047] nouveau T[   VBIOS][0000:01:00.0] 0xa64e[ ]: ZM_REG	R[0x11e8d0] = 0x00330033
>[    0.400048] nouveau T[   VBIOS][0000:01:00.0] 0xa657[ ]: ZM_REG_SEQUENCE	0x02
>[    0.400049] nouveau T[   VBIOS][0000:01:00.0] 0xa65d[ ]: 		R[0x11e864] = 0x01010000
>[    0.400050] nouveau T[   VBIOS][0000:01:00.0] 0xa661[ ]: 		R[0x11e868] = 0x01011010
>[    0.400051] nouveau T[   VBIOS][0000:01:00.0] 0xa665[ ]: ZM_REG	R[0x11eb00] = 0x003c3c07
>[    0.400052] nouveau T[   VBIOS][0000:01:00.0] 0xa66e[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011ec20] 0x0c 0x08
>[    0.400053] nouveau T[   VBIOS][0000:01:00.0] 0xa675[ ]: 	R[0x11ec20] = {
>[    0.400054] nouveau T[   VBIOS][0000:01:00.0] 0xa675[ ]: 		0x05050505
>[    0.400054] nouveau T[   VBIOS][0000:01:00.0] 0xa679[ ]: 		0x05050505
>[    0.400055] nouveau T[   VBIOS][0000:01:00.0] 0xa67d[ ]: 		0x05050505 *
>[    0.400056] nouveau T[   VBIOS][0000:01:00.0] 0xa681[ ]: 		0x05050505
>[    0.400057] nouveau T[   VBIOS][0000:01:00.0] 0xa685[ ]: 		0x05050505
>[    0.400058] nouveau T[   VBIOS][0000:01:00.0] 0xa689[ ]: 		0x05050505
>[    0.400058] nouveau T[   VBIOS][0000:01:00.0] 0xa68d[ ]: 		0x05050505
>[    0.400059] nouveau T[   VBIOS][0000:01:00.0] 0xa691[ ]: 		0x05050505
>[    0.400060] nouveau T[   VBIOS][0000:01:00.0] 0xa695[ ]: 	}
>[    0.400061] nouveau T[   VBIOS][0000:01:00.0] 0xa695[ ]: 	R[0x11ec2c] = {
>[    0.400061] nouveau T[   VBIOS][0000:01:00.0] 0xa695[ ]: 		0x05050505
>[    0.400062] nouveau T[   VBIOS][0000:01:00.0] 0xa699[ ]: 		0x05050505
>[    0.400063] nouveau T[   VBIOS][0000:01:00.0] 0xa69d[ ]: 		0x05050505 *
>[    0.400064] nouveau T[   VBIOS][0000:01:00.0] 0xa6a1[ ]: 		0x05050505
>[    0.400065] nouveau T[   VBIOS][0000:01:00.0] 0xa6a5[ ]: 		0x05050505
>[    0.400065] nouveau T[   VBIOS][0000:01:00.0] 0xa6a9[ ]: 		0x05050505
>[    0.400066] nouveau T[   VBIOS][0000:01:00.0] 0xa6ad[ ]: 		0x05050505
>[    0.400067] nouveau T[   VBIOS][0000:01:00.0] 0xa6b1[ ]: 		0x05050505
>[    0.400068] nouveau T[   VBIOS][0000:01:00.0] 0xa6b5[ ]: 	}
>[    0.400068] nouveau T[   VBIOS][0000:01:00.0] 0xa6b5[ ]: 	R[0x11ec38] = {
>[    0.400069] nouveau T[   VBIOS][0000:01:00.0] 0xa6b5[ ]: 		0x05050505
>[    0.400070] nouveau T[   VBIOS][0000:01:00.0] 0xa6b9[ ]: 		0x05050505
>[    0.400071] nouveau T[   VBIOS][0000:01:00.0] 0xa6bd[ ]: 		0x05050505 *
>[    0.400072] nouveau T[   VBIOS][0000:01:00.0] 0xa6c1[ ]: 		0x05050505
>[    0.400072] nouveau T[   VBIOS][0000:01:00.0] 0xa6c5[ ]: 		0x05050505
>[    0.400073] nouveau T[   VBIOS][0000:01:00.0] 0xa6c9[ ]: 		0x05050505
>[    0.400074] nouveau T[   VBIOS][0000:01:00.0] 0xa6cd[ ]: 		0x05050505
>[    0.400075] nouveau T[   VBIOS][0000:01:00.0] 0xa6d1[ ]: 		0x05050505
>[    0.400075] nouveau T[   VBIOS][0000:01:00.0] 0xa6d5[ ]: 	}
>[    0.400076] nouveau T[   VBIOS][0000:01:00.0] 0xa6d5[ ]: 	R[0x11ec44] = {
>[    0.400077] nouveau T[   VBIOS][0000:01:00.0] 0xa6d5[ ]: 		0x05050505
>[    0.400078] nouveau T[   VBIOS][0000:01:00.0] 0xa6d9[ ]: 		0x05050505
>[    0.400079] nouveau T[   VBIOS][0000:01:00.0] 0xa6dd[ ]: 		0x05050505 *
>[    0.400079] nouveau T[   VBIOS][0000:01:00.0] 0xa6e1[ ]: 		0x05050505
>[    0.400080] nouveau T[   VBIOS][0000:01:00.0] 0xa6e5[ ]: 		0x05050505
>[    0.400081] nouveau T[   VBIOS][0000:01:00.0] 0xa6e9[ ]: 		0x05050505
>[    0.400082] nouveau T[   VBIOS][0000:01:00.0] 0xa6ed[ ]: 		0x05050505
>[    0.400082] nouveau T[   VBIOS][0000:01:00.0] 0xa6f1[ ]: 		0x05050505
>[    0.400083] nouveau T[   VBIOS][0000:01:00.0] 0xa6f5[ ]: 	}
>[    0.400084] nouveau T[   VBIOS][0000:01:00.0] 0xa6f5[ ]: 	R[0x11ec50] = {
>[    0.400085] nouveau T[   VBIOS][0000:01:00.0] 0xa6f5[ ]: 		0x05050505
>[    0.400086] nouveau T[   VBIOS][0000:01:00.0] 0xa6f9[ ]: 		0x05050505
>[    0.400086] nouveau T[   VBIOS][0000:01:00.0] 0xa6fd[ ]: 		0x05050505 *
>[    0.400087] nouveau T[   VBIOS][0000:01:00.0] 0xa701[ ]: 		0x05050505
>[    0.400088] nouveau T[   VBIOS][0000:01:00.0] 0xa705[ ]: 		0x05050505
>[    0.400089] nouveau T[   VBIOS][0000:01:00.0] 0xa709[ ]: 		0x05050505
>[    0.400089] nouveau T[   VBIOS][0000:01:00.0] 0xa70d[ ]: 		0x05050505
>[    0.400090] nouveau T[   VBIOS][0000:01:00.0] 0xa711[ ]: 		0x05050505
>[    0.400091] nouveau T[   VBIOS][0000:01:00.0] 0xa715[ ]: 	}
>[    0.400092] nouveau T[   VBIOS][0000:01:00.0] 0xa715[ ]: 	R[0x11ec5c] = {
>[    0.400093] nouveau T[   VBIOS][0000:01:00.0] 0xa715[ ]: 		0x05050505
>[    0.400093] nouveau T[   VBIOS][0000:01:00.0] 0xa719[ ]: 		0x05050505
>[    0.400094] nouveau T[   VBIOS][0000:01:00.0] 0xa71d[ ]: 		0x05050505 *
>[    0.400095] nouveau T[   VBIOS][0000:01:00.0] 0xa721[ ]: 		0x05050505
>[    0.400096] nouveau T[   VBIOS][0000:01:00.0] 0xa725[ ]: 		0x05050505
>[    0.400096] nouveau T[   VBIOS][0000:01:00.0] 0xa729[ ]: 		0x05050505
>[    0.400097] nouveau T[   VBIOS][0000:01:00.0] 0xa72d[ ]: 		0x05050505
>[    0.400098] nouveau T[   VBIOS][0000:01:00.0] 0xa731[ ]: 		0x05050505
>[    0.400099] nouveau T[   VBIOS][0000:01:00.0] 0xa735[ ]: 	}
>[    0.400100] nouveau T[   VBIOS][0000:01:00.0] 0xa735[ ]: 	R[0x11ec68] = {
>[    0.400100] nouveau T[   VBIOS][0000:01:00.0] 0xa735[ ]: 		0x05050505
>[    0.400101] nouveau T[   VBIOS][0000:01:00.0] 0xa739[ ]: 		0x05050505
>[    0.400102] nouveau T[   VBIOS][0000:01:00.0] 0xa73d[ ]: 		0x05050505 *
>[    0.400103] nouveau T[   VBIOS][0000:01:00.0] 0xa741[ ]: 		0x05050505
>[    0.400103] nouveau T[   VBIOS][0000:01:00.0] 0xa745[ ]: 		0x05050505
>[    0.400104] nouveau T[   VBIOS][0000:01:00.0] 0xa749[ ]: 		0x05050505
>[    0.400105] nouveau T[   VBIOS][0000:01:00.0] 0xa74d[ ]: 		0x05050505
>[    0.400106] nouveau T[   VBIOS][0000:01:00.0] 0xa751[ ]: 		0x05050505
>[    0.400107] nouveau T[   VBIOS][0000:01:00.0] 0xa755[ ]: 	}
>[    0.400107] nouveau T[   VBIOS][0000:01:00.0] 0xa755[ ]: 	R[0x11ec74] = {
>[    0.400108] nouveau T[   VBIOS][0000:01:00.0] 0xa755[ ]: 		0x05050505
>[    0.400109] nouveau T[   VBIOS][0000:01:00.0] 0xa759[ ]: 		0x05050505
>[    0.400110] nouveau T[   VBIOS][0000:01:00.0] 0xa75d[ ]: 		0x05050505 *
>[    0.400110] nouveau T[   VBIOS][0000:01:00.0] 0xa761[ ]: 		0x05050505
>[    0.400111] nouveau T[   VBIOS][0000:01:00.0] 0xa765[ ]: 		0x05050505
>[    0.400112] nouveau T[   VBIOS][0000:01:00.0] 0xa769[ ]: 		0x05050505
>[    0.400113] nouveau T[   VBIOS][0000:01:00.0] 0xa76d[ ]: 		0x05050505
>[    0.400114] nouveau T[   VBIOS][0000:01:00.0] 0xa771[ ]: 		0x05050505
>[    0.400114] nouveau T[   VBIOS][0000:01:00.0] 0xa775[ ]: 	}
>[    0.400115] nouveau T[   VBIOS][0000:01:00.0] 0xa775[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e724] 0x04 0x02
>[    0.400116] nouveau T[   VBIOS][0000:01:00.0] 0xa77c[ ]: 	R[0x11e724] = {
>[    0.400117] nouveau T[   VBIOS][0000:01:00.0] 0xa77c[ ]: 		0x00000000
>[    0.400118] nouveau T[   VBIOS][0000:01:00.0] 0xa780[ ]: 		0x00000000
>[    0.400118] nouveau T[   VBIOS][0000:01:00.0] 0xa784[ ]: 		0x00000000 *
>[    0.400119] nouveau T[   VBIOS][0000:01:00.0] 0xa788[ ]: 		0x00000000
>[    0.400120] nouveau T[   VBIOS][0000:01:00.0] 0xa78c[ ]: 		0x00000000
>[    0.400121] nouveau T[   VBIOS][0000:01:00.0] 0xa790[ ]: 		0x00000000
>[    0.400122] nouveau T[   VBIOS][0000:01:00.0] 0xa794[ ]: 		0x00000000
>[    0.400122] nouveau T[   VBIOS][0000:01:00.0] 0xa798[ ]: 		0x00000000
>[    0.400123] nouveau T[   VBIOS][0000:01:00.0] 0xa79c[ ]: 	}
>[    0.400124] nouveau T[   VBIOS][0000:01:00.0] 0xa79c[ ]: 	R[0x11e728] = {
>[    0.400125] nouveau T[   VBIOS][0000:01:00.0] 0xa79c[ ]: 		0x88888888
>[    0.400125] nouveau T[   VBIOS][0000:01:00.0] 0xa7a0[ ]: 		0x00000000
>[    0.400126] nouveau T[   VBIOS][0000:01:00.0] 0xa7a4[ ]: 		0x00000000 *
>[    0.400127] nouveau T[   VBIOS][0000:01:00.0] 0xa7a8[ ]: 		0x00000000
>[    0.400128] nouveau T[   VBIOS][0000:01:00.0] 0xa7ac[ ]: 		0x00000000
>[    0.400128] nouveau T[   VBIOS][0000:01:00.0] 0xa7b0[ ]: 		0x00000000
>[    0.400129] nouveau T[   VBIOS][0000:01:00.0] 0xa7b4[ ]: 		0x00000000
>[    0.400130] nouveau T[   VBIOS][0000:01:00.0] 0xa7b8[ ]: 		0x00000000
>[    0.400131] nouveau T[   VBIOS][0000:01:00.0] 0xa7bc[ ]: 	}
>[    0.400132] nouveau T[   VBIOS][0000:01:00.0] 0xa7bc[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001107a0] 0x0c 0x03
>[    0.400133] nouveau T[   VBIOS][0000:01:00.0] 0xa7c3[ ]: 	R[0x1107a0] = {
>[    0.400133] nouveau T[   VBIOS][0000:01:00.0] 0xa7c3[ ]: 		0x00000000
>[    0.400134] nouveau T[   VBIOS][0000:01:00.0] 0xa7c7[ ]: 		0x00000000
>[    0.400135] nouveau T[   VBIOS][0000:01:00.0] 0xa7cb[ ]: 		0x00000000 *
>[    0.400136] nouveau T[   VBIOS][0000:01:00.0] 0xa7cf[ ]: 		0x00000000
>[    0.400136] nouveau T[   VBIOS][0000:01:00.0] 0xa7d3[ ]: 		0x00000000
>[    0.400137] nouveau T[   VBIOS][0000:01:00.0] 0xa7d7[ ]: 		0x00000000
>[    0.400138] nouveau T[   VBIOS][0000:01:00.0] 0xa7db[ ]: 		0x00000000
>[    0.400139] nouveau T[   VBIOS][0000:01:00.0] 0xa7df[ ]: 		0x00000000
>[    0.400139] nouveau T[   VBIOS][0000:01:00.0] 0xa7e3[ ]: 	}
>[    0.400140] nouveau T[   VBIOS][0000:01:00.0] 0xa7e3[ ]: 	R[0x1107ac] = {
>[    0.400141] nouveau T[   VBIOS][0000:01:00.0] 0xa7e3[ ]: 		0x55555555
>[    0.400142] nouveau T[   VBIOS][0000:01:00.0] 0xa7e7[ ]: 		0x55555555
>[    0.400143] nouveau T[   VBIOS][0000:01:00.0] 0xa7eb[ ]: 		0x55555555 *
>[    0.400143] nouveau T[   VBIOS][0000:01:00.0] 0xa7ef[ ]: 		0x55555555
>[    0.400144] nouveau T[   VBIOS][0000:01:00.0] 0xa7f3[ ]: 		0x55555555
>[    0.400145] nouveau T[   VBIOS][0000:01:00.0] 0xa7f7[ ]: 		0x55555555
>[    0.400146] nouveau T[   VBIOS][0000:01:00.0] 0xa7fb[ ]: 		0x55555555
>[    0.400147] nouveau T[   VBIOS][0000:01:00.0] 0xa7ff[ ]: 		0x55555555
>[    0.400147] nouveau T[   VBIOS][0000:01:00.0] 0xa803[ ]: 	}
>[    0.400148] nouveau T[   VBIOS][0000:01:00.0] 0xa803[ ]: 	R[0x1107b8] = {
>[    0.400149] nouveau T[   VBIOS][0000:01:00.0] 0xa803[ ]: 		0x00000000
>[    0.400150] nouveau T[   VBIOS][0000:01:00.0] 0xa807[ ]: 		0x22222222
>[    0.400150] nouveau T[   VBIOS][0000:01:00.0] 0xa80b[ ]: 		0x00000000 *
>[    0.400151] nouveau T[   VBIOS][0000:01:00.0] 0xa80f[ ]: 		0x00000000
>[    0.400152] nouveau T[   VBIOS][0000:01:00.0] 0xa813[ ]: 		0x00000000
>[    0.400153] nouveau T[   VBIOS][0000:01:00.0] 0xa817[ ]: 		0x00000000
>[    0.400154] nouveau T[   VBIOS][0000:01:00.0] 0xa81b[ ]: 		0x00000000
>[    0.400154] nouveau T[   VBIOS][0000:01:00.0] 0xa81f[ ]: 		0x00000000
>[    0.400155] nouveau T[   VBIOS][0000:01:00.0] 0xa823[ ]: 	}
>[    0.400156] nouveau T[   VBIOS][0000:01:00.0] 0xa823[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001117a0] 0x0c 0x03
>[    0.400157] nouveau T[   VBIOS][0000:01:00.0] 0xa82a[ ]: 	R[0x1117a0] = {
>[    0.400158] nouveau T[   VBIOS][0000:01:00.0] 0xa82a[ ]: 		0x00000000
>[    0.400158] nouveau T[   VBIOS][0000:01:00.0] 0xa82e[ ]: 		0x00000000
>[    0.400159] nouveau T[   VBIOS][0000:01:00.0] 0xa832[ ]: 		0x00000000 *
>[    0.400160] nouveau T[   VBIOS][0000:01:00.0] 0xa836[ ]: 		0x00000000
>[    0.400161] nouveau T[   VBIOS][0000:01:00.0] 0xa83a[ ]: 		0x00000000
>[    0.400161] nouveau T[   VBIOS][0000:01:00.0] 0xa83e[ ]: 		0x00000000
>[    0.400162] nouveau T[   VBIOS][0000:01:00.0] 0xa842[ ]: 		0x00000000
>[    0.400163] nouveau T[   VBIOS][0000:01:00.0] 0xa846[ ]: 		0x00000000
>[    0.400164] nouveau T[   VBIOS][0000:01:00.0] 0xa84a[ ]: 	}
>[    0.400165] nouveau T[   VBIOS][0000:01:00.0] 0xa84a[ ]: 	R[0x1117ac] = {
>[    0.400165] nouveau T[   VBIOS][0000:01:00.0] 0xa84a[ ]: 		0x55555555
>[    0.400166] nouveau T[   VBIOS][0000:01:00.0] 0xa84e[ ]: 		0x55555555
>[    0.400167] nouveau T[   VBIOS][0000:01:00.0] 0xa852[ ]: 		0x55555555 *
>[    0.400168] nouveau T[   VBIOS][0000:01:00.0] 0xa856[ ]: 		0x55555555
>[    0.400169] nouveau T[   VBIOS][0000:01:00.0] 0xa85a[ ]: 		0x55555555
>[    0.400169] nouveau T[   VBIOS][0000:01:00.0] 0xa85e[ ]: 		0x55555555
>[    0.400170] nouveau T[   VBIOS][0000:01:00.0] 0xa862[ ]: 		0x55555555
>[    0.400171] nouveau T[   VBIOS][0000:01:00.0] 0xa866[ ]: 		0x55555555
>[    0.400172] nouveau T[   VBIOS][0000:01:00.0] 0xa86a[ ]: 	}
>[    0.400172] nouveau T[   VBIOS][0000:01:00.0] 0xa86a[ ]: 	R[0x1117b8] = {
>[    0.400173] nouveau T[   VBIOS][0000:01:00.0] 0xa86a[ ]: 		0x00000000
>[    0.400174] nouveau T[   VBIOS][0000:01:00.0] 0xa86e[ ]: 		0x22222222
>[    0.400175] nouveau T[   VBIOS][0000:01:00.0] 0xa872[ ]: 		0x00000000 *
>[    0.400176] nouveau T[   VBIOS][0000:01:00.0] 0xa876[ ]: 		0x00000000
>[    0.400176] nouveau T[   VBIOS][0000:01:00.0] 0xa87a[ ]: 		0x00000000
>[    0.400177] nouveau T[   VBIOS][0000:01:00.0] 0xa87e[ ]: 		0x00000000
>[    0.400178] nouveau T[   VBIOS][0000:01:00.0] 0xa882[ ]: 		0x00000000
>[    0.400179] nouveau T[   VBIOS][0000:01:00.0] 0xa886[ ]: 		0x00000000
>[    0.400179] nouveau T[   VBIOS][0000:01:00.0] 0xa88a[ ]: 	}
>[    0.400180] nouveau T[   VBIOS][0000:01:00.0] 0xa88a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00110d38] 0x04 0x01
>[    0.400181] nouveau T[   VBIOS][0000:01:00.0] 0xa891[ ]: 	R[0x110d38] = {
>[    0.400182] nouveau T[   VBIOS][0000:01:00.0] 0xa891[ ]: 		0x55555555
>[    0.400183] nouveau T[   VBIOS][0000:01:00.0] 0xa895[ ]: 		0x55555555
>[    0.400184] nouveau T[   VBIOS][0000:01:00.0] 0xa899[ ]: 		0x54554555 *
>[    0.400184] nouveau T[   VBIOS][0000:01:00.0] 0xa89d[ ]: 		0x55555555
>[    0.400185] nouveau T[   VBIOS][0000:01:00.0] 0xa8a1[ ]: 		0x55555555
>[    0.400186] nouveau T[   VBIOS][0000:01:00.0] 0xa8a5[ ]: 		0x54554555
>[    0.400187] nouveau T[   VBIOS][0000:01:00.0] 0xa8a9[ ]: 		0x55555555
>[    0.400187] nouveau T[   VBIOS][0000:01:00.0] 0xa8ad[ ]: 		0x55555555
>[    0.400188] nouveau T[   VBIOS][0000:01:00.0] 0xa8b1[ ]: 	}
>[    0.400189] nouveau T[   VBIOS][0000:01:00.0] 0xa8b1[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111d38] 0x04 0x01
>[    0.400190] nouveau T[   VBIOS][0000:01:00.0] 0xa8b8[ ]: 	R[0x111d38] = {
>[    0.400191] nouveau T[   VBIOS][0000:01:00.0] 0xa8b8[ ]: 		0x55555555
>[    0.400192] nouveau T[   VBIOS][0000:01:00.0] 0xa8bc[ ]: 		0x55555555
>[    0.400192] nouveau T[   VBIOS][0000:01:00.0] 0xa8c0[ ]: 		0x34434454 *
>[    0.400193] nouveau T[   VBIOS][0000:01:00.0] 0xa8c4[ ]: 		0x55555555
>[    0.400194] nouveau T[   VBIOS][0000:01:00.0] 0xa8c8[ ]: 		0x55555555
>[    0.400195] nouveau T[   VBIOS][0000:01:00.0] 0xa8cc[ ]: 		0x34434454
>[    0.400196] nouveau T[   VBIOS][0000:01:00.0] 0xa8d0[ ]: 		0x55555555
>[    0.400196] nouveau T[   VBIOS][0000:01:00.0] 0xa8d4[ ]: 		0x55555555
>[    0.400197] nouveau T[   VBIOS][0000:01:00.0] 0xa8d8[ ]: 	}
>[    0.400198] nouveau T[   VBIOS][0000:01:00.0] 0xa8d8[ ]: NV_REG	R[0x11e200] &= 0xffffefff |= 0x00001000
>[    0.400199] nouveau T[   VBIOS][0000:01:00.0] 0xa8e5[ ]: NV_REG	R[0x11e808] &= 0xfcffffff |= 0x02000000
>[    0.400200] nouveau T[   VBIOS][0000:01:00.0] 0xa8f2[ ]: CONDITION	0x28
>[    0.400201] nouveau T[   VBIOS][0000:01:00.0] 0xa8f4[ ]: 	[0x28] (R[0x001590] & 0x00000008) == 0x00000008
>[    0.400202] nouveau T[   VBIOS][0000:01:00.0] 0xa8f4[ ]: NOT
>[    0.400203] nouveau T[   VBIOS][0000:01:00.0] 0xa8f5[ ]: TIME	0x0064
>[    0.400204] nouveau T[   VBIOS][0000:01:00.0] 0xa8f8[ ]: RESUME
>[    0.400204] nouveau T[   VBIOS][0000:01:00.0] 0xa8f9[ ]: ZM_REG	R[0x11e218] = 0x01001001
>[    0.400205] nouveau T[   VBIOS][0000:01:00.0] 0xa902[ ]: ZM_REG	R[0x11e21c] = 0x00000001
>[    0.400206] nouveau T[   VBIOS][0000:01:00.0] 0xa90b[ ]: ZM_REG	R[0x11e218] = 0x01001101
>[    0.400207] nouveau T[   VBIOS][0000:01:00.0] 0xa914[ ]: CONDITION	0x28
>[    0.400208] nouveau T[   VBIOS][0000:01:00.0] 0xa916[ ]: 	[0x28] (R[0x001590] & 0x00000008) == 0x00000008
>[    0.400209] nouveau T[   VBIOS][0000:01:00.0] 0xa916[ ]: NOT
>[    0.400210] nouveau T[   VBIOS][0000:01:00.0] 0xa917[ ]: TIME	0x00c8
>[    0.400210] nouveau T[   VBIOS][0000:01:00.0] 0xa91a[ ]: RESUME
>[    0.400211] nouveau T[   VBIOS][0000:01:00.0] 0xa91b[ ]: ZM_REG	R[0x11e218] = 0x01001101
>[    0.400212] nouveau T[   VBIOS][0000:01:00.0] 0xa924[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e808] 0x04 0x01
>[    0.400213] nouveau T[   VBIOS][0000:01:00.0] 0xa92b[ ]: 	R[0x11e808] = {
>[    0.400214] nouveau T[   VBIOS][0000:01:00.0] 0xa92b[ ]: 		0x48000070
>[    0.400215] nouveau T[   VBIOS][0000:01:00.0] 0xa92f[ ]: 		0x48000070
>[    0.400216] nouveau T[   VBIOS][0000:01:00.0] 0xa933[ ]: 		0x48000070 *
>[    0.400216] nouveau T[   VBIOS][0000:01:00.0] 0xa937[ ]: 		0x48000070
>[    0.400217] nouveau T[   VBIOS][0000:01:00.0] 0xa93b[ ]: 		0x48000070
>[    0.400218] nouveau T[   VBIOS][0000:01:00.0] 0xa93f[ ]: 		0x48000070
>[    0.400219] nouveau T[   VBIOS][0000:01:00.0] 0xa943[ ]: 		0x48000070
>[    0.400219] nouveau T[   VBIOS][0000:01:00.0] 0xa947[ ]: 		0x48000070
>[    0.400220] nouveau T[   VBIOS][0000:01:00.0] 0xa94b[ ]: 	}
>[    0.400221] nouveau T[   VBIOS][0000:01:00.0] 0xa94b[ ]: MACRO	0x05
>[    0.400222] nouveau T[   VBIOS][0000:01:00.0] 0xa94b[ ]: 		R[0x11e318] = 0x00000001
>[    0.400223] nouveau T[   VBIOS][0000:01:00.0] 0xa94d[ ]: MACRO	0x05
>[    0.400224] nouveau T[   VBIOS][0000:01:00.0] 0xa94d[ ]: 		R[0x11e318] = 0x00000001
>[    0.400225] nouveau T[   VBIOS][0000:01:00.0] 0xa94f[ ]: MACRO	0x03
>[    0.400226] nouveau T[   VBIOS][0000:01:00.0] 0xa94f[ ]: 		R[0x11e314] = 0x00000001
>[    0.400226] nouveau T[   VBIOS][0000:01:00.0] 0xa951[ ]: REPEAT	0x05
>[    0.400227] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: MACRO	0x05
>[    0.400228] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: 		R[0x11e318] = 0x00000001
>[    0.400229] nouveau T[   VBIOS][0000:01:00.0] 0xa955[ ]: END_REPEAT
>[    0.400230] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[    0.400231] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: MACRO	0x05
>[    0.400231] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: 		R[0x11e318] = 0x00000001
>[    0.400232] nouveau T[   VBIOS][0000:01:00.0] 0xa955[ ]: END_REPEAT
>[    0.400233] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[    0.400234] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: MACRO	0x05
>[    0.400235] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: 		R[0x11e318] = 0x00000001
>[    0.400235] nouveau T[   VBIOS][0000:01:00.0] 0xa955[ ]: END_REPEAT
>[    0.400236] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[    0.400237] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: MACRO	0x05
>[    0.400238] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: 		R[0x11e318] = 0x00000001
>[    0.400239] nouveau T[   VBIOS][0000:01:00.0] 0xa955[ ]: END_REPEAT
>[    0.400239] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[    0.400240] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: MACRO	0x05
>[    0.400241] nouveau T[   VBIOS][0000:01:00.0] 0xa953[ ]: 		R[0x11e318] = 0x00000001
>[    0.400242] nouveau T[   VBIOS][0000:01:00.0] 0xa955[ ]: END_REPEAT
>[    0.400243] nouveau T[   VBIOS][0000:01:00.0] 0xa956[ ]: ZM_REG	R[0x11e34c] = 0x00f00000
>[    0.400244] nouveau T[   VBIOS][0000:01:00.0] 0xa95f[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e338] 0x04 0x01
>[    0.400245] nouveau T[   VBIOS][0000:01:00.0] 0xa966[ ]: 	R[0x11e338] = {
>[    0.400245] nouveau T[   VBIOS][0000:01:00.0] 0xa966[ ]: 		0x00300120
>[    0.400246] nouveau T[   VBIOS][0000:01:00.0] 0xa96a[ ]: 		0x00300120
>[    0.400247] nouveau T[   VBIOS][0000:01:00.0] 0xa96e[ ]: 		0x00300120 *
>[    0.400248] nouveau T[   VBIOS][0000:01:00.0] 0xa972[ ]: 		0x00300220
>[    0.400249] nouveau T[   VBIOS][0000:01:00.0] 0xa976[ ]: 		0x00300120
>[    0.400249] nouveau T[   VBIOS][0000:01:00.0] 0xa97a[ ]: 		0x00300120
>[    0.400250] nouveau T[   VBIOS][0000:01:00.0] 0xa97e[ ]: 		0x00300220
>[    0.400251] nouveau T[   VBIOS][0000:01:00.0] 0xa982[ ]: 		0x00300220
>[    0.400252] nouveau T[   VBIOS][0000:01:00.0] 0xa986[ ]: 	}
>[    0.400253] nouveau T[   VBIOS][0000:01:00.0] 0xa986[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e330] 0x04 0x01
>[    0.400254] nouveau T[   VBIOS][0000:01:00.0] 0xa98d[ ]: 	R[0x11e330] = {
>[    0.400254] nouveau T[   VBIOS][0000:01:00.0] 0xa98d[ ]: 		0x00100030
>[    0.400255] nouveau T[   VBIOS][0000:01:00.0] 0xa991[ ]: 		0x00100030
>[    0.400256] nouveau T[   VBIOS][0000:01:00.0] 0xa995[ ]: 		0x00100030 *
>[    0.400257] nouveau T[   VBIOS][0000:01:00.0] 0xa999[ ]: 		0x00100070
>[    0.400257] nouveau T[   VBIOS][0000:01:00.0] 0xa99d[ ]: 		0x00100030
>[    0.400258] nouveau T[   VBIOS][0000:01:00.0] 0xa9a1[ ]: 		0x00100030
>[    0.400259] nouveau T[   VBIOS][0000:01:00.0] 0xa9a5[ ]: 		0x00100030
>[    0.400260] nouveau T[   VBIOS][0000:01:00.0] 0xa9a9[ ]: 		0x00100030
>[    0.400261] nouveau T[   VBIOS][0000:01:00.0] 0xa9ad[ ]: 	}
>[    0.400261] nouveau T[   VBIOS][0000:01:00.0] 0xa9ad[ ]: CONDITION	0x1d
>[    0.400262] nouveau T[   VBIOS][0000:01:00.0] 0xa9af[ ]: 	[0x1d] (R[0x11e60c] & 0x00000040) == 0x00000040
>[    0.400263] nouveau T[   VBIOS][0000:01:00.0] 0xa9af[ ]: NV_REG	R[0x00d638] &= 0xffffcfff |= 0x00003000
>[    0.400265] nouveau T[   VBIOS][0000:01:00.0] 0xa9bc[ ]: NV_REG	R[0x00d604] &= 0xfffffffe |= 0x00000001
>[    0.400265] nouveau T[   VBIOS][0000:01:00.0] 0xa9c9[ ]: TIME	0x0014
>[    0.400266] nouveau T[   VBIOS][0000:01:00.0] 0xa9cc[ ]: RESUME
>[    0.400267] nouveau T[   VBIOS][0000:01:00.0] 0xa9cd[ ]: ZM_REG	R[0x11e354] = 0x00800000
>[    0.400268] nouveau T[   VBIOS][0000:01:00.0] 0xa9d6[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e300] 0x04 0x01
>[    0.400269] nouveau T[   VBIOS][0000:01:00.0] 0xa9dd[ ]: 	R[0x11e300] = {
>[    0.400270] nouveau T[   VBIOS][0000:01:00.0] 0xa9dd[ ]: 		0x00000125
>[    0.400270] nouveau T[   VBIOS][0000:01:00.0] 0xa9e1[ ]: 		0x00000125
>[    0.400271] nouveau T[   VBIOS][0000:01:00.0] 0xa9e5[ ]: 		0x00000025 *
>[    0.400272] nouveau T[   VBIOS][0000:01:00.0] 0xa9e9[ ]: 		0x00000025
>[    0.400273] nouveau T[   VBIOS][0000:01:00.0] 0xa9ed[ ]: 		0x00000125
>[    0.400274] nouveau T[   VBIOS][0000:01:00.0] 0xa9f1[ ]: 		0x00000015
>[    0.400274] nouveau T[   VBIOS][0000:01:00.0] 0xa9f5[ ]: 		0x00000025
>[    0.400275] nouveau T[   VBIOS][0000:01:00.0] 0xa9f9[ ]: 		0x00000025
>[    0.400276] nouveau T[   VBIOS][0000:01:00.0] 0xa9fd[ ]: 	}
>[    0.400277] nouveau T[   VBIOS][0000:01:00.0] 0xa9fd[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e33c] 0x04 0x01
>[    0.400278] nouveau T[   VBIOS][0000:01:00.0] 0xaa04[ ]: 	R[0x11e33c] = {
>[    0.400278] nouveau T[   VBIOS][0000:01:00.0] 0xaa04[ ]: 		0x0040077f
>[    0.400279] nouveau T[   VBIOS][0000:01:00.0] 0xaa08[ ]: 		0x0040077f
>[    0.400280] nouveau T[   VBIOS][0000:01:00.0] 0xaa0c[ ]: 		0x0040077f *
>[    0.400281] nouveau T[   VBIOS][0000:01:00.0] 0xaa10[ ]: 		0x0040077f
>[    0.400282] nouveau T[   VBIOS][0000:01:00.0] 0xaa14[ ]: 		0x0040077f
>[    0.400282] nouveau T[   VBIOS][0000:01:00.0] 0xaa18[ ]: 		0x004007df
>[    0.400283] nouveau T[   VBIOS][0000:01:00.0] 0xaa1c[ ]: 		0x0040077f
>[    0.400284] nouveau T[   VBIOS][0000:01:00.0] 0xaa20[ ]: 		0x0040077f
>[    0.400285] nouveau T[   VBIOS][0000:01:00.0] 0xaa24[ ]: 	}
>[    0.400286] nouveau T[   VBIOS][0000:01:00.0] 0xaa24[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e334] 0x04 0x01
>[    0.400286] nouveau T[   VBIOS][0000:01:00.0] 0xaa2b[ ]: 	R[0x11e334] = {
>[    0.400287] nouveau T[   VBIOS][0000:01:00.0] 0xaa2b[ ]: 		0x0020001b
>[    0.400288] nouveau T[   VBIOS][0000:01:00.0] 0xaa2f[ ]: 		0x0020001b
>[    0.400289] nouveau T[   VBIOS][0000:01:00.0] 0xaa33[ ]: 		0x0020001b *
>[    0.400290] nouveau T[   VBIOS][0000:01:00.0] 0xaa37[ ]: 		0x0020001b
>[    0.400290] nouveau T[   VBIOS][0000:01:00.0] 0xaa3b[ ]: 		0x0020001b
>[    0.400291] nouveau T[   VBIOS][0000:01:00.0] 0xaa3f[ ]: 		0x00200000
>[    0.400292] nouveau T[   VBIOS][0000:01:00.0] 0xaa43[ ]: 		0x0020001b
>[    0.400293] nouveau T[   VBIOS][0000:01:00.0] 0xaa47[ ]: 		0x0020001b
>[    0.400293] nouveau T[   VBIOS][0000:01:00.0] 0xaa4b[ ]: 	}
>[    0.400294] nouveau T[   VBIOS][0000:01:00.0] 0xaa4b[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e340] 0x04 0x01
>[    0.400295] nouveau T[   VBIOS][0000:01:00.0] 0xaa52[ ]: 	R[0x11e340] = {
>[    0.400296] nouveau T[   VBIOS][0000:01:00.0] 0xaa52[ ]: 		0x00500240
>[    0.400297] nouveau T[   VBIOS][0000:01:00.0] 0xaa56[ ]: 		0x00500000
>[    0.400298] nouveau T[   VBIOS][0000:01:00.0] 0xaa5a[ ]: 		0x00500000 *
>[    0.400298] nouveau T[   VBIOS][0000:01:00.0] 0xaa5e[ ]: 		0x00500000
>[    0.400299] nouveau T[   VBIOS][0000:01:00.0] 0xaa62[ ]: 		0x00500000
>[    0.400300] nouveau T[   VBIOS][0000:01:00.0] 0xaa66[ ]: 		0x00500180
>[    0.400301] nouveau T[   VBIOS][0000:01:00.0] 0xaa6a[ ]: 		0x00500000
>[    0.400301] nouveau T[   VBIOS][0000:01:00.0] 0xaa6e[ ]: 		0x00500000
>[    0.400302] nouveau T[   VBIOS][0000:01:00.0] 0xaa72[ ]: 	}
>[    0.400303] nouveau T[   VBIOS][0000:01:00.0] 0xaa72[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e344] 0x04 0x01
>[    0.400304] nouveau T[   VBIOS][0000:01:00.0] 0xaa79[ ]: 	R[0x11e344] = {
>[    0.400305] nouveau T[   VBIOS][0000:01:00.0] 0xaa79[ ]: 		0x00600008
>[    0.400306] nouveau T[   VBIOS][0000:01:00.0] 0xaa7d[ ]: 		0x00600008
>[    0.400306] nouveau T[   VBIOS][0000:01:00.0] 0xaa81[ ]: 		0x00600008 *
>[    0.400307] nouveau T[   VBIOS][0000:01:00.0] 0xaa85[ ]: 		0x00600008
>[    0.400308] nouveau T[   VBIOS][0000:01:00.0] 0xaa89[ ]: 		0x00600008
>[    0.400309] nouveau T[   VBIOS][0000:01:00.0] 0xaa8d[ ]: 		0x00600008
>[    0.400309] nouveau T[   VBIOS][0000:01:00.0] 0xaa91[ ]: 		0x00600008
>[    0.400310] nouveau T[   VBIOS][0000:01:00.0] 0xaa95[ ]: 		0x00600008
>[    0.400311] nouveau T[   VBIOS][0000:01:00.0] 0xaa99[ ]: 	}
>[    0.400312] nouveau T[   VBIOS][0000:01:00.0] 0xaa99[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e348] 0x04 0x01
>[    0.400313] nouveau T[   VBIOS][0000:01:00.0] 0xaaa0[ ]: 	R[0x11e348] = {
>[    0.400314] nouveau T[   VBIOS][0000:01:00.0] 0xaaa0[ ]: 		0x00700188
>[    0.400314] nouveau T[   VBIOS][0000:01:00.0] 0xaaa4[ ]: 		0x00700188
>[    0.400315] nouveau T[   VBIOS][0000:01:00.0] 0xaaa8[ ]: 		0x00700188 *
>[    0.400316] nouveau T[   VBIOS][0000:01:00.0] 0xaaac[ ]: 		0x00700188
>[    0.400317] nouveau T[   VBIOS][0000:01:00.0] 0xaab0[ ]: 		0x00700188
>[    0.400317] nouveau T[   VBIOS][0000:01:00.0] 0xaab4[ ]: 		0x00700188
>[    0.400318] nouveau T[   VBIOS][0000:01:00.0] 0xaab8[ ]: 		0x00700188
>[    0.400319] nouveau T[   VBIOS][0000:01:00.0] 0xaabc[ ]: 		0x00700188
>[    0.400320] nouveau T[   VBIOS][0000:01:00.0] 0xaac0[ ]: 	}
>[    0.400321] nouveau T[   VBIOS][0000:01:00.0] 0xaac0[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e358] 0x04 0x01
>[    0.400322] nouveau T[   VBIOS][0000:01:00.0] 0xaac7[ ]: 	R[0x11e358] = {
>[    0.400322] nouveau T[   VBIOS][0000:01:00.0] 0xaac7[ ]: 		0x00900000
>[    0.400323] nouveau T[   VBIOS][0000:01:00.0] 0xaacb[ ]: 		0x00900000
>[    0.400324] nouveau T[   VBIOS][0000:01:00.0] 0xaacf[ ]: 		0x00900000 *
>[    0.400325] nouveau T[   VBIOS][0000:01:00.0] 0xaad3[ ]: 		0x00900000
>[    0.400326] nouveau T[   VBIOS][0000:01:00.0] 0xaad7[ ]: 		0x00900000
>[    0.400326] nouveau T[   VBIOS][0000:01:00.0] 0xaadb[ ]: 		0x00900000
>[    0.400327] nouveau T[   VBIOS][0000:01:00.0] 0xaadf[ ]: 		0x00900000
>[    0.400328] nouveau T[   VBIOS][0000:01:00.0] 0xaae3[ ]: 		0x00900000
>[    0.400329] nouveau T[   VBIOS][0000:01:00.0] 0xaae7[ ]: 	}
>[    0.400330] nouveau T[   VBIOS][0000:01:00.0] 0xaae7[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e35c] 0x04 0x01
>[    0.400330] nouveau T[   VBIOS][0000:01:00.0] 0xaaee[ ]: 	R[0x11e35c] = {
>[    0.400331] nouveau T[   VBIOS][0000:01:00.0] 0xaaee[ ]: 		0x00e00000
>[    0.400332] nouveau T[   VBIOS][0000:01:00.0] 0xaaf2[ ]: 		0x00e00000
>[    0.400333] nouveau T[   VBIOS][0000:01:00.0] 0xaaf6[ ]: 		0x00e00000 *
>[    0.400334] nouveau T[   VBIOS][0000:01:00.0] 0xaafa[ ]: 		0x00e00000
>[    0.400334] nouveau T[   VBIOS][0000:01:00.0] 0xaafe[ ]: 		0x00e00000
>[    0.400335] nouveau T[   VBIOS][0000:01:00.0] 0xab02[ ]: 		0x00e00000
>[    0.400336] nouveau T[   VBIOS][0000:01:00.0] 0xab06[ ]: 		0x00e00000
>[    0.400337] nouveau T[   VBIOS][0000:01:00.0] 0xab0a[ ]: 		0x00e00000
>[    0.400337] nouveau T[   VBIOS][0000:01:00.0] 0xab0e[ ]: 	}
>[    0.400338] nouveau T[   VBIOS][0000:01:00.0] 0xab0e[ ]: CONDITION	0x1c
>[    0.400339] nouveau T[   VBIOS][0000:01:00.0] 0xab10[ ]: 	[0x1c] (R[0x11e050] & 0x80000000) == 0x00000000
>[    0.400340] nouveau T[   VBIOS][0000:01:00.0] 0xab10[ ]: SUB_DIRECT	0xafc9
>[    0.400341] nouveau T[   VBIOS][0000:01:00.0] 0xab13[ ]: RESUME
>[    0.400342] nouveau T[   VBIOS][0000:01:00.0] 0xab14[ ]: MACRO	0x04
>[    0.400343] nouveau T[   VBIOS][0000:01:00.0] 0xab14[ ]: 		R[0x11e310] = 0x00000001
>[    0.400344] nouveau T[   VBIOS][0000:01:00.0] 0xab16[ ]: MACRO	0x04
>[    0.400344] nouveau T[   VBIOS][0000:01:00.0] 0xab16[ ]: 		R[0x11e310] = 0x00000001
>[    0.400345] nouveau T[   VBIOS][0000:01:00.0] 0xab18[ ]: CONDITION	0x28
>[    0.400346] nouveau T[   VBIOS][0000:01:00.0] 0xab1a[ ]: 	[0x28] (R[0x001590] & 0x00000008) == 0x00000008
>[    0.400347] nouveau T[   VBIOS][0000:01:00.0] 0xab1a[ ]: NOT
>[    0.400348] nouveau T[   VBIOS][0000:01:00.0] 0xab1b[ ]: TIME	0x03e8
>[    0.400349] nouveau T[   VBIOS][0000:01:00.0] 0xab1e[ ]: RESUME
>[    0.400350] nouveau T[   VBIOS][0000:01:00.0] 0xab1f[ ]: CONDITION	0x28
>[    0.400351] nouveau T[   VBIOS][0000:01:00.0] 0xab21[ ]: 	[0x28] (R[0x001590] & 0x00000008) == 0x00000008
>[    0.400351] nouveau T[   VBIOS][0000:01:00.0] 0xab21[ ]: SUB_DIRECT	0xaff8
>[    0.400352] nouveau T[   VBIOS][0000:01:00.0] 0xab24[ ]: RESUME
>[    0.400353] nouveau T[   VBIOS][0000:01:00.0] 0xab25[ ]: ZM_REG	R[0x11e210] = 0x80000000
>[    0.400354] nouveau T[   VBIOS][0000:01:00.0] 0xab2e[ ]: ZM_REG	R[0x11e500] = 0x80200015
>[    0.400355] nouveau T[   VBIOS][0000:01:00.0] 0xab37[ ]: ZM_REG	R[0x11e9a4] = 0x00051f00
>[    0.400356] nouveau T[   VBIOS][0000:01:00.0] 0xab40[ ]: ZM_REG	R[0x11e9ac] = 0x00000000
>[    0.400357] nouveau T[   VBIOS][0000:01:00.0] 0xab49[ ]: NV_REG	R[0x11e99c] &= 0xff80ffff |= 0x00010000
>[    0.400358] nouveau T[   VBIOS][0000:01:00.0] 0xab56[ ]: NV_REG	R[0x11e9a0] &= 0xf0f0ffff |= 0x02020000
>[    0.400359] nouveau T[   VBIOS][0000:01:00.0] 0xab63[ ]: ZM_REG	R[0x11e978] = 0x887a3e09
>[    0.400360] nouveau T[   VBIOS][0000:01:00.0] 0xab6c[ ]: ZM_REG	R[0x11e988] = 0x2001ff00
>[    0.400360] nouveau T[   VBIOS][0000:01:00.0] 0xab75[ ]: ZM_REG	R[0x11e9cc] = 0x80180080
>[    0.400361] nouveau T[   VBIOS][0000:01:00.0] 0xab7e[ ]: ZM_REG	R[0x11e9d0] = 0x05015000
>[    0.400362] nouveau T[   VBIOS][0000:01:00.0] 0xab87[ ]: ZM_REG	R[0x11e9d4] = 0x02047f81
>[    0.400363] nouveau T[   VBIOS][0000:01:00.0] 0xab90[ ]: ZM_REG	R[0x11e9d8] = 0x2010f000
>[    0.400364] nouveau T[   VBIOS][0000:01:00.0] 0xab99[ ]: ZM_REG	R[0x11e9dc] = 0x20017f00
>[    0.400365] nouveau T[   VBIOS][0000:01:00.0] 0xaba2[ ]: ZM_REG	R[0x11e9e0] = 0x20000000
>[    0.400366] nouveau T[   VBIOS][0000:01:00.0] 0xabab[ ]: ZM_REG	R[0x11e9e4] = 0x00001113
>[    0.400367] nouveau T[   VBIOS][0000:01:00.0] 0xabb4[ ]: ZM_REG	R[0x11e9e8] = 0x000001f0
>[    0.400367] nouveau T[   VBIOS][0000:01:00.0] 0xabbd[ ]: ZM_REG	R[0x11e9ec] = 0x01022858
>[    0.400368] nouveau T[   VBIOS][0000:01:00.0] 0xabc6[ ]: ZM_REG	R[0x11e984] = 0x00000900
>[    0.400369] nouveau T[   VBIOS][0000:01:00.0] 0xabcf[ ]: ZM_REG	R[0x11e994] = 0x00000005
>[    0.400370] nouveau T[   VBIOS][0000:01:00.0] 0xabd8[ ]: ZM_REG	R[0x11e998] = 0x00011b00
>[    0.400371] nouveau T[   VBIOS][0000:01:00.0] 0xabe1[ ]: ZM_REG	R[0x11e9a8] = 0x00010700
>[    0.400372] nouveau T[   VBIOS][0000:01:00.0] 0xabea[ ]: ZM_REG	R[0x11e9b0] = 0x05513f41
>[    0.400373] nouveau T[   VBIOS][0000:01:00.0] 0xabf3[ ]: ZM_REG	R[0x11e9f0] = 0x05513f41
>[    0.400374] nouveau T[   VBIOS][0000:01:00.0] 0xabfc[ ]: ZM_REG	R[0x11e98c] = 0x00000040
>[    0.400375] nouveau T[   VBIOS][0000:01:00.0] 0xac05[ ]: ZM_REG	R[0x11e990] = 0x00000000
>[    0.400375] nouveau T[   VBIOS][0000:01:00.0] 0xac0e[ ]: ZM_REG	R[0x11e910] = 0x88020000
>[    0.400376] nouveau T[   VBIOS][0000:01:00.0] 0xac17[ ]: ZM_REG	R[0x11e914] = 0x88020000
>[    0.400377] nouveau T[   VBIOS][0000:01:00.0] 0xac20[ ]: TIME	0x0064
>[    0.400378] nouveau T[   VBIOS][0000:01:00.0] 0xac23[ ]: NV_REG	R[0x11e470] &= 0xffffffff |= 0x00000000
>[    0.400379] nouveau T[   VBIOS][0000:01:00.0] 0xac30[ ]: NV_REG	R[0x11e400] &= 0xffffffff |= 0x00000000
>[    0.400380] nouveau T[   VBIOS][0000:01:00.0] 0xac3d[ ]: NV_REG	R[0x17ea00] &= 0xffffffff |= 0x00000000
>[    0.400381] nouveau T[   VBIOS][0000:01:00.0] 0xac4a[ ]: ZM_REG	R[0x141200] = 0x1000000c
>[    0.400382] nouveau T[   VBIOS][0000:01:00.0] 0xac53[ ]: ZM_REG	R[0x17e840] = 0x000f0030
>[    0.400383] nouveau T[   VBIOS][0000:01:00.0] 0xac5c[ ]: TIME	0x03e8
>[    0.400384] nouveau T[   VBIOS][0000:01:00.0] 0xac5f[ ]: NV_REG	R[0x11e200] &= 0xfffff7ff |= 0x00000800
>[    0.400385] nouveau T[   VBIOS][0000:01:00.0] 0xac6c[ ]: NV_REG	R[0x11e830] &= 0xfeffffff |= 0x01000000
>[    0.400386] nouveau T[   VBIOS][0000:01:00.0] 0xac79[ ]: NV_REG	R[0x11e830] &= 0xfeffffff |= 0x00000000
>[    0.400387] nouveau T[   VBIOS][0000:01:00.0] 0xac86[ ]: DONE
>[    0.400387] nouveau T[   VBIOS][0000:01:00.0] 0x695d[ ]: DONE
>[    0.400388] nouveau T[   VBIOS][0000:01:00.0] 0xb029[ ]: DONE
>[    0.400389] nouveau T[   VBIOS][0000:01:00.0] 0xb02a[ ]: SUB_DIRECT	0x8bb1
>[    0.400390] nouveau T[   VBIOS][0000:01:00.0] 0xb02d[ ]: ZM_REG_SEQUENCE	0x02
>[    0.400391] nouveau T[   VBIOS][0000:01:00.0] 0xb033[ ]: 		R[0x10f440] = 0x22f84f10
>[    0.400392] nouveau T[   VBIOS][0000:01:00.0] 0xb037[ ]: 		R[0x10f444] = 0x04cc883f
>[    0.400393] nouveau T[   VBIOS][0000:01:00.0] 0xb03b[ ]: ZM_REG	R[0x10f468] = 0x00001005
>[    0.400394] nouveau T[   VBIOS][0000:01:00.0] 0xb044[ ]: NV_REG	R[0x020210] &= 0xfffffffc |= 0x00000001
>[    0.400395] nouveau T[   VBIOS][0000:01:00.0] 0xb051[ ]: ZM_REG	R[0x08a088] = 0x10000003
>[    0.400396] nouveau T[   VBIOS][0000:01:00.0] 0xb05a[ ]: NV_REG	R[0x020018] &= 0xffffffff |= 0x00000000
>[    0.400397] nouveau T[   VBIOS][0000:01:00.0] 0xb067[ ]: NV_REG	R[0x00e500] &= 0xffffff03 |= 0x000000b0
>[    0.400398] nouveau T[   VBIOS][0000:01:00.0] 0xb074[ ]: NV_REG	R[0x00e550] &= 0xffffff03 |= 0x000000b0
>[    0.400399] nouveau T[   VBIOS][0000:01:00.0] 0xb081[ ]: NV_REG	R[0x00e5a0] &= 0xffffff03 |= 0x000000b0
>[    0.400400] nouveau T[   VBIOS][0000:01:00.0] 0xb08e[ ]: NV_REG	R[0x00e5f0] &= 0xffffff03 |= 0x000000b0
>[    0.400401] nouveau T[   VBIOS][0000:01:00.0] 0xb09b[ ]: ZM_REG	R[0x022680] = 0x80000000
>[    0.400402] nouveau T[   VBIOS][0000:01:00.0] 0xb0a4[ ]: NV_REG	R[0x17e878] &= 0xfffeffff |= 0x00010000
>[    0.400402] nouveau T[   VBIOS][0000:01:00.0] 0xb0b1[ ]: NV_REG	R[0x08841c] &= 0xfffffeff |= 0x00000100
>[    0.400403] nouveau T[   VBIOS][0000:01:00.0] 0xb0be[ ]: NV_REG	R[0x022400] &= 0xfffff7ff |= 0x00000000
>[    0.400404] nouveau T[   VBIOS][0000:01:00.0] 0xb0cb[ ]: NV_REG	R[0x02240c] &= 0xfffffffd |= 0x00000002
>[    0.400405] nouveau T[   VBIOS][0000:01:00.0] 0xb0d8[ ]: DONE
>[    0.400406] nouveau T[   VBIOS][0000:01:00.0] 0xb0d9[ ]: DONE
>[    0.400407] nouveau T[   VBIOS][0000:01:00.0] 0xb13f[ ]: DONE
>[    0.400408] nouveau T[   VBIOS][0000:01:00.0] 0xb13e[ ]: DONE
>[    0.400453] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[    0.400454] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[    0.400455] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.400456] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:05: -> NULL
>[    0.400460] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    0.400463] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:01: -> NULL
>[    0.400467] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    0.400470] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    0.400474] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    0.400477] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:01: -> NULL
>[    0.400481] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    0.400485] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    0.400495] nouveau D[     I2C][0000:01:00.0] reset
>[    0.400515] nouveau  [     PMC][0000:01:00.0] MSI interrupts enabled
>[    0.400564] nouveau  [     PFB][0000:01:00.0] RAM type: GDDR5
>[    0.400566] nouveau  [     PFB][0000:01:00.0] RAM size: 2048 MiB
>[    0.400568] nouveau  [     PFB][0000:01:00.0]    ZCOMP: 0 tags
>[    0.400591] nouveau T[   VBIOS][0000:01:00.0] 0xad9d[0]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e67c] 0x04 0x01
>[    0.400592] nouveau T[   VBIOS][0000:01:00.0] 0xada4[0]: 	R[0x11e67c] = {
>[    0.400592] nouveau T[   VBIOS][0000:01:00.0] 0xada4[0]: 		0xfff10000
>[    0.400593] nouveau T[   VBIOS][0000:01:00.0] 0xada8[0]: 		0xfff10000
>[    0.400594] nouveau T[   VBIOS][0000:01:00.0] 0xadac[0]: 		0xfff10000 *
>[    0.400595] nouveau T[   VBIOS][0000:01:00.0] 0xadb0[0]: 		0xfff10000
>[    0.400596] nouveau T[   VBIOS][0000:01:00.0] 0xadb4[0]: 		0xfff10000
>[    0.400597] nouveau T[   VBIOS][0000:01:00.0] 0xadb8[0]: 		0xfff10000
>[    0.400597] nouveau T[   VBIOS][0000:01:00.0] 0xadbc[0]: 		0xfff10000
>[    0.400598] nouveau T[   VBIOS][0000:01:00.0] 0xadc0[0]: 		0xfff10000
>[    0.400599] nouveau T[   VBIOS][0000:01:00.0] 0xadc4[0]: 	}
>[    0.400600] nouveau T[   VBIOS][0000:01:00.0] 0xadc4[0]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e708] 0x04 0x01
>[    0.400601] nouveau T[   VBIOS][0000:01:00.0] 0xadcb[0]: 	R[0x11e708] = {
>[    0.400602] nouveau T[   VBIOS][0000:01:00.0] 0xadcb[0]: 		0x00030000
>[    0.400602] nouveau T[   VBIOS][0000:01:00.0] 0xadcf[0]: 		0x00030440
>[    0.400603] nouveau T[   VBIOS][0000:01:00.0] 0xadd3[0]: 		0x00030220 *
>[    0.400604] nouveau T[   VBIOS][0000:01:00.0] 0xadd7[0]: 		0x00030000
>[    0.400605] nouveau T[   VBIOS][0000:01:00.0] 0xaddb[0]: 		0x00030400
>[    0.400606] nouveau T[   VBIOS][0000:01:00.0] 0xaddf[0]: 		0x00030440
>[    0.400606] nouveau T[   VBIOS][0000:01:00.0] 0xade3[0]: 		0x00030000
>[    0.400607] nouveau T[   VBIOS][0000:01:00.0] 0xade7[0]: 		0x00030000
>[    0.400608] nouveau T[   VBIOS][0000:01:00.0] 0xadeb[0]: 	}
>[    0.400609] nouveau T[   VBIOS][0000:01:00.0] 0xadeb[0]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e6a0] 0x04 0x06
>[    0.400610] nouveau T[   VBIOS][0000:01:00.0] 0xadf2[0]: 	R[0x11e6a0] = {
>[    0.400610] nouveau T[   VBIOS][0000:01:00.0] 0xadf2[0]: 		0x04040404
>[    0.400611] nouveau T[   VBIOS][0000:01:00.0] 0xadf6[0]: 		0x03030303
>[    0.400612] nouveau T[   VBIOS][0000:01:00.0] 0xadfa[0]: 		0x00000000 *
>[    0.400613] nouveau T[   VBIOS][0000:01:00.0] 0xadfe[0]: 		0x06060606
>[    0.400614] nouveau T[   VBIOS][0000:01:00.0] 0xae02[0]: 		0x03030303
>[    0.400614] nouveau T[   VBIOS][0000:01:00.0] 0xae06[0]: 		0x01010101
>[    0.400615] nouveau T[   VBIOS][0000:01:00.0] 0xae0a[0]: 		0x06060606
>[    0.400616] nouveau T[   VBIOS][0000:01:00.0] 0xae0e[0]: 		0x06060606
>[    0.400617] nouveau T[   VBIOS][0000:01:00.0] 0xae12[0]: 	}
>[    0.400618] nouveau T[   VBIOS][0000:01:00.0] 0xae12[0]: 	R[0x11e6a4] = {
>[    0.400618] nouveau T[   VBIOS][0000:01:00.0] 0xae12[0]: 		0x04040404
>[    0.400619] nouveau T[   VBIOS][0000:01:00.0] 0xae16[0]: 		0x03030303
>[    0.400620] nouveau T[   VBIOS][0000:01:00.0] 0xae1a[0]: 		0x00000000 *
>[    0.400621] nouveau T[   VBIOS][0000:01:00.0] 0xae1e[0]: 		0x06060606
>[    0.400622] nouveau T[   VBIOS][0000:01:00.0] 0xae22[0]: 		0x03030303
>[    0.400622] nouveau T[   VBIOS][0000:01:00.0] 0xae26[0]: 		0x01010101
>[    0.400623] nouveau T[   VBIOS][0000:01:00.0] 0xae2a[0]: 		0x06060606
>[    0.400624] nouveau T[   VBIOS][0000:01:00.0] 0xae2e[0]: 		0x06060606
>[    0.400625] nouveau T[   VBIOS][0000:01:00.0] 0xae32[0]: 	}
>[    0.400625] nouveau T[   VBIOS][0000:01:00.0] 0xae32[0]: 	R[0x11e6a8] = {
>[    0.400626] nouveau T[   VBIOS][0000:01:00.0] 0xae32[0]: 		0x0f0f0f0f
>[    0.400627] nouveau T[   VBIOS][0000:01:00.0] 0xae36[0]: 		0x0a0a0a0a
>[    0.400628] nouveau T[   VBIOS][0000:01:00.0] 0xae3a[0]: 		0x0f0f0f0f *
>[    0.400629] nouveau T[   VBIOS][0000:01:00.0] 0xae3e[0]: 		0x0f0f0f0f
>[    0.400629] nouveau T[   VBIOS][0000:01:00.0] 0xae42[0]: 		0x15151515
>[    0.400630] nouveau T[   VBIOS][0000:01:00.0] 0xae46[0]: 		0x0c0c0c0c
>[    0.400631] nouveau T[   VBIOS][0000:01:00.0] 0xae4a[0]: 		0x0f0f0f0f
>[    0.400632] nouveau T[   VBIOS][0000:01:00.0] 0xae4e[0]: 		0x0f0f0f0f
>[    0.400632] nouveau T[   VBIOS][0000:01:00.0] 0xae52[0]: 	}
>[    0.400633] nouveau T[   VBIOS][0000:01:00.0] 0xae52[0]: 	R[0x11e6ac] = {
>[    0.400634] nouveau T[   VBIOS][0000:01:00.0] 0xae52[0]: 		0x0f0f0f0f
>[    0.400635] nouveau T[   VBIOS][0000:01:00.0] 0xae56[0]: 		0x0a0a0a0a
>[    0.400636] nouveau T[   VBIOS][0000:01:00.0] 0xae5a[0]: 		0x0f0f0f0f *
>[    0.400636] nouveau T[   VBIOS][0000:01:00.0] 0xae5e[0]: 		0x0f0f0f0f
>[    0.400637] nouveau T[   VBIOS][0000:01:00.0] 0xae62[0]: 		0x15151515
>[    0.400638] nouveau T[   VBIOS][0000:01:00.0] 0xae66[0]: 		0x0c0c0c0c
>[    0.400639] nouveau T[   VBIOS][0000:01:00.0] 0xae6a[0]: 		0x0f0f0f0f
>[    0.400639] nouveau T[   VBIOS][0000:01:00.0] 0xae6e[0]: 		0x0f0f0f0f
>[    0.400640] nouveau T[   VBIOS][0000:01:00.0] 0xae72[0]: 	}
>[    0.400641] nouveau T[   VBIOS][0000:01:00.0] 0xae72[0]: 	R[0x11e6b0] = {
>[    0.400642] nouveau T[   VBIOS][0000:01:00.0] 0xae72[0]: 		0x05050505
>[    0.400643] nouveau T[   VBIOS][0000:01:00.0] 0xae76[0]: 		0x05050505
>[    0.400643] nouveau T[   VBIOS][0000:01:00.0] 0xae7a[0]: 		0x05050505 *
>[    0.400644] nouveau T[   VBIOS][0000:01:00.0] 0xae7e[0]: 		0x05050505
>[    0.400645] nouveau T[   VBIOS][0000:01:00.0] 0xae82[0]: 		0x05050505
>[    0.400646] nouveau T[   VBIOS][0000:01:00.0] 0xae86[0]: 		0x05050505
>[    0.400647] nouveau T[   VBIOS][0000:01:00.0] 0xae8a[0]: 		0x05050505
>[    0.400647] nouveau T[   VBIOS][0000:01:00.0] 0xae8e[0]: 		0x05050505
>[    0.400648] nouveau T[   VBIOS][0000:01:00.0] 0xae92[0]: 	}
>[    0.400649] nouveau T[   VBIOS][0000:01:00.0] 0xae92[0]: 	R[0x11e6b4] = {
>[    0.400650] nouveau T[   VBIOS][0000:01:00.0] 0xae92[0]: 		0x05050505
>[    0.400650] nouveau T[   VBIOS][0000:01:00.0] 0xae96[0]: 		0x05050505
>[    0.400651] nouveau T[   VBIOS][0000:01:00.0] 0xae9a[0]: 		0x05050505 *
>[    0.400652] nouveau T[   VBIOS][0000:01:00.0] 0xae9e[0]: 		0x05050505
>[    0.400653] nouveau T[   VBIOS][0000:01:00.0] 0xaea2[0]: 		0x05050505
>[    0.400654] nouveau T[   VBIOS][0000:01:00.0] 0xaea6[0]: 		0x05050505
>[    0.400654] nouveau T[   VBIOS][0000:01:00.0] 0xaeaa[0]: 		0x05050505
>[    0.400655] nouveau T[   VBIOS][0000:01:00.0] 0xaeae[0]: 		0x05050505
>[    0.400656] nouveau T[   VBIOS][0000:01:00.0] 0xaeb2[0]: 	}
>[    0.400657] nouveau T[   VBIOS][0000:01:00.0] 0xaeb2[0]: DONE
>[    0.400665] nouveau T[   VBIOS][0000:01:00.0] 0xaeb3[0]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e67c] 0x04 0x01
>[    0.400666] nouveau T[   VBIOS][0000:01:00.0] 0xaeba[0]: 	R[0x11e67c] = {
>[    0.400667] nouveau T[   VBIOS][0000:01:00.0] 0xaeba[0]: 		0xffff0000
>[    0.400668] nouveau T[   VBIOS][0000:01:00.0] 0xaebe[0]: 		0xffff0000
>[    0.400669] nouveau T[   VBIOS][0000:01:00.0] 0xaec2[0]: 		0xffff0000 *
>[    0.400669] nouveau T[   VBIOS][0000:01:00.0] 0xaec6[0]: 		0xffff0000
>[    0.400670] nouveau T[   VBIOS][0000:01:00.0] 0xaeca[0]: 		0xffff0000
>[    0.400671] nouveau T[   VBIOS][0000:01:00.0] 0xaece[0]: 		0xffff0000
>[    0.400672] nouveau T[   VBIOS][0000:01:00.0] 0xaed2[0]: 		0xffff0000
>[    0.400672] nouveau T[   VBIOS][0000:01:00.0] 0xaed6[0]: 		0xffff0000
>[    0.400673] nouveau T[   VBIOS][0000:01:00.0] 0xaeda[0]: 	}
>[    0.400674] nouveau T[   VBIOS][0000:01:00.0] 0xaeda[0]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e708] 0x04 0x01
>[    0.400675] nouveau T[   VBIOS][0000:01:00.0] 0xaee1[0]: 	R[0x11e708] = {
>[    0.400676] nouveau T[   VBIOS][0000:01:00.0] 0xaee1[0]: 		0x00030000
>[    0.400677] nouveau T[   VBIOS][0000:01:00.0] 0xaee5[0]: 		0x00030440
>[    0.400677] nouveau T[   VBIOS][0000:01:00.0] 0xaee9[0]: 		0x00030332 *
>[    0.400678] nouveau T[   VBIOS][0000:01:00.0] 0xaeed[0]: 		0x00030552
>[    0.400679] nouveau T[   VBIOS][0000:01:00.0] 0xaef1[0]: 		0x00030660
>[    0.400680] nouveau T[   VBIOS][0000:01:00.0] 0xaef5[0]: 		0x00030222
>[    0.400681] nouveau T[   VBIOS][0000:01:00.0] 0xaef9[0]: 		0x00030000
>[    0.400681] nouveau T[   VBIOS][0000:01:00.0] 0xaefd[0]: 		0x00030000
>[    0.400682] nouveau T[   VBIOS][0000:01:00.0] 0xaf01[0]: 	}
>[    0.400683] nouveau T[   VBIOS][0000:01:00.0] 0xaf01[0]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0011e6a0] 0x04 0x06
>[    0.400684] nouveau T[   VBIOS][0000:01:00.0] 0xaf08[0]: 	R[0x11e6a0] = {
>[    0.400685] nouveau T[   VBIOS][0000:01:00.0] 0xaf08[0]: 		0x00000000
>[    0.400686] nouveau T[   VBIOS][0000:01:00.0] 0xaf0c[0]: 		0x00000000
>[    0.400686] nouveau T[   VBIOS][0000:01:00.0] 0xaf10[0]: 		0x00000000 *
>[    0.400687] nouveau T[   VBIOS][0000:01:00.0] 0xaf14[0]: 		0x00000000
>[    0.400688] nouveau T[   VBIOS][0000:01:00.0] 0xaf18[0]: 		0x00000000
>[    0.400689] nouveau T[   VBIOS][0000:01:00.0] 0xaf1c[0]: 		0x00000000
>[    0.400689] nouveau T[   VBIOS][0000:01:00.0] 0xaf20[0]: 		0x00000000
>[    0.400690] nouveau T[   VBIOS][0000:01:00.0] 0xaf24[0]: 		0x00000000
>[    0.400691] nouveau T[   VBIOS][0000:01:00.0] 0xaf28[0]: 	}
>[    0.400692] nouveau T[   VBIOS][0000:01:00.0] 0xaf28[0]: 	R[0x11e6a4] = {
>[    0.400693] nouveau T[   VBIOS][0000:01:00.0] 0xaf28[0]: 		0x00000000
>[    0.400693] nouveau T[   VBIOS][0000:01:00.0] 0xaf2c[0]: 		0x00000000
>[    0.400694] nouveau T[   VBIOS][0000:01:00.0] 0xaf30[0]: 		0x00000000 *
>[    0.400695] nouveau T[   VBIOS][0000:01:00.0] 0xaf34[0]: 		0x00000000
>[    0.400696] nouveau T[   VBIOS][0000:01:00.0] 0xaf38[0]: 		0x00000000
>[    0.400696] nouveau T[   VBIOS][0000:01:00.0] 0xaf3c[0]: 		0x00000000
>[    0.400697] nouveau T[   VBIOS][0000:01:00.0] 0xaf40[0]: 		0x00000000
>[    0.400698] nouveau T[   VBIOS][0000:01:00.0] 0xaf44[0]: 		0x00000000
>[    0.400699] nouveau T[   VBIOS][0000:01:00.0] 0xaf48[0]: 	}
>[    0.400699] nouveau T[   VBIOS][0000:01:00.0] 0xaf48[0]: 	R[0x11e6a8] = {
>[    0.400700] nouveau T[   VBIOS][0000:01:00.0] 0xaf48[0]: 		0x00000000
>[    0.400701] nouveau T[   VBIOS][0000:01:00.0] 0xaf4c[0]: 		0x00000000
>[    0.400702] nouveau T[   VBIOS][0000:01:00.0] 0xaf50[0]: 		0x00000000 *
>[    0.400703] nouveau T[   VBIOS][0000:01:00.0] 0xaf54[0]: 		0x00000000
>[    0.400703] nouveau T[   VBIOS][0000:01:00.0] 0xaf58[0]: 		0x00000000
>[    0.400704] nouveau T[   VBIOS][0000:01:00.0] 0xaf5c[0]: 		0x00000000
>[    0.400705] nouveau T[   VBIOS][0000:01:00.0] 0xaf60[0]: 		0x00000000
>[    0.400706] nouveau T[   VBIOS][0000:01:00.0] 0xaf64[0]: 		0x00000000
>[    0.400706] nouveau T[   VBIOS][0000:01:00.0] 0xaf68[0]: 	}
>[    0.400707] nouveau T[   VBIOS][0000:01:00.0] 0xaf68[0]: 	R[0x11e6ac] = {
>[    0.400708] nouveau T[   VBIOS][0000:01:00.0] 0xaf68[0]: 		0x00000000
>[    0.400709] nouveau T[   VBIOS][0000:01:00.0] 0xaf6c[0]: 		0x00000000
>[    0.400710] nouveau T[   VBIOS][0000:01:00.0] 0xaf70[0]: 		0x00000000 *
>[    0.400710] nouveau T[   VBIOS][0000:01:00.0] 0xaf74[0]: 		0x00000000
>[    0.400737] nouveau T[   VBIOS][0000:01:00.0] 0xaf78[0]: 		0x00000000
>[    0.400739] nouveau T[   VBIOS][0000:01:00.0] 0xaf7c[0]: 		0x00000000
>[    0.400740] nouveau T[   VBIOS][0000:01:00.0] 0xaf80[0]: 		0x00000000
>[    0.400741] nouveau T[   VBIOS][0000:01:00.0] 0xaf84[0]: 		0x00000000
>[    0.400742] nouveau T[   VBIOS][0000:01:00.0] 0xaf88[0]: 	}
>[    0.400743] nouveau T[   VBIOS][0000:01:00.0] 0xaf88[0]: 	R[0x11e6b0] = {
>[    0.400744] nouveau T[   VBIOS][0000:01:00.0] 0xaf88[0]: 		0x00000000
>[    0.400745] nouveau T[   VBIOS][0000:01:00.0] 0xaf8c[0]: 		0x00000000
>[    0.400746] nouveau T[   VBIOS][0000:01:00.0] 0xaf90[0]: 		0x00000000 *
>[    0.400748] nouveau T[   VBIOS][0000:01:00.0] 0xaf94[0]: 		0x00000000
>[    0.400749] nouveau T[   VBIOS][0000:01:00.0] 0xaf98[0]: 		0x00000000
>[    0.400749] nouveau T[   VBIOS][0000:01:00.0] 0xaf9c[0]: 		0x00000000
>[    0.400751] nouveau T[   VBIOS][0000:01:00.0] 0xafa0[0]: 		0x00000000
>[    0.400751] nouveau T[   VBIOS][0000:01:00.0] 0xafa4[0]: 		0x00000000
>[    0.400752] nouveau T[   VBIOS][0000:01:00.0] 0xafa8[0]: 	}
>[    0.400753] nouveau T[   VBIOS][0000:01:00.0] 0xafa8[0]: 	R[0x11e6b4] = {
>[    0.400754] nouveau T[   VBIOS][0000:01:00.0] 0xafa8[0]: 		0x00000000
>[    0.400755] nouveau T[   VBIOS][0000:01:00.0] 0xafac[0]: 		0x00000000
>[    0.400755] nouveau T[   VBIOS][0000:01:00.0] 0xafb0[0]: 		0x00000000 *
>[    0.400756] nouveau T[   VBIOS][0000:01:00.0] 0xafb4[0]: 		0x00000000
>[    0.400757] nouveau T[   VBIOS][0000:01:00.0] 0xafb8[0]: 		0x00000000
>[    0.400758] nouveau T[   VBIOS][0000:01:00.0] 0xafbc[0]: 		0x00000000
>[    0.400759] nouveau T[   VBIOS][0000:01:00.0] 0xafc0[0]: 		0x00000000
>[    0.400759] nouveau T[   VBIOS][0000:01:00.0] 0xafc4[0]: 		0x00000000
>[    0.400760] nouveau T[   VBIOS][0000:01:00.0] 0xafc8[0]: 	}
>[    0.400761] nouveau T[   VBIOS][0000:01:00.0] 0xafc8[0]: DONE
>[    0.422890] nouveau D[     I2C][0000:01:00.0] probing monitoring devices on bus: 2
>[    0.422892] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.424070] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.424071] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.425254] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.425256] nouveau D[     I2C][0000:01:00.0] using custom udelay 40 instead of 10
>[    0.425257] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.429515] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.429516] nouveau D[     I2C][0000:01:00.0] using custom udelay 40 instead of 10
>[    0.429517] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.433761] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.433762] nouveau D[     I2C][0000:01:00.0] using custom udelay 40 instead of 10
>[    0.433763] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.438010] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.438011] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.439168] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.439169] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.440319] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.440321] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.441472] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.441473] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.442631] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.442632] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.443790] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.443791] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.444961] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.444962] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.446117] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.446118] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.447270] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.447271] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.448429] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.448430] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.449581] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.449582] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.450756] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.450757] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.451913] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.451914] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.453066] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.453067] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.454221] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.454222] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> PORT:02
>[    0.455373] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:02: -> NULL
>[    0.455374] nouveau D[     I2C][0000:01:00.0] no devices found.
>[    0.455376] nouveau  [  PTHERM][0000:01:00.0] FAN control: none / external
>[    0.455400] nouveau  [  PTHERM][0000:01:00.0] fan management: automatic
>[    0.455426] nouveau  [  PTHERM][0000:01:00.0] internal sensor: yes
>[    0.455499] nouveau  [     CLK][0000:01:00.0] 07: core 270-405 MHz memory 838 MHz 
>[    0.455546] nouveau  [     CLK][0000:01:00.0] 0a: core 270-925 MHz memory 1560 MHz 
>[    0.455580] nouveau  [     CLK][0000:01:00.0] 0e: core 270-925 MHz memory 4000 MHz 
>[    0.455606] nouveau  [     CLK][0000:01:00.0] 0f: core 270-925 MHz memory 5016 MHz 
>[    0.455769] nouveau  [     CLK][0000:01:00.0] --: core 405 MHz memory 680 MHz 
>[    0.502332] [TTM] Zone  kernel: Available graphics memory: 8167212 kiB
>[    0.502336] [TTM] Zone   dma32: Available graphics memory: 2097152 kiB
>[    0.502339] [TTM] Initializing pool allocator
>[    0.502344] [TTM] Initializing DMA pool allocator
>[    0.502354] nouveau  [     DRM] VRAM: 2048 MiB
>[    0.502356] nouveau  [     DRM] GART: 1048576 MiB
>[    0.502360] nouveau D[     DRM] Pointer to BIT loadval table invalid
>[    0.502362] nouveau  [     DRM] TMDS table version 2.0
>[    0.502365] nouveau  [     DRM] DCB version 4.0
>[    0.502369] nouveau  [     DRM] DCB outp 00: 04810fb6 0f230010
>[    0.502372] nouveau  [     DRM] DCB outp 01: 01821fd6 0f420020
>[    0.502375] nouveau  [     DRM] DCB outp 02: 01021f12 00020020
>[    0.502378] nouveau  [     DRM] DCB outp 03: 08832fc6 0f420010
>[    0.502381] nouveau  [     DRM] DCB outp 04: 08032f02 00020010
>[    0.502384] nouveau  [     DRM] DCB outp 05: 02843f62 00020010
>[    0.502386] nouveau  [     DRM] DCB conn 00: 00020047
>[    0.502390] nouveau  [     DRM] DCB conn 01: 02208146
>[    0.502393] nouveau  [     DRM] DCB conn 02: 01104246
>[    0.502396] nouveau  [     DRM] DCB conn 03: 00410361
>[    0.502443] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:01: -> PORT:1b
>[    0.502445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 16
>[    0.502713] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110900f 0x10000010
>[    0.502717] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    0.502721] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.502725] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.502730] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.502735] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[    0.502893] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[    0.502896] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4184840a
>[    0.502900] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.502905] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.502909] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.502914] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[    0.503080] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    0.503084] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41017777
>[    0.503088] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.503092] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.503096] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.503103] nouveau T[   VBIOS][0000:01:00.0] 0x6501[0]: NV_REG	R[0x00ea80] &= 0xfffffffd |= 0x00000002
>[    0.503107] nouveau T[   VBIOS][0000:01:00.0] 0x650e[0]: SUB_DIRECT	0x66f2
>[    0.503109] nouveau T[   VBIOS][0000:01:00.0] 0x66f2[1]: AUXCH	AUX[0x00000107] 0x01
>[    0.503110] nouveau T[   VBIOS][0000:01:00.0] 0x66f8[1]: 	AUX[0x00000107] &= 0xef |= 0x10
>[    0.503111] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000107 1
>[    0.503265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.503269] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41017710
>[    0.503273] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.503277] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.503281] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.503286] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000107 1
>[    0.503301] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000010
>[    0.503302] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.503303] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.503304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.503444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.503448] nouveau T[   VBIOS][0000:01:00.0] 0x66fa[1]: DONE
>[    0.503449] nouveau T[   VBIOS][0000:01:00.0] 0x6511[0]: DONE
>[    0.503450] nouveau T[   VBIOS][0000:01:00.0] 0x5f17[0]: NV_REG	R[0x00e800] &= 0xfffffcff |= 0x00000300
>[    0.503454] nouveau T[   VBIOS][0000:01:00.0] 0x5f24[0]: NV_REG	R[0x00e820] &= 0xfffffcff |= 0x00000300
>[    0.503457] nouveau T[   VBIOS][0000:01:00.0] 0x5f31[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[    0.503460] nouveau T[   VBIOS][0000:01:00.0] 0x5f3e[0]: NV_REG	R[0x40612300] &= 0xfcffffff |= 0x03000000
>[    0.503464] nouveau T[   VBIOS][0000:01:00.0] 0x5f4b[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000002
>[    0.503468] nouveau T[   VBIOS][0000:01:00.0] 0x5f58[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[    0.503469] nouveau T[   VBIOS][0000:01:00.0] 0x5f61[0]: ZM_REG	R[0x4061c010] = 0x0040152f
>[    0.503470] nouveau T[   VBIOS][0000:01:00.0] 0x5f6a[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[    0.503471] nouveau T[   VBIOS][0000:01:00.0] 0x5f73[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000000
>[    0.503474] nouveau T[   VBIOS][0000:01:00.0] 0x5f80[0]: TIME	0x03e8
>[    0.504475] nouveau T[   VBIOS][0000:01:00.0] 0x5f83[0]: SUB_DIRECT	0x4a48
>[    0.504476] nouveau T[   VBIOS][0000:01:00.0] 0x4a48[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[    0.504488] nouveau T[   VBIOS][0000:01:00.0] 0x4a55[1]: TIME	0x0064
>[    0.504589] nouveau T[   VBIOS][0000:01:00.0] 0x4a58[1]: CONDITION	0x06
>[    0.504590] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.504602] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[ ]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[    0.504603] nouveau T[   VBIOS][0000:01:00.0] 0x4a67[ ]: RESUME
>[    0.504604] nouveau T[   VBIOS][0000:01:00.0] 0x4a68[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[    0.504607] nouveau T[   VBIOS][0000:01:00.0] 0x4a75[1]: TIME	0x0064
>[    0.504708] nouveau T[   VBIOS][0000:01:00.0] 0x4a78[1]: CONDITION	0x06
>[    0.504709] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.504721] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[    0.504725] nouveau T[   VBIOS][0000:01:00.0] 0x4a87[1]: RESUME
>[    0.504726] nouveau T[   VBIOS][0000:01:00.0] 0x4a88[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[    0.504729] nouveau T[   VBIOS][0000:01:00.0] 0x4a95[1]: TIME	0x0064
>[    0.504830] nouveau T[   VBIOS][0000:01:00.0] 0x4a98[1]: CONDITION	0x06
>[    0.504831] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.504843] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[    0.504847] nouveau T[   VBIOS][0000:01:00.0] 0x4aa7[1]: RESUME
>[    0.504848] nouveau T[   VBIOS][0000:01:00.0] 0x4aa8[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[    0.504851] nouveau T[   VBIOS][0000:01:00.0] 0x4ab5[1]: TIME	0x0064
>[    0.504952] nouveau T[   VBIOS][0000:01:00.0] 0x4ab8[1]: CONDITION	0x06
>[    0.504953] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.504965] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[    0.504968] nouveau T[   VBIOS][0000:01:00.0] 0x4ac7[1]: RESUME
>[    0.504969] nouveau T[   VBIOS][0000:01:00.0] 0x4ac8[1]: DONE
>[    0.504970] nouveau T[   VBIOS][0000:01:00.0] 0x5f86[0]: NV_REG	R[0x40612300] &= 0xfffcffff |= 0x00010000
>[    0.504974] nouveau T[   VBIOS][0000:01:00.0] 0x5f93[0]: TIME	0x0032
>[    0.505025] nouveau T[   VBIOS][0000:01:00.0] 0x5f96[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[    0.505037] nouveau T[   VBIOS][0000:01:00.0] 0x5fa3[0]: NV_REG	R[0x4061c034] &= 0x7fee0fff |= 0x80000000
>[    0.505039] nouveau T[   VBIOS][0000:01:00.0] 0x5fb0[0]: CONDITION_TIME	0x14 0xff
>[    0.505040] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: 	[0x14] (R[0x4061c034] & 0x80000000) == 0x00000000
>[    0.505044] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: TIME	0x000a
>[    0.505055] nouveau T[   VBIOS][0000:01:00.0] 0x5fb6[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[    0.505066] nouveau T[   VBIOS][0000:01:00.0] 0x5fc3[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x00000000
>[    0.505069] nouveau T[   VBIOS][0000:01:00.0] 0x5fd0[0]: AUXCH	AUX[0x00000102] 0x01
>[    0.505070] nouveau T[   VBIOS][0000:01:00.0] 0x5fd6[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[    0.505071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.505224] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.505227] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41017700
>[    0.505231] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.505235] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.505239] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.505243] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.505259] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[    0.505260] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505260] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505261] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505400] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.505404] nouveau T[   VBIOS][0000:01:00.0] 0x5fd8[0]: DP_CONDITION	0x05 0x15
>[    0.505405] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[    0.505558] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.505561] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41017701
>[    0.505565] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.505569] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.505573] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.505577] nouveau T[   VBIOS][0000:01:00.0] 0x5fdb[0]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[    0.505580] nouveau T[   VBIOS][0000:01:00.0] 0x5fe8[0]: AUXCH	AUX[0x0000010a] 0x01
>[    0.505581] nouveau T[   VBIOS][0000:01:00.0] 0x5fee[0]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[    0.505582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000010a 1
>[    0.505734] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.505738] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41017701
>[    0.505742] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.505746] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.505750] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.505754] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x0000010a 1
>[    0.505769] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[    0.505770] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505771] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505772] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505911] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.505914] nouveau T[   VBIOS][0000:01:00.0] 0x5ff0[0]: DONE
>[    0.505915] nouveau T[   VBIOS][0000:01:00.0] 0x643c[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[    0.505916] nouveau T[   VBIOS][0000:01:00.0] 0x6445[0]: NV_REG	R[0x4061c010] &= 0xff0fffff |= 0x00400000
>[    0.505919] nouveau T[   VBIOS][0000:01:00.0] 0x6452[0]: NV_REG	R[0x4061c014] &= 0xffffffff |= 0x00000000
>[    0.505922] nouveau T[   VBIOS][0000:01:00.0] 0x645f[0]: DONE
>[    0.505937] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[    0.505953] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x0000840a
>[    0.505954] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505955] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.505956] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506102] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[    0.506109] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.506263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.506266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41017720
>[    0.506271] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.506275] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.506279] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.506284] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.506299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[    0.506300] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506301] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506302] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506442] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.506485] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[    0.506502] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506503] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506504] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506505] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.506670] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[    0.506774] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[    0.506975] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[    0.506978] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803333
>[    0.506983] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.506987] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.506991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.506999] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.507153] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.507156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803321
>[    0.507160] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.507165] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.507169] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.507173] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.507189] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[    0.507190] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.507191] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.507192] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.507331] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.507735] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[    0.507936] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[    0.507940] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817777
>[    0.507944] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.507948] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.507952] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.507960] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.508111] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.508115] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817722
>[    0.508119] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.508123] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.508127] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.508131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.508147] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[    0.508148] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508148] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.508301] nouveau T[   VBIOS][0000:01:00.0] 0x5ff1[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x10101010
>[    0.508304] nouveau T[   VBIOS][0000:01:00.0] 0x5ffe[0]: AUXCH	AUX[0x00000102] 0x01
>[    0.508305] nouveau T[   VBIOS][0000:01:00.0] 0x6004[0]: 	AUX[0x00000102] &= 0xdc |= 0x00
>[    0.508305] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.508458] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.508462] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817720
>[    0.508466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.508470] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.508474] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.508478] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.508494] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508495] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508495] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508496] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.508635] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.508638] nouveau T[   VBIOS][0000:01:00.0] 0x6006[0]: DONE
>[    0.508683] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[    0.508685] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 16
>[    0.508702] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[    0.508710] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    0.508724] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[    0.508725] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 16
>[    0.508741] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[    0.508749] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    0.509726] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    0.509730] [drm] Driver supports precise vblank timestamp query.
>[    0.516531] nouveau  [     DRM] MM: using COPY for buffer copies
>[    0.582223] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    0.582233] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    0.582439] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    0.582443] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    0.582448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.582452] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.582457] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.582461] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    0.582463] nouveau D[     DRM] encoder: 4x270000
>[    0.582464] nouveau D[     DRM] maximum: 4x270000
>[    0.582465] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    0.582639] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    0.582642] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    0.582647] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.582651] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.582656] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.582660] nouveau D[     DRM] Sink OUI: 0010fa
>[    0.582662] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    0.582829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    0.582832] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    0.582836] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.582841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.582845] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.582850] nouveau D[     DRM] Branch OUI: 000000
>[    0.582852] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    0.582868] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.582870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.582871] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.582872] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.583011] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    0.583014] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    0.583168] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    0.583171] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    0.583176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    0.583180] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000002
>[    0.583184] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000010f
>[    0.583189] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    0.583204] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.583205] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.583206] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.583208] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.583347] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    0.583351] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.583625] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.583629] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    0.583633] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    0.583637] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    0.583641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.583645] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.583912] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.583915] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    0.583919] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    0.583923] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    0.583927] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    0.583931] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.584198] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.584201] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    0.584205] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    0.584209] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    0.584213] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    0.584217] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.584485] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.584488] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    0.584492] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    0.584496] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    0.584500] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    0.584504] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.584773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.584777] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    0.584781] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    0.584785] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    0.584789] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    0.584793] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.585059] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.585063] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    0.585067] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    0.585071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    0.585075] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    0.585079] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    0.585346] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    0.585349] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.585353] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.585357] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.585361] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    0.585365] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    0.585632] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    0.585635] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.585639] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.585643] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.585647] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.585653] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] status updated from 3 to 1
>[    0.585659] nouveau D[     DRM] native mode from preferred
>[    0.585666] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    0.585668] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    0.585669] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    0.585670] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    0.585671] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    0.585672] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    0.585673] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    0.585674] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    0.585676] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    0.585677] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    0.585678] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    0.585679] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    0.585680] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    0.585681] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    0.585682] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    0.585684] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    0.585684] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[    0.585701] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[    0.585702] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[    0.585718] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[    0.585726] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    0.585727] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[    0.587940] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[    0.587941] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] status updated from 3 to 2
>[    0.587943] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[    0.587943] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[    0.587978] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[    0.587979] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[    0.588000] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[    0.588023] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    0.588024] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[    0.590323] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[    0.590324] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] status updated from 3 to 2
>[    0.590325] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[    0.590325] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[    0.590333] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[    0.591494] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    0.591495] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] status updated from 3 to 2
>[    0.591496] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[    0.591497] [drm:drm_setup_crtcs] 
>[    0.591504] [drm:drm_enable_connectors] connector 35 enabled? yes
>[    0.591515] [drm:drm_enable_connectors] connector 37 enabled? no
>[    0.591516] [drm:drm_enable_connectors] connector 40 enabled? no
>[    0.591517] [drm:drm_enable_connectors] connector 43 enabled? no
>[    0.591518] [drm:drm_target_preferred] looking for cmdline mode on connector 35
>[    0.591519] [drm:drm_target_preferred] looking for preferred mode on connector 35 0
>[    0.591519] [drm:drm_target_preferred] found mode 2880x1800
>[    0.591520] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    0.591522] [drm:drm_setup_crtcs] desired mode 2880x1800 set on crtc 28 (0,0)
>[    0.627041] nouveau  [     DRM] allocated 2880x1800 fb: 0x60000, bo ffff88046c631800
>[    0.627126] fbcon: nouveaufb (fb0) is primary device
>[    0.627175] [drm:drm_crtc_helper_set_config] 
>[    0.627176] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    0.627177] [drm:drm_crtc_helper_set_config] crtc has no fb, full mode set
>[    0.627177] [drm:drm_crtc_helper_set_config] modes are different, full mode set
>[    0.627179] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.627180] [drm:drm_mode_debug_printmodeline] Modeline 62:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    0.627181] [drm:drm_crtc_helper_set_config] encoder changed, full mode switch
>[    0.627182] [drm:drm_crtc_helper_set_config] crtc changed, full mode switch
>[    0.627182] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    0.627183] [drm:drm_crtc_helper_set_config] attempting to set mode from userspace
>[    0.627184] [drm:drm_mode_debug_printmodeline] Modeline 62:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    0.627185] [drm:drm_crtc_helper_set_mode] [CRTC:28]
>[    0.627214] [drm:drm_crtc_helper_set_mode] [ENCODER:36:TMDS-36] set [MODE:62:2880x1800]
>[    0.627235] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[    0.627396] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[    0.627399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000840a
>[    0.627403] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.627407] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.627411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.627415] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[    0.627583] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    0.627601] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00017777
>[    0.627615] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.627624] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.627629] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.628051] nouveau T[   VBIOS][0000:01:00.0] 0x66e2[0]: DONE
>[    0.832332] nouveau T[   VBIOS][0000:01:00.0] 0x66e3[0]: NV_REG	R[0x80616600] &= 0xfffffffe |= 0x00000000
>[    0.832337] nouveau T[   VBIOS][0000:01:00.0] 0x66f0[0]: DONE
>[    0.832338] nouveau T[   VBIOS][0000:01:00.0] 0x6033[0]: NV_REG	R[0x40612300] &= 0xfc80ffff |= 0x00280000
>[    0.832342] nouveau T[   VBIOS][0000:01:00.0] 0x6040[0]: NV_REG	R[0x6061c130] &= 0xfffffff0 |= 0x00000000
>[    0.832345] nouveau T[   VBIOS][0000:01:00.0] 0x604d[0]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80110000
>[    0.832350] nouveau T[   VBIOS][0000:01:00.0] 0x605a[0]: CONDITION_TIME	0x14 0xff
>[    0.832352] nouveau T[   VBIOS][0000:01:00.0] 0x605d[0]: 	[0x14] (R[0x4061c034] & 0x80000000) == 0x00000000
>[    0.832356] nouveau T[   VBIOS][0000:01:00.0] 0x605d[0]: NV_REG	R[0x6061c10c] &= 0xfffffffe |= 0x00000000
>[    0.832361] nouveau T[   VBIOS][0000:01:00.0] 0x606a[0]: NV_REG	R[0x4061c014] &= 0xff3fffff |= 0x00c00000
>[    0.832365] nouveau T[   VBIOS][0000:01:00.0] 0x6077[0]: NV_REG	R[0x4061c00c] &= 0xfffffffe |= 0x00000001
>[    0.832374] nouveau T[   VBIOS][0000:01:00.0] 0x6084[0]: DONE
>[    0.832412] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[    0.832581] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[    0.832585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0001840a
>[    0.832589] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.832593] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.832603] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.832608] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[    0.832780] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    0.832783] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00013333
>[    0.832787] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.832790] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.832794] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.832902] nouveau T[   VBIOS][0000:01:00.0] 0x6501[0]: NV_REG	R[0x00ea80] &= 0xfffffffd |= 0x00000002
>[    0.832909] nouveau T[   VBIOS][0000:01:00.0] 0x650e[0]: SUB_DIRECT	0x66f2
>[    0.832911] nouveau T[   VBIOS][0000:01:00.0] 0x66f2[1]: AUXCH	AUX[0x00000107] 0x01
>[    0.832913] nouveau T[   VBIOS][0000:01:00.0] 0x66f8[1]: 	AUX[0x00000107] &= 0xef |= 0x10
>[    0.832915] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000107 1
>[    0.833087] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.833090] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00013310
>[    0.833095] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.833099] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.833102] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.833107] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000107 1
>[    0.833129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000010
>[    0.833129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.833130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.833131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.833269] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.833278] nouveau T[   VBIOS][0000:01:00.0] 0x66fa[1]: DONE
>[    0.833279] nouveau T[   VBIOS][0000:01:00.0] 0x6511[0]: DONE
>[    0.833280] nouveau T[   VBIOS][0000:01:00.0] 0x5f17[0]: NV_REG	R[0x00e800] &= 0xfffffcff |= 0x00000300
>[    0.833285] nouveau T[   VBIOS][0000:01:00.0] 0x5f24[0]: NV_REG	R[0x00e820] &= 0xfffffcff |= 0x00000300
>[    0.833288] nouveau T[   VBIOS][0000:01:00.0] 0x5f31[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[    0.833292] nouveau T[   VBIOS][0000:01:00.0] 0x5f3e[0]: NV_REG	R[0x40612300] &= 0xfcffffff |= 0x03000000
>[    0.833295] nouveau T[   VBIOS][0000:01:00.0] 0x5f4b[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000002
>[    0.833300] nouveau T[   VBIOS][0000:01:00.0] 0x5f58[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[    0.833301] nouveau T[   VBIOS][0000:01:00.0] 0x5f61[0]: ZM_REG	R[0x4061c010] = 0x0040152f
>[    0.833302] nouveau T[   VBIOS][0000:01:00.0] 0x5f6a[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[    0.833303] nouveau T[   VBIOS][0000:01:00.0] 0x5f73[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000000
>[    0.833308] nouveau T[   VBIOS][0000:01:00.0] 0x5f80[0]: TIME	0x03e8
>[    0.834308] nouveau T[   VBIOS][0000:01:00.0] 0x5f83[0]: SUB_DIRECT	0x4a48
>[    0.834309] nouveau T[   VBIOS][0000:01:00.0] 0x4a48[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[    0.834314] nouveau T[   VBIOS][0000:01:00.0] 0x4a55[1]: TIME	0x0064
>[    0.834414] nouveau T[   VBIOS][0000:01:00.0] 0x4a58[1]: CONDITION	0x06
>[    0.834415] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.834428] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[ ]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[    0.834428] nouveau T[   VBIOS][0000:01:00.0] 0x4a67[ ]: RESUME
>[    0.834429] nouveau T[   VBIOS][0000:01:00.0] 0x4a68[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[    0.834434] nouveau T[   VBIOS][0000:01:00.0] 0x4a75[1]: TIME	0x0064
>[    0.834534] nouveau T[   VBIOS][0000:01:00.0] 0x4a78[1]: CONDITION	0x06
>[    0.834535] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.834540] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[    0.834544] nouveau T[   VBIOS][0000:01:00.0] 0x4a87[1]: RESUME
>[    0.834544] nouveau T[   VBIOS][0000:01:00.0] 0x4a88[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[    0.834549] nouveau T[   VBIOS][0000:01:00.0] 0x4a95[1]: TIME	0x0064
>[    0.834649] nouveau T[   VBIOS][0000:01:00.0] 0x4a98[1]: CONDITION	0x06
>[    0.834650] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.834661] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[    0.834666] nouveau T[   VBIOS][0000:01:00.0] 0x4aa7[1]: RESUME
>[    0.834666] nouveau T[   VBIOS][0000:01:00.0] 0x4aa8[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[    0.834670] nouveau T[   VBIOS][0000:01:00.0] 0x4ab5[1]: TIME	0x0064
>[    0.834771] nouveau T[   VBIOS][0000:01:00.0] 0x4ab8[1]: CONDITION	0x06
>[    0.834771] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[    0.834783] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[    0.834787] nouveau T[   VBIOS][0000:01:00.0] 0x4ac7[1]: RESUME
>[    0.834788] nouveau T[   VBIOS][0000:01:00.0] 0x4ac8[1]: DONE
>[    0.834788] nouveau T[   VBIOS][0000:01:00.0] 0x5f86[0]: NV_REG	R[0x40612300] &= 0xfffcffff |= 0x00010000
>[    0.834791] nouveau T[   VBIOS][0000:01:00.0] 0x5f93[0]: TIME	0x0032
>[    0.834842] nouveau T[   VBIOS][0000:01:00.0] 0x5f96[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[    0.834848] nouveau T[   VBIOS][0000:01:00.0] 0x5fa3[0]: NV_REG	R[0x4061c034] &= 0x7fee0fff |= 0x80000000
>[    0.834852] nouveau T[   VBIOS][0000:01:00.0] 0x5fb0[0]: CONDITION_TIME	0x14 0xff
>[    0.834852] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: 	[0x14] (R[0x4061c034] & 0x80000000) == 0x00000000
>[    0.834856] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: TIME	0x000a
>[    0.834866] nouveau T[   VBIOS][0000:01:00.0] 0x5fb6[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[    0.834878] nouveau T[   VBIOS][0000:01:00.0] 0x5fc3[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x00000000
>[    0.834883] nouveau T[   VBIOS][0000:01:00.0] 0x5fd0[0]: AUXCH	AUX[0x00000102] 0x01
>[    0.834883] nouveau T[   VBIOS][0000:01:00.0] 0x5fd6[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[    0.834884] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.835050] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.835053] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00013300
>[    0.835057] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.835061] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.835066] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.835072] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.835094] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[    0.835094] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835095] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835095] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835239] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.835243] nouveau T[   VBIOS][0000:01:00.0] 0x5fd8[0]: DP_CONDITION	0x05 0x15
>[    0.835244] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[    0.835406] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.835410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00013301
>[    0.835413] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.835427] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.835440] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.835449] nouveau T[   VBIOS][0000:01:00.0] 0x5fdb[0]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[    0.835452] nouveau T[   VBIOS][0000:01:00.0] 0x5fe8[0]: AUXCH	AUX[0x0000010a] 0x01
>[    0.835453] nouveau T[   VBIOS][0000:01:00.0] 0x5fee[0]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[    0.835453] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000010a 1
>[    0.835646] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.835650] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00013301
>[    0.835658] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.835663] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.835667] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.835672] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x0000010a 1
>[    0.835690] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[    0.835691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835692] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835832] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.835836] nouveau T[   VBIOS][0000:01:00.0] 0x5ff0[0]: DONE
>[    0.835837] nouveau T[   VBIOS][0000:01:00.0] 0x643c[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[    0.835838] nouveau T[   VBIOS][0000:01:00.0] 0x6445[0]: NV_REG	R[0x4061c010] &= 0xff0fffff |= 0x00400000
>[    0.835842] nouveau T[   VBIOS][0000:01:00.0] 0x6452[0]: NV_REG	R[0x4061c014] &= 0xffffffff |= 0x00000000
>[    0.835844] nouveau T[   VBIOS][0000:01:00.0] 0x645f[0]: DONE
>[    0.835870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[    0.835886] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x0000840a
>[    0.835887] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835887] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.835888] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836036] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[    0.836049] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.836210] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.836213] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00013320
>[    0.836217] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.836222] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.836227] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.836232] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.836253] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[    0.836253] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836254] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836255] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836398] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.836462] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[    0.836491] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836492] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836493] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836494] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.836659] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[    0.836765] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[    0.836964] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[    0.836969] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803333
>[    0.836972] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.836976] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.836986] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.836994] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.837151] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.837156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803321
>[    0.837160] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.837163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.837167] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.837176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.837192] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[    0.837193] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.837194] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.837194] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.837336] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.837740] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[    0.837943] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[    0.837947] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817777
>[    0.837950] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.837953] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.837957] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.837964] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.838122] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.838125] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817722
>[    0.838130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.838134] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.838139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.838145] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.838161] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[    0.838161] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838162] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838307] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.838311] nouveau T[   VBIOS][0000:01:00.0] 0x5ff1[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x10101010
>[    0.838314] nouveau T[   VBIOS][0000:01:00.0] 0x5ffe[0]: AUXCH	AUX[0x00000102] 0x01
>[    0.838315] nouveau T[   VBIOS][0000:01:00.0] 0x6004[0]: 	AUX[0x00000102] &= 0xdc |= 0x00
>[    0.838315] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[    0.838499] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[    0.838504] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817720
>[    0.838515] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.838525] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    0.838529] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    0.838533] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[    0.838552] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838552] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838553] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838553] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    0.838697] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    0.838706] nouveau T[   VBIOS][0000:01:00.0] 0x6006[0]: DONE
>[    0.838740] nouveau T[   VBIOS][0000:01:00.0] 0x63e9[0]: DP_CONDITION	0x00 0x28
>[    0.838741] nouveau T[   VBIOS][0000:01:00.0] 0x63ec[0]: NV_REG	R[0x00d618] &= 0xffffffff |= 0x00000000
>[    0.838746] nouveau T[   VBIOS][0000:01:00.0] 0x63f9[0]: NV_REG	R[0x00d620] &= 0xffffffff |= 0x00000000
>[    0.838750] nouveau T[   VBIOS][0000:01:00.0] 0x6406[0]: NV_REG	R[0x00d604] &= 0xffffffff |= 0x00000000
>[    0.838753] nouveau T[   VBIOS][0000:01:00.0] 0x6413[0]: RESUME
>[    0.838754] nouveau T[   VBIOS][0000:01:00.0] 0x6414[0]: SUB_DIRECT	0x6007
>[    0.838755] nouveau T[   VBIOS][0000:01:00.0] 0x6007[1]: COPY_NV_REG	R[0x80616600] &= 0x000001fc |= ((R[0x6061c10c] >> 0x00) & 0xffffffff ^ 0x00000000)
>[    0.838763] nouveau T[   VBIOS][0000:01:00.0] 0x601d[1]: SUB_DIRECT	0x670e
>[    0.838764] nouveau T[   VBIOS][0000:01:00.0] 0x670e[2]: ZM_REG_SEQUENCE	0x10
>[    0.838765] nouveau T[   VBIOS][0000:01:00.0] 0x6714[2]: 		R[0x4061c040] = 0x000010c8
>[    0.838766] nouveau T[   VBIOS][0000:01:00.0] 0x6718[2]: 		R[0x4061c044] = 0x0040a000
>[    0.838766] nouveau T[   VBIOS][0000:01:00.0] 0x671c[2]: 		R[0x4061c048] = 0x00408000
>[    0.838767] nouveau T[   VBIOS][0000:01:00.0] 0x6720[2]: 		R[0x4061c04c] = 0x00408000
>[    0.838768] nouveau T[   VBIOS][0000:01:00.0] 0x6724[2]: 		R[0x4061c050] = 0x00001032
>[    0.838769] nouveau T[   VBIOS][0000:01:00.0] 0x6728[2]: 		R[0x4061c054] = 0x0040a000
>[    0.838770] nouveau T[   VBIOS][0000:01:00.0] 0x672c[2]: 		R[0x4061c058] = 0x00408000
>[    0.838770] nouveau T[   VBIOS][0000:01:00.0] 0x6730[2]: 		R[0x4061c05c] = 0x00408000
>[    0.838771] nouveau T[   VBIOS][0000:01:00.0] 0x6734[2]: 		R[0x4061c060] = 0x00002000
>[    0.838772] nouveau T[   VBIOS][0000:01:00.0] 0x6738[2]: 		R[0x4061c064] = 0x000090c8
>[    0.838773] nouveau T[   VBIOS][0000:01:00.0] 0x673c[2]: 		R[0x4061c068] = 0x00008000
>[    0.838774] nouveau T[   VBIOS][0000:01:00.0] 0x6740[2]: 		R[0x4061c06c] = 0x00008000
>[    0.838774] nouveau T[   VBIOS][0000:01:00.0] 0x6744[2]: 		R[0x4061c070] = 0x00002000
>[    0.838775] nouveau T[   VBIOS][0000:01:00.0] 0x6748[2]: 		R[0x4061c074] = 0x00008000
>[    0.838776] nouveau T[   VBIOS][0000:01:00.0] 0x674c[2]: 		R[0x4061c078] = 0x00008000
>[    0.838777] nouveau T[   VBIOS][0000:01:00.0] 0x6750[2]: 		R[0x4061c07c] = 0x00008000
>[    0.838777] nouveau T[   VBIOS][0000:01:00.0] 0x6754[2]: DONE
>[    0.838778] nouveau T[   VBIOS][0000:01:00.0] 0x6020[1]: NV_REG	R[0x4061c030] &= 0xffff0f0f |= 0x0000c040
>[    0.838782] nouveau T[   VBIOS][0000:01:00.0] 0x602d[1]: CR		C[0xe8] &= 0xdf |= 0x20
>[    0.838785] nouveau T[   VBIOS][0000:01:00.0] 0x6031[1]: DONE
>[    0.838786] nouveau T[   VBIOS][0000:01:00.0] 0x6417[0]: DONE
>[    1.040093] nouveau T[   VBIOS][0000:01:00.0] 0x6032[0]: DONE
>[    1.073263] [drm:drm_crtc_helper_set_config] Setting connector DPMS state to on
>[    1.073264] [drm:drm_crtc_helper_set_config] 	[CONNECTOR:35:eDP-1] set DPMS on
>[    1.073267] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[    1.073283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[    1.073284] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.073284] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.073285] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.073424] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    1.123307] [drm:drm_crtc_helper_set_config] 
>[    1.123309] [drm:drm_crtc_helper_set_config] [CRTC:30] [NOFB]
>[    1.173225] [drm:drm_crtc_helper_set_config] 
>[    1.173226] [drm:drm_crtc_helper_set_config] [CRTC:32] [NOFB]
>[    1.223277] [drm:drm_crtc_helper_set_config] 
>[    1.223278] [drm:drm_crtc_helper_set_config] [CRTC:34] [NOFB]
>[    1.273192] [drm:drm_fb_helper_hotplug_event] 
>[    1.273194] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    1.273211] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    1.273437] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    1.273441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    1.273445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    1.273448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.273452] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    1.273457] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    1.273458] nouveau D[     DRM] encoder: 4x270000
>[    1.273458] nouveau D[     DRM] maximum: 4x270000
>[    1.273459] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    1.273626] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    1.273630] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    1.273634] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    1.273638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.273641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    1.273646] nouveau D[     DRM] Sink OUI: 0010fa
>[    1.273647] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    1.273814] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    1.273817] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    1.273821] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    1.273825] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.273829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    1.273833] nouveau D[     DRM] Branch OUI: 000000
>[    1.273835] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    1.273850] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.273851] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.273852] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.273852] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.273992] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    1.273996] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    1.274149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    1.274152] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    1.274156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    1.274160] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.274164] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    1.274168] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    1.274184] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.274184] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.274185] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.274186] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    1.274323] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    1.274326] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.274595] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.274599] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    1.274603] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    1.274606] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    1.274610] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.274614] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.274883] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.274887] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    1.274891] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    1.274895] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    1.274899] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    1.274903] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.275171] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.275174] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    1.275178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    1.275182] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    1.275185] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    1.275189] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.275459] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.275462] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    1.275466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    1.275470] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    1.275473] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    1.275477] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.275744] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.275747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    1.275751] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    1.275755] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    1.275758] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    1.275762] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.276029] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.276032] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    1.276036] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    1.276039] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    1.276043] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    1.276047] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    1.276317] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    1.276320] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.276324] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.276327] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.276331] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    1.276335] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    1.276602] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    1.276605] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.276609] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.276612] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    1.276616] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    1.276625] nouveau D[     DRM] native mode from preferred
>[    1.276633] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    1.276635] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    1.276636] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    1.276637] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    1.276637] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    1.276638] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    1.276639] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    1.276640] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    1.276641] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    1.276642] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    1.276642] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    1.276643] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    1.276644] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    1.276645] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    1.276646] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    1.276646] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    1.276647] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[    1.276663] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[    1.276664] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[    1.276679] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[    1.276686] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    1.276688] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[    1.278910] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[    1.278910] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[    1.278911] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[    1.278919] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[    1.278919] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[    1.278934] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[    1.278942] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    1.278942] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[    1.281189] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[    1.281190] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[    1.281190] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[    1.281198] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[    1.282363] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    1.282363] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[    1.282365] [drm:drm_setup_crtcs] 
>[    1.282366] [drm:drm_enable_connectors] connector 35 enabled? yes
>[    1.282366] [drm:drm_enable_connectors] connector 37 enabled? no
>[    1.282366] [drm:drm_enable_connectors] connector 40 enabled? no
>[    1.282367] [drm:drm_enable_connectors] connector 43 enabled? no
>[    1.282367] [drm:drm_target_preferred] looking for cmdline mode on connector 35
>[    1.282368] [drm:drm_target_preferred] looking for preferred mode on connector 35 0
>[    1.282368] [drm:drm_target_preferred] found mode 2880x1800
>[    1.282369] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    1.282370] [drm:drm_setup_crtcs] desired mode 2880x1800 set on crtc 28 (0,0)
>[    1.282385] [drm:drm_crtc_helper_set_config] 
>[    1.282385] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    1.282387] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    1.282393] [drm:drm_crtc_helper_set_config] 
>[    1.282393] [drm:drm_crtc_helper_set_config] [CRTC:30] [NOFB]
>[    1.323176] [drm:drm_crtc_helper_set_config] 
>[    1.323177] [drm:drm_crtc_helper_set_config] [CRTC:32] [NOFB]
>[    1.336222] tsc: Refined TSC clocksource calibration: 2294.667 MHz
>[    1.373149] [drm:drm_crtc_helper_set_config] 
>[    1.373150] [drm:drm_crtc_helper_set_config] [CRTC:34] [NOFB]
>[    1.423233] [drm:drm_crtc_helper_set_config] 
>[    1.423235] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    1.423237] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    1.429554] Console: switching to colour frame buffer device 360x112
>[    1.429557] [drm:drm_crtc_helper_set_config] 
>[    1.429558] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    1.429559] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    1.436064] nouveau 0000:01:00.0: fb0: nouveaufb frame buffer device
>[    1.436067] nouveau 0000:01:00.0: registered panic notifier
>[    1.440234] [drm] Initialized nouveau 1.2.1 20120801 for 0000:01:00.0 on minor 0
>[    1.441610] loop: module loaded
>[    1.441696] ahci 0000:05:00.0: version 3.0
>[    1.452222] ahci 0000:05:00.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
>[    1.452231] ahci 0000:05:00.0: flags: 64bit ncq led clo only pio ccc 
>[    1.452460] scsi host0: ahci
>[    1.452538] ata1: SATA max UDMA/133 abar m8192@0xc1b00000 port 0xc1b00100 irq 16
>[    1.452630] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
>[    1.452634] e100: Copyright(c) 1999-2006 Intel Corporation
>[    1.452651] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
>[    1.452655] e1000: Copyright (c) 1999-2006 Intel Corporation.
>[    1.452673] sky2: driver version 1.30
>[    1.452716] ipw2100: Intel(R) PRO/Wireless 2100 Network Driver, git-1.2.2
>[    1.452721] ipw2100: Copyright(c) 2003-2006 Intel Corporation
>[    1.452740] libipw: 802.11 data/management/control stack, git-1.1.13
>[    1.452745] libipw: Copyright (C) 2004-2005 Intel Corporation <jketreno@linux.intel.com>
>[    1.452762] usbcore: registered new interface driver asix
>[    1.452775] usbcore: registered new interface driver ax88179_178a
>[    1.452787] usbcore: registered new interface driver cdc_ether
>[    1.452799] usbcore: registered new interface driver net1080
>[    1.452813] usbcore: registered new interface driver cdc_subset
>[    1.452825] usbcore: registered new interface driver zaurus
>[    1.452842] usbcore: registered new interface driver cdc_ncm
>[    1.453035] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.453077] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>[    1.453206] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810
>[    1.453224] xhci_hcd 0000:00:14.0: cache line size of 256 is not supported
>[    1.453374] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.453392] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.453397] usb usb1: Product: xHCI Host Controller
>[    1.453401] usb usb1: Manufacturer: Linux 4.0.5-gnuNOUVEAUDEBUG xhci-hcd
>[    1.453405] usb usb1: SerialNumber: 0000:00:14.0
>[    1.453542] hub 1-0:1.0: USB hub found
>[    1.453572] hub 1-0:1.0: 14 ports detected
>[    1.453988] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.454032] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    1.454119] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.454140] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.454148] usb usb2: Product: xHCI Host Controller
>[    1.454155] usb usb2: Manufacturer: Linux 4.0.5-gnuNOUVEAUDEBUG xhci-hcd
>[    1.454159] usb usb2: SerialNumber: 0000:00:14.0
>[    1.454281] hub 2-0:1.0: USB hub found
>[    1.454307] hub 2-0:1.0: 6 ports detected
>[    1.454556] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    1.454562] ehci-pci: EHCI PCI platform driver
>[    1.454577] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    1.454584] ohci-pci: OHCI PCI platform driver
>[    1.454597] ohci-platform: OHCI generic platform driver
>[    1.454612] uhci_hcd: USB Universal Host Controller Interface driver
>[    1.454647] usbcore: registered new interface driver usblp
>[    1.454667] usbcore: registered new interface driver usb-storage
>[    1.454700] usbcore: registered new interface driver usbserial
>[    1.454705] usbip_core: USB/IP Core v1.0.0
>[    1.454733] vhci_hcd vhci_hcd: USB/IP Virtual Host Controller
>[    1.454772] vhci_hcd vhci_hcd: new USB bus registered, assigned bus number 3
>[    1.455024] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.455030] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.455034] usb usb3: Product: USB/IP Virtual Host Controller
>[    1.455038] usb usb3: Manufacturer: Linux 4.0.5-gnuNOUVEAUDEBUG vhci_hcd
>[    1.455042] usb usb3: SerialNumber: vhci_hcd
>[    1.455160] hub 3-0:1.0: USB hub found
>[    1.455176] hub 3-0:1.0: 8 ports detected
>[    1.455357] vhci_hcd: USB/IP 'Virtual' Host Controller (VHCI) Driver v1.0.0
>[    1.455378] usbcore: registered new device driver usbip-host
>[    1.455383] usbip_host: USB/IP Host Driver v1.0.0
>[    1.455414] i8042: PNP: No PS/2 controller found. Probing ports directly.
>[    1.759021] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[    1.759224] ata1.00: unexpected _GTF length (8)
>[    1.759283] ata1.00: ATA-8: APPLE SSD SM0512F, UXM2JA1Q, max UDMA/133
>[    1.759288] ata1.00: 977105060 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[    1.759489] ata1.00: unexpected _GTF length (8)
>[    1.759559] ata1.00: configured for UDMA/133
>[    1.759692] scsi 0:0:0:0: Direct-Access     ATA      APPLE SSD SM0512 JA1Q PQ: 0 ANSI: 5
>[    1.759838] sd 0:0:0:0: [sda] 977105060 512-byte logical blocks: (500 GB/465 GiB)
>[    1.759844] sd 0:0:0:0: [sda] 4096-byte physical blocks
>[    1.759855] sd 0:0:0:0: Attached scsi generic sg0 type 0
>[    1.759920] sd 0:0:0:0: [sda] Write Protect is off
>[    1.759933] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    1.759979] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    1.761684]  sda: sda1 sda2 sda3 sda4 sda5 sda6 sda7
>[    1.762083] sd 0:0:0:0: [sda] Attached SCSI disk
>[    2.024953] xhci_hcd 0000:00:14.0: Bad Slot ID 2
>[    2.024958] xhci_hcd 0000:00:14.0: Could not allocate xHCI USB device data structures
>[    2.024969] usb usb1-port8: couldn't allocate usb_device
>[    2.594402] i8042: No controller found
>[    2.594420] Switched to clocksource tsc
>[    2.594424] usb 2-4: new SuperSpeed USB device number 2 using xhci_hcd
>[    2.594459] mousedev: PS/2 mouse device common for all mice
>[    2.594559] usbcore: registered new interface driver bcm5974
>[    2.594604] rtc_cmos 00:02: RTC can wake from S4
>[    2.594699] rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0
>[    2.594728] rtc_cmos 00:02: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    2.594798] ACPI Warning: SystemIO range 0x000000000000EFA0-0x000000000000EFBF conflicts with OpRegion 0x000000000000EFA0-0x000000000000EFAF (\_SB_.PCI0.SBUS.SMBI) (20150204/utaddress-254)
>[    2.594799] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    2.594824] usbcore: registered new interface driver uvcvideo
>[    2.594824] USB Video Class driver (1.1.1)
>[    2.606493] usb 2-4: New USB device found, idVendor=05ac, idProduct=8406
>[    2.606972] usb 2-4: New USB device strings: Mfr=3, Product=4, SerialNumber=5
>[    2.607871] usb 2-4: Product: Card Reader
>[    2.608754] usb 2-4: Manufacturer: Apple
>[    2.609654] usb 2-4: SerialNumber: 000000000820
>[    2.611193] usb-storage 2-4:1.0: USB Mass Storage device detected
>[    2.611704] scsi host1: usb-storage 2-4:1.0
>[    2.654179] applesmc: key=614 fan=2 temp=41 index=40 acc=0 lux=2 kbd=1
>[    2.654926] device-mapper: ioctl: 4.30.0-ioctl (2014-12-22) initialised: dm-devel@redhat.com
>[    2.655599] EFI Variables Facility v0.08 2004-May-17
>[    2.746451] usb 1-12: new full-speed USB device number 2 using xhci_hcd
>[    2.916783] usb 1-12: New USB device found, idVendor=05ac, idProduct=0262
>[    2.917276] usb 1-12: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    2.918204] usb 1-12: Product: Apple Internal Keyboard / Trackpad
>[    2.919131] usb 1-12: Manufacturer: Apple Inc.
>[    2.922707] input: bcm5974 as /devices/pci0000:00/0000:00:14.0/usb1/1-12/1-12:1.2/input/input5
>[    2.924721] hidraw: raw HID events driver (C) Jiri Kosina
>[    2.929124] input: Apple Inc. Apple Internal Keyboard / Trackpad as /devices/pci0000:00/0000:00:14.0/usb1/1-12/1-12:1.0/0003:05AC:0262.0001/input/input6
>[    2.980543] apple 0003:05AC:0262.0001: input,hidraw0: USB HID v1.11 Keyboard [Apple Inc. Apple Internal Keyboard / Trackpad] on usb-0000:00:14.0-12/input0
>[    2.984119] apple 0003:05AC:0262.0002: hidraw1: USB HID v1.11 Device [Apple Inc. Apple Internal Keyboard / Trackpad] on usb-0000:00:14.0-12/input1
>[    2.984673] usbcore: registered new interface driver usbhid
>[    2.985619] usbhid: USB HID core driver
>[    2.987016] apple_gmux: Found gmux version 4.0.8 [indexed]
>[    3.008449] thunderbolt 0000:08:00.0: NHI initialized, starting thunderbolt
>[    3.008971] thunderbolt 0000:08:00.0: allocating TX ring 0 of size 10
>[    3.009953] thunderbolt 0000:08:00.0: allocating RX ring 0 of size 10
>[    3.010914] thunderbolt 0000:08:00.0: control channel created
>[    3.011874] thunderbolt 0000:08:00.0: control channel starting...
>[    3.012834] thunderbolt 0000:08:00.0: starting TX ring 0
>[    3.013788] thunderbolt 0000:08:00.0: enabling interrupt at register 0x38200 bit 0 (0x0 -> 0x1)
>[    3.014742] thunderbolt 0000:08:00.0: starting RX ring 0
>[    3.015703] thunderbolt 0000:08:00.0: enabling interrupt at register 0x38200 bit 12 (0x1 -> 0x1001)
>[    3.016816] thunderbolt 0000:08:00.0: initializing Switch at 0x0 (depth: 0, up port: 5)
>[    3.017620] thunderbolt 0000:08:00.0: old switch config:
>[    3.018562] thunderbolt 0000:08:00.0:  Switch: 8086:156d (Revision: 0, TB Version: 2)
>[    3.019520] thunderbolt 0000:08:00.0:   Max Port Number: 12
>[    3.020475] thunderbolt 0000:08:00.0:   Config:
>[    3.021429] thunderbolt 0000:08:00.0:    Upstream Port Number: 5 Depth: 0 Route String: 0x0 Enabled: 1, PlugEventsDelay: 255ms
>[    3.022408] thunderbolt 0000:08:00.0:    unknown1: 0x0 unknown4: 0x0
>[    3.023462] thunderbolt 0000:08:00.0: 0: unsupported switch device id 0x156d
>[    3.055491] thunderbolt 0000:08:00.0: 0: uid: 0x1000f00393300
>[    3.056128] thunderbolt 0000:08:00.0:  Port 0: 8086:156d (Revision: 0, TB Version: 1, Type: Port (0x1))
>[    3.057082] thunderbolt 0000:08:00.0:   Max hop id (in/out): 7/7
>[    3.058062] thunderbolt 0000:08:00.0:   Max counters: 8
>[    3.059037] thunderbolt 0000:08:00.0:   NFC Credits: 0x700000
>[    3.060525] thunderbolt 0000:08:00.0:  Port 1: 8086:156d (Revision: 0, TB Version: 1, Type: Port (0x1))
>[    3.061063] thunderbolt 0000:08:00.0:   Max hop id (in/out): 15/15
>[    3.062036] thunderbolt 0000:08:00.0:   Max counters: 16
>[    3.063006] thunderbolt 0000:08:00.0:   NFC Credits: 0x3c00000
>[    3.064480] thunderbolt 0000:08:00.0:  Port 2: 8086:156d (Revision: 0, TB Version: 1, Type: Port (0x1))
>[    3.065032] thunderbolt 0000:08:00.0:   Max hop id (in/out): 15/15
>[    3.066006] thunderbolt 0000:08:00.0:   Max counters: 16
>[    3.066975] thunderbolt 0000:08:00.0:   NFC Credits: 0x3c00000
>[    3.068457] thunderbolt 0000:08:00.0:  Port 3: 8086:156d (Revision: 0, TB Version: 1, Type: Port (0x1))
>[    3.068999] thunderbolt 0000:08:00.0:   Max hop id (in/out): 15/15
>[    3.069982] thunderbolt 0000:08:00.0:   Max counters: 16
>[    3.070937] thunderbolt 0000:08:00.0:   NFC Credits: 0x3c00000
>[    3.072411] thunderbolt 0000:08:00.0:  Port 4: 8086:156d (Revision: 0, TB Version: 1, Type: Port (0x1))
>[    3.072969] thunderbolt 0000:08:00.0:   Max hop id (in/out): 15/15
>[    3.074031] thunderbolt 0000:08:00.0:   Max counters: 16
>[    3.074997] thunderbolt 0000:08:00.0:   NFC Credits: 0x3c00000
>[    3.076063] thunderbolt 0000:08:00.0:  Port 5: 8086:156d (Revision: 0, TB Version: 1, Type: NHI (0x2))
>[    3.076927] thunderbolt 0000:08:00.0:   Max hop id (in/out): 11/11
>[    3.077895] thunderbolt 0000:08:00.0:   Max counters: 16
>[    3.078859] thunderbolt 0000:08:00.0:   NFC Credits: 0xf00000
>[    3.079927] thunderbolt 0000:08:00.0:  Port 6: 8086:156d (Revision: 0, TB Version: 1, Type: PCIe (0x100101))
>[    3.080792] thunderbolt 0000:08:00.0:   Max hop id (in/out): 8/8
>[    3.081760] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.082738] thunderbolt 0000:08:00.0:   NFC Credits: 0x700000
>[    3.083816] thunderbolt 0000:08:00.0:  Port 7: 8086:156d (Revision: 0, TB Version: 1, Type: PCIe (0x100101))
>[    3.084685] thunderbolt 0000:08:00.0:   Max hop id (in/out): 8/8
>[    3.085660] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.086629] thunderbolt 0000:08:00.0:   NFC Credits: 0x700000
>[    3.087723] thunderbolt 0000:08:00.0:  Port 8: 8086:156d (Revision: 0, TB Version: 1, Type: PCIe (0x100101))
>[    3.088573] thunderbolt 0000:08:00.0:   Max hop id (in/out): 8/8
>[    3.089534] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.090605] thunderbolt 0000:08:00.0:   NFC Credits: 0x700000
>[    3.091732] thunderbolt 0000:08:00.0:  Port 9: 8086:156d (Revision: 0, TB Version: 1, Type: PCIe (0x100101))
>[    3.092546] thunderbolt 0000:08:00.0:   Max hop id (in/out): 8/8
>[    3.093513] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.094484] thunderbolt 0000:08:00.0:   NFC Credits: 0x700000
>[    3.095461] thunderbolt 0000:08:00.0:  Port 10: 8086:156d (Revision: 0, TB Version: 1, Type: DP/HDMI (0xe0102))
>[    3.096412] thunderbolt 0000:08:00.0:   Max hop id (in/out): 9/9
>[    3.097370] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.098328] thunderbolt 0000:08:00.0:   NFC Credits: 0x700000
>[    3.099318] thunderbolt 0000:08:00.0:  Port 11: 8086:156d (Revision: 0, TB Version: 1, Type: DP/HDMI (0xe0101))
>[    3.100241] thunderbolt 0000:08:00.0:   Max hop id (in/out): 9/9
>[    3.101196] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.102155] thunderbolt 0000:08:00.0:   NFC Credits: 0xf00000
>[    3.103141] thunderbolt 0000:08:00.0:  Port 12: 8086:156d (Revision: 0, TB Version: 1, Type: DP/HDMI (0xe0101))
>[    3.104063] thunderbolt 0000:08:00.0:   Max hop id (in/out): 9/9
>[    3.105014] thunderbolt 0000:08:00.0:   Max counters: 2
>[    3.105965] thunderbolt 0000:08:00.0:   NFC Credits: 0xf00000
>[    3.107377] thunderbolt 0000:08:00.0: 0:1: is unplugged (state: 7)
>[    3.107978] thunderbolt 0000:08:00.0: 0:3: is unplugged (state: 7)
>[    3.109309] snd_hda_intel 0000:01:00.1: enabling device (0000 -> 0002)
>[    3.109889] snd_hda_intel 0000:01:00.1: Disabling MSI
>[    3.110791] snd_hda_intel 0000:01:00.1: Handle VGA-switcheroo audio client
>[    3.111793] Netfilter messages via NETLINK v0.30.
>[    3.112704] nf_conntrack version 0.5.0 (65536 buckets, 262144 max)
>[    3.113721] ctnetlink v0.93: registering with nfnetlink.
>[    3.114589] ip_tables: (C) 2000-2006 Netfilter Core Team
>[    3.115511] TCP: cubic registered
>[    3.117225] Initializing XFRM netlink socket
>[    3.117923] NET: Registered protocol family 10
>[    3.118893] ip6_tables: (C) 2000-2006 Netfilter Core Team
>[    3.119677] sit: IPv6 over IPv4 tunneling driver
>[    3.120690] NET: Registered protocol family 17
>[    3.121489] lib80211: common routines for IEEE802.11 drivers
>[    3.121684] sound hdaudioC0D0: autoconfig for CS4208: line_outs=2 (0x12/0x13/0x0/0x0/0x0) type:speaker
>[    3.121685] sound hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[    3.121686] sound hdaudioC0D0:    hp_outs=1 (0x10/0x0/0x0/0x0/0x0)
>[    3.121687] sound hdaudioC0D0:    mono: mono_out=0x0
>[    3.121688] sound hdaudioC0D0:    dig-out=0x21/0x0
>[    3.121688] sound hdaudioC0D0:    inputs:
>[    3.121690] sound hdaudioC0D0:      Internal Mic=0x1c
>[    3.121690] sound hdaudioC0D0:      Mic=0x18
>[    3.129574] lib80211_crypt: registered algorithm 'NULL'
>[    3.129578] lib80211_crypt: registered algorithm 'WEP'
>[    3.129590] lib80211_crypt: registered algorithm 'CCMP'
>[    3.129592] lib80211_crypt: registered algorithm 'TKIP'
>[    3.129599] Key type dns_resolver registered
>[    3.130788] registered taskstats version 1
>[    3.131817]   Magic number: 3:939:194
>[    3.132327] console [netcon0] enabled
>[    3.133106] netconsole: network logging started
>[    3.134717] PM: Hibernation image not present or could not be loaded.
>[    3.134722] ALSA device list:
>[    3.135150]   #0: HDA Intel PCH at 0xc1e14000 irq 36
>[    3.136020] md: Waiting for all devices to be available before autodetect
>[    3.136842] md: If you don't use raid, use raid=noautodetect
>[    3.137785] md: Autodetecting RAID arrays.
>[    3.138526] md: Scanned 0 and added 0 devices.
>[    3.139356] md: autorun ...
>[    3.140209] md: ... autorun DONE.
>[    3.141175] EXT3-fs (sda7): error: couldn't mount because of unsupported optional features (240)
>[    3.141957] EXT4-fs (sda7): couldn't mount as ext2 due to feature incompatibilities
>[    3.144118] EXT4-fs (sda7): INFO: recovery required on readonly filesystem
>[    3.144545] EXT4-fs (sda7): write access will be enabled during recovery
>[    3.167340] EXT4-fs (sda7): recovery complete
>[    3.171839] EXT4-fs (sda7): mounted filesystem with ordered data mode. Opts: (null)
>[    3.172293] VFS: Mounted root (ext4 filesystem) readonly on device 8:7.
>[    3.173868] devtmpfs: mounted
>[    3.174515] Freeing unused kernel memory: 1076K (ffffffff81f20000 - ffffffff8202d000)
>[    3.175038] Write protecting the kernel read-only data: 14336k
>[    3.176036] Freeing unused kernel memory: 292K (ffff8800019b7000 - ffff880001a00000)
>[    3.176771] Freeing unused kernel memory: 812K (ffff880001d35000 - ffff880001e00000)
>[    3.221828] [drm:drm_crtc_helper_set_config] 
>[    3.221830] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    3.221833] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    3.227804] setfont (1350) used greatest stack depth: 13552 bytes left
>[    3.229439] kbd_mode (1351) used greatest stack depth: 13216 bytes left
>[    3.257965] init-early.sh (1349) used greatest stack depth: 12776 bytes left
>[    3.266143] snd_hda_intel 0000:01:00.1: Too many HDMI devices
>[    3.267265] snd_hda_intel 0000:01:00.1: Consider building the kernel with CONFIG_SND_DYNAMIC_MINORS=y
>[    3.408065] ip (1464) used greatest stack depth: 12664 bytes left
>[    3.488446] udevd[1553]: starting version 1.5.3
>[    3.489573] random: udevd urandom read with 65 bits of entropy available
>[    3.619198] scsi 1:0:0:0: Direct-Access     APPLE    SD Card Reader   3.00 PQ: 0 ANSI: 6
>[    3.619342] sd 1:0:0:0: Attached scsi generic sg1 type 0
>[    3.620868] sd 1:0:0:0: [sdb] Attached SCSI removable disk
>[    4.677712] EXT4-fs (sda7): re-mounted. Opts: (null)
>[    4.742858] Adding 8388604k swap on /dev/sda6.  Priority:-1 extents:1 across:8388604k SS
>[    4.770232] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
>[    4.956447] [drm:drm_crtc_helper_set_config] 
>[    4.956449] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    4.956454] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    6.078412] sh (4840) used greatest stack depth: 12592 bytes left
>[    6.360172] random: nonblocking pool is initialized
>[    6.389333] [drm:drm_crtc_helper_set_config] 
>[    6.389336] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:63] #connectors=1 (x y) (0 0)
>[    6.389341] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    6.396098] [drm:drm_mode_getresources] CRTC[4] CONNECTORS[4] ENCODERS[6]
>[    6.396102] [drm:drm_mode_getresources] CRTC[4] CONNECTORS[4] ENCODERS[6]
>[    6.396115] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    6.396118] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    6.396138] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    6.396364] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    6.396369] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    6.396374] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.396379] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.396383] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.396388] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    6.396390] nouveau D[     DRM] encoder: 4x270000
>[    6.396391] nouveau D[     DRM] maximum: 4x270000
>[    6.396398] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    6.396575] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    6.396578] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    6.396583] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.396587] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.396592] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.396597] nouveau D[     DRM] Sink OUI: 0010fa
>[    6.396598] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    6.396767] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    6.396770] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    6.396775] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.396779] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.396784] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.396789] nouveau D[     DRM] Branch OUI: 000000
>[    6.396791] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    6.396808] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.396809] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.396811] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.396812] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.396953] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    6.396957] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    6.397108] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    6.397113] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    6.397117] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.397122] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.397126] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.397132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    6.397149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.397150] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.397151] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.397153] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.397292] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    6.397296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.397566] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.397569] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    6.397573] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    6.397578] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    6.397582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.397587] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.397854] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.397857] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    6.397862] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    6.397866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    6.397871] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    6.397876] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.398142] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.398145] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    6.398150] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    6.398154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    6.398159] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    6.398163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.398432] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.398435] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    6.398439] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    6.398444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    6.398449] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    6.398453] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.398720] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.398723] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    6.398728] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    6.398732] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    6.398737] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    6.398742] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.399008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.399011] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    6.399016] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    6.399020] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    6.399025] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    6.399030] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.399296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.399299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.399304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.399309] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.399313] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    6.399318] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    6.399586] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    6.399589] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.399594] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.399598] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.399603] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.399614] nouveau D[     DRM] native mode from preferred
>[    6.399629] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    6.399632] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    6.399634] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    6.399636] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    6.399638] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    6.399640] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    6.399642] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    6.399644] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    6.399646] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    6.399648] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    6.399650] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    6.399652] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    6.399654] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    6.399656] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    6.399658] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    6.399660] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    6.399664] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    6.399704] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[    6.399707] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[    6.399726] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[    6.399728] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[    6.399744] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[    6.399753] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    6.399756] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[    6.401933] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[    6.401935] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[    6.401938] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[    6.401960] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[    6.401962] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[    6.401980] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[    6.401981] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[    6.401999] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[    6.402007] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    6.402010] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[    6.404280] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[    6.404281] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[    6.404283] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[    6.404293] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[    6.404294] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[    6.404311] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[    6.405477] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    6.405478] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[    6.405479] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[    6.409199] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    6.409200] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    6.409214] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    6.409419] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    6.409423] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    6.409427] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.409431] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.409435] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.409439] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    6.409439] nouveau D[     DRM] encoder: 4x270000
>[    6.409440] nouveau D[     DRM] maximum: 4x270000
>[    6.409441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    6.409607] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    6.409610] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    6.409614] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.409618] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.409622] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.409626] nouveau D[     DRM] Sink OUI: 0010fa
>[    6.409627] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    6.409795] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    6.409798] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    6.409802] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.409806] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.409810] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.409814] nouveau D[     DRM] Branch OUI: 000000
>[    6.409815] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    6.409831] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.409832] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.409833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.409833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.409973] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    6.409976] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    6.410128] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    6.410131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    6.410135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    6.410139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.410143] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.410147] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    6.410163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.410164] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.410164] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.410165] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.410304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    6.410308] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.410577] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.410580] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    6.410584] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    6.410588] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    6.410592] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.410596] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.410862] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.410866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    6.410870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    6.410874] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    6.410878] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    6.410882] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.411149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.411152] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    6.411156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    6.411160] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    6.411164] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    6.411168] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.411437] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.411441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    6.411445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    6.411448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    6.411452] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    6.411457] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.411723] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.411726] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    6.411730] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    6.411734] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    6.411738] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    6.411742] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.412009] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.412013] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    6.412017] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    6.412021] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    6.412025] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    6.412029] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    6.412296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    6.412300] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.412304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.412308] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.412311] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    6.412316] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    6.412586] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    6.412589] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.412593] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.412597] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    6.412601] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    6.412609] nouveau D[     DRM] native mode from preferred
>[    6.412618] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    6.412619] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    6.412620] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    6.412621] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    6.412623] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    6.412624] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    6.412625] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    6.412626] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    6.412627] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    6.412628] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    6.412629] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    6.412630] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    6.412632] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    6.412633] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    6.412634] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    6.412635] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    6.412637] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    6.412913] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[    6.412914] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[    6.412931] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[    6.412932] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[    6.412948] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[    6.412956] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    6.412957] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[    6.415140] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[    6.415141] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[    6.415143] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[    6.415152] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[    6.415153] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[    6.415169] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[    6.415170] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[    6.415184] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[    6.415192] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    6.415193] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[    6.417423] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[    6.417424] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[    6.417425] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[    6.417432] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[    6.417433] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[    6.417449] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[    6.418604] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    6.418605] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[    6.418606] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[    6.420778] nouveau T[   VBIOS][0000:01:00.0] inc() == 2
>[    6.496285] [drm:drm_mode_addfb2] [FB:62]
>[    6.496318] [drm:drm_mode_setcrtc] [CRTC:28]
>[    6.496321] [drm:drm_mode_setcrtc] [CONNECTOR:35:eDP-1]
>[    6.496323] [drm:drm_crtc_helper_set_config] 
>[    6.496325] [drm:drm_crtc_helper_set_config] [CRTC:28] [FB:62] #connectors=1 (x y) (0 0)
>[    6.496330] [drm:drm_crtc_helper_set_config] [CONNECTOR:35:eDP-1] to [CRTC:28]
>[    6.521192] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[    6.521220] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[    6.521222] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.521223] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.521225] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    6.521365] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[    6.923639] nouveau T[   VBIOS][0000:01:00.0] inc() == 3
>[    6.958370] nouveau T[   VBIOS][0000:01:00.0] dec() == 2
>[    7.353455] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.353459] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    7.353479] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    7.353687] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    7.353692] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    7.353696] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.353701] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.353705] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.353710] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    7.353711] nouveau D[     DRM] encoder: 4x270000
>[    7.353712] nouveau D[     DRM] maximum: 4x270000
>[    7.353714] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    7.353880] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.353884] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    7.353888] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.353892] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.353897] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.353902] nouveau D[     DRM] Sink OUI: 0010fa
>[    7.353903] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    7.354071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.354074] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.354078] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.354083] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.354087] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.354092] nouveau D[     DRM] Branch OUI: 000000
>[    7.354094] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.354111] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354112] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354113] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354114] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.354255] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    7.354408] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    7.354411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.354416] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.354420] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.354424] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.354429] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.354445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354446] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354447] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.354588] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.354591] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.354858] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.354861] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    7.354866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    7.354870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    7.354874] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.354879] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.355148] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.355151] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    7.355156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    7.355160] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    7.355165] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    7.355169] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.355437] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.355440] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    7.355444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    7.355448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.355452] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.355456] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.355723] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.355727] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.355731] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    7.355735] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    7.355739] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    7.355743] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.356011] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.356015] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    7.356019] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    7.356023] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    7.356026] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    7.356031] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.356297] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.356300] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    7.356304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    7.356308] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    7.356312] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    7.356316] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.356583] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.356586] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.356590] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.356594] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.356598] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    7.356602] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    7.356874] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    7.356877] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.356880] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.356884] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.356889] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.356898] nouveau D[     DRM] native mode from preferred
>[    7.356908] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    7.356910] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    7.356911] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    7.356912] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    7.356923] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    7.356924] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    7.356925] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    7.356926] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    7.356928] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    7.356929] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    7.356930] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    7.356931] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    7.356932] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    7.356934] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    7.356935] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    7.356936] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    7.356939] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.357032] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[    7.357033] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[    7.357066] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[    7.357067] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[    7.357084] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[    7.357091] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[    7.357093] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[    7.359313] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[    7.359315] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[    7.359319] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[    7.359322] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[    7.359323] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[    7.359340] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[    7.359341] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[    7.359357] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[    7.359365] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[    7.359366] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[    7.361676] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[    7.361678] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[    7.361680] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[    7.361684] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[    7.361685] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[    7.361702] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[    7.362873] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[    7.362875] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[    7.362877] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[    7.401358] nouveau T[   VBIOS][0000:01:00.0] inc() == 3
>[    7.433751] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.433761] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    7.433782] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    7.433989] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    7.433994] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    7.433999] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.434003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.434008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.434013] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    7.434014] nouveau D[     DRM] encoder: 4x270000
>[    7.434015] nouveau D[     DRM] maximum: 4x270000
>[    7.434017] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    7.434185] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.434189] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    7.434193] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.434197] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.434202] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.434207] nouveau D[     DRM] Sink OUI: 0010fa
>[    7.434208] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    7.434376] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.434379] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.434384] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.434388] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.434392] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.434397] nouveau D[     DRM] Branch OUI: 000000
>[    7.434400] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.434416] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434419] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434420] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434560] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.434563] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    7.434713] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    7.434716] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.434721] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.434725] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.434730] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.434735] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.434750] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434751] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434753] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434759] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.434900] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.434904] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.435174] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.435177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    7.435181] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    7.435186] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    7.435190] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.435195] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.435465] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.435469] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    7.435473] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    7.435478] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    7.435482] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    7.435487] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.435760] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.435764] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    7.435769] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    7.435773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.435778] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.435782] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.436053] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.436056] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.436060] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    7.436065] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    7.436069] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    7.436074] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.436344] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.436347] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    7.436351] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    7.436356] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    7.436360] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    7.436365] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.436634] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.436638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    7.436642] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    7.436646] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    7.436651] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    7.436655] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.436924] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.436927] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.436932] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.436936] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.436941] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    7.436946] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    7.437215] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    7.437219] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.437223] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.437228] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.437232] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.437243] nouveau D[     DRM] native mode from preferred
>[    7.437257] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    7.437259] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    7.437261] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    7.437263] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    7.437265] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    7.437267] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    7.437269] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    7.437271] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    7.437273] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    7.437275] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    7.437277] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    7.437278] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    7.437280] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    7.437282] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    7.437284] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    7.437286] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    7.437290] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.437832] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.437834] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    7.437849] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    7.438056] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    7.438059] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    7.438064] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.438068] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.438073] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.438077] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    7.438079] nouveau D[     DRM] encoder: 4x270000
>[    7.438080] nouveau D[     DRM] maximum: 4x270000
>[    7.438081] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    7.438249] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.438252] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    7.438256] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.438261] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.438265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.438270] nouveau D[     DRM] Sink OUI: 0010fa
>[    7.438271] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    7.438439] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.438443] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.438447] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.438451] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.438456] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.438460] nouveau D[     DRM] Branch OUI: 000000
>[    7.438462] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.438479] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438480] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438481] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438483] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438622] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.438626] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    7.438779] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    7.438783] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.438787] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.438792] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.438796] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.438801] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.438816] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438818] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438819] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438820] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.438960] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.438963] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.439230] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.439233] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    7.439237] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    7.439242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    7.439246] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.439251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.439521] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.439525] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    7.439529] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    7.439533] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    7.439538] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    7.439543] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.439811] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.439814] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    7.439818] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    7.439823] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.439827] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.439832] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.440103] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.440106] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.440110] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    7.440115] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    7.440119] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    7.440124] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.440393] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.440397] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    7.440401] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    7.440406] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    7.440410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    7.440415] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.440681] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.440685] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    7.440689] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    7.440694] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    7.440698] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    7.440703] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.440971] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.440976] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.440981] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.440986] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.440991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    7.440997] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    7.441267] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    7.441272] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.441277] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.441282] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.441287] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.441317] nouveau D[     DRM] native mode from preferred
>[    7.441331] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    7.441333] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    7.441335] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    7.441337] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    7.441339] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    7.441341] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    7.441343] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    7.441345] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    7.441348] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    7.441350] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    7.441352] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    7.441354] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    7.441356] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    7.441358] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    7.441360] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    7.441362] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    7.441366] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.441449] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[    7.441451] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[    7.441466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[    7.441674] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[    7.441677] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[    7.441682] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.441686] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.441691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.441696] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[    7.441697] nouveau D[     DRM] encoder: 4x270000
>[    7.441698] nouveau D[     DRM] maximum: 4x270000
>[    7.441700] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[    7.441868] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.441871] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[    7.441876] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.441881] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.441885] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.441890] nouveau D[     DRM] Sink OUI: 0010fa
>[    7.441892] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[    7.442060] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[    7.442063] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.442068] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.442073] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.442077] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.442082] nouveau D[     DRM] Branch OUI: 000000
>[    7.442084] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.442101] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442102] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442103] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442105] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.442246] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[    7.442396] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[    7.442399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[    7.442404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[    7.442409] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.442413] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.442418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[    7.442434] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442435] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442437] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442438] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[    7.442579] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[    7.442583] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.442852] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.442855] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[    7.442860] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[    7.442864] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[    7.442869] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.442874] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.443141] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.443144] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[    7.443149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[    7.443153] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[    7.443158] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[    7.443163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.443430] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.443433] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[    7.443438] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[    7.443443] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.443447] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.443452] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.443719] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.443722] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[    7.443727] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[    7.443731] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[    7.443736] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[    7.443741] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.444009] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.444013] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[    7.444017] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[    7.444022] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[    7.444027] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[    7.444032] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.444299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.444302] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[    7.444307] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[    7.444311] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[    7.444316] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[    7.444320] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[    7.444588] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[    7.444591] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.444596] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.444600] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.444605] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[    7.444610] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[    7.444879] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[    7.444882] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.444887] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.444891] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[    7.444896] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[    7.444903] nouveau D[     DRM] native mode from preferred
>[    7.444916] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[    7.444919] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[    7.444921] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[    7.444923] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[    7.444925] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[    7.444927] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[    7.444929] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[    7.444931] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[    7.444933] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[    7.444935] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[    7.444937] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[    7.444940] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[    7.444942] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[    7.444944] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[    7.444946] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[    7.444948] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[    7.444951] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.137616] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.137622] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.137641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.137850] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.137856] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.137860] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.137865] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.137870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.137875] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.137877] nouveau D[     DRM] encoder: 4x270000
>[   10.137878] nouveau D[     DRM] maximum: 4x270000
>[   10.137881] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.138050] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.138055] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.138060] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.138064] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.138069] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.138074] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.138076] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.138247] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.138252] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.138257] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.138262] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.138266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.138272] nouveau D[     DRM] Branch OUI: 000000
>[   10.138275] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.138292] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138293] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138295] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138297] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138433] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.138439] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.138589] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.138594] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.138599] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.138604] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.138608] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.138614] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.138631] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138632] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138634] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138636] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.138773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.138778] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.139046] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.139051] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.139056] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.139061] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.139065] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.139071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.139343] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.139349] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.139354] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.139359] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.139365] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.139371] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.139641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.139646] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.139651] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.139656] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.139662] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.139668] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.139936] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.139941] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.139946] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.139952] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.139957] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.139962] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.140238] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.140243] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.140248] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.140253] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.140259] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.140265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.140535] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.140541] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.140546] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.140551] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.140556] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.140562] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.140833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.140838] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.140843] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.140849] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.140854] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.140859] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.141129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.141134] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.141140] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.141145] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.141150] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.141165] nouveau D[     DRM] native mode from preferred
>[   10.141190] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.141194] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.141198] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.141201] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.141204] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.141207] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.141210] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.141213] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.141216] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.141219] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.141222] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.141229] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.141232] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.141235] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.141238] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.141241] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.141248] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.141357] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.141359] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.141367] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.141576] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.141580] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.141585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.141590] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.141595] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.141600] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.141602] nouveau D[     DRM] encoder: 4x270000
>[   10.141603] nouveau D[     DRM] maximum: 4x270000
>[   10.141605] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.141774] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.141778] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.141783] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.141788] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.141793] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.141798] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.141800] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.141969] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.141972] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.141977] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.141982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.141987] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.141991] nouveau D[     DRM] Branch OUI: 000000
>[   10.141994] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.142011] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142012] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142014] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142015] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142152] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.142156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.142311] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.142316] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.142320] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.142325] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.142330] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.142335] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.142352] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142354] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142355] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142357] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.142497] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.142501] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.142768] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.142773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.142778] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.142783] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.142788] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.142793] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.143061] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.143064] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.143069] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.143074] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.143079] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.143084] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.143352] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.143357] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.143362] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.143366] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.143371] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.143376] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.143643] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.143648] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.143653] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.143657] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.143662] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.143667] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.143934] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.143937] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.143942] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.143947] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.143952] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.143957] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.144225] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.144229] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.144233] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.144238] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.144243] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.144248] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.144514] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.144519] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.144523] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.144528] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.144533] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.144538] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.144805] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.144809] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.144814] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.144818] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.144823] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.144831] nouveau D[     DRM] native mode from preferred
>[   10.144847] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.144850] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.144852] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.144855] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.144857] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.144859] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.144862] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.144864] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.144866] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.144869] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.144871] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.144873] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.144876] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.144878] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.144880] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.144882] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.144886] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.148768] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.148771] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.148780] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.148988] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.148993] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.148998] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.149003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.149008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.149013] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.149015] nouveau D[     DRM] encoder: 4x270000
>[   10.149016] nouveau D[     DRM] maximum: 4x270000
>[   10.149018] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.149187] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.149192] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.149197] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.149202] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.149206] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.149211] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.149213] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.149389] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.149394] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.149399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.149404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.149409] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.149413] nouveau D[     DRM] Branch OUI: 000000
>[   10.149433] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.149457] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149459] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149461] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149463] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149603] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.149609] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.149762] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.149767] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.149772] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.149782] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.149786] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.149792] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.149809] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149811] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149813] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149814] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.149951] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.149956] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.150227] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.150232] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.150237] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.150242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.150247] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.150252] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.150520] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.150525] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.150530] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.150535] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.150540] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.150545] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.150814] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.150819] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.150824] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.150829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.150833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.150839] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.151108] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.151113] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.151118] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.151123] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.151127] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.151133] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.151404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.151409] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.151414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.151418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.151423] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.151429] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.151697] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.151702] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.151707] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.151712] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.151717] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.151722] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.151990] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.151995] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.152000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.152005] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.152010] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.152015] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.152283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.152288] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.152293] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.152298] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.152302] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.152312] nouveau D[     DRM] native mode from preferred
>[   10.152329] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.152332] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.152334] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.152336] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.152339] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.152341] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.152344] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.152346] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.152349] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.152351] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.152354] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.152356] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.152359] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.152361] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.152364] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.152366] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.152370] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.152510] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[   10.152513] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[   10.152531] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[   10.152534] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[   10.152551] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[   10.152560] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[   10.152563] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[   10.154731] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[   10.154733] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[   10.154742] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[   10.154750] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   10.154751] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[   10.154761] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[   10.154763] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[   10.154780] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[   10.154789] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[   10.154792] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[   10.157041] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[   10.157043] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[   10.157046] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   10.157050] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[   10.157052] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[   10.157070] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[   10.158206] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[   10.158208] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[   10.158210] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[   10.384010] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.384014] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.384027] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.384235] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.384238] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.384242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.384247] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.384251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.384255] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.384256] nouveau D[     DRM] encoder: 4x270000
>[   10.384257] nouveau D[     DRM] maximum: 4x270000
>[   10.384258] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.384426] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.384430] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.384434] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.384438] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.384441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.384446] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.384447] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.384614] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.384617] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.384621] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.384625] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.384629] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.384633] nouveau D[     DRM] Branch OUI: 000000
>[   10.384635] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.384652] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384652] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384653] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384654] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384793] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.384796] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.384946] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.384949] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.384953] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.384957] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.384961] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.384966] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.384981] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384983] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.384984] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.385121] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.385124] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.385392] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.385395] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.385399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.385404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.385408] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.385412] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.385680] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.385683] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.385687] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.385691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.385695] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.385700] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.385966] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.385970] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.385974] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.385978] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.385982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.385986] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.386254] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.386258] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.386262] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.386266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.386270] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.386274] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.386541] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.386545] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.386549] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.386553] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.386557] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.386561] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.386830] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.386833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.386837] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.386841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.386845] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.386849] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.387118] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.387121] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.387125] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.387129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.387133] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.387138] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.387404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.387407] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.387411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.387415] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.387419] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.387428] nouveau D[     DRM] native mode from preferred
>[   10.387439] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.387441] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.387442] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.387443] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.387444] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.387445] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.387447] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.387448] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.387449] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.387450] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.387452] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.387453] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.387454] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.387455] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.387456] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.387458] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.387461] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.388677] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   10.388703] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   10.388705] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.388706] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.388708] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.388848] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   10.431472] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.431476] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.431486] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.431692] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.431696] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.431700] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.431704] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.431708] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.431713] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.431714] nouveau D[     DRM] encoder: 4x270000
>[   10.431715] nouveau D[     DRM] maximum: 4x270000
>[   10.431716] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.431882] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.431885] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.431889] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.431893] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.431897] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.431902] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.431903] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.432072] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.432075] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.432080] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.432084] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.432088] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.432092] nouveau D[     DRM] Branch OUI: 000000
>[   10.432094] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.432110] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432111] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432112] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432113] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.432255] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.432406] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.432410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.432414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.432418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.432422] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.432427] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.432442] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432443] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.432582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.432585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.432854] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.432857] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.432861] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.432865] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.432869] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.432873] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.433143] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.433147] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.433151] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.433155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.433159] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.433163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.433428] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.433432] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.433436] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.433440] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.433444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.433448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.433716] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.433719] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.433723] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.433727] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.433731] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.433736] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.434003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.434007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.434011] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.434015] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.434019] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.434023] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.434291] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.434294] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.434298] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.434302] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.434306] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.434310] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.434578] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.434581] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.434585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.434589] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.434593] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.434597] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.434865] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.434868] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.434872] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.434876] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.434880] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.434889] nouveau D[     DRM] native mode from preferred
>[   10.434899] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.434910] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.434911] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.434912] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.434914] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.434915] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.434916] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.434917] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.434918] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.434920] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.434921] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.434922] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.434923] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.434925] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.434926] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.434927] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.434930] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.436857] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.436860] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.436873] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.437079] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.437083] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.437087] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.437091] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.437095] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.437099] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.437100] nouveau D[     DRM] encoder: 4x270000
>[   10.437101] nouveau D[     DRM] maximum: 4x270000
>[   10.437102] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.437272] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.437275] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.437279] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.437283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.437287] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.437292] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.437293] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.437459] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.437463] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.437467] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.437471] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.437475] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.437479] nouveau D[     DRM] Branch OUI: 000000
>[   10.437480] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.437496] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437497] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437498] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437499] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.437641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.437793] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.437796] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.437800] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.437804] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.437808] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.437813] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.437828] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437828] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437830] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.437968] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.437971] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.438238] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.438242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.438246] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.438250] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.438254] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.438258] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.438526] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.438529] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.438533] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.438537] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.438541] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.438546] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.438813] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.438817] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.438821] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.438825] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.438829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.438833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.439105] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.439111] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.439116] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.439121] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.439126] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.439132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.439401] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.439406] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.439411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.439416] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.439421] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.439427] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.439695] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.439701] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.439706] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.439711] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.439716] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.439722] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.439991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.439996] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.440001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.440007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.440012] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.440017] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.440286] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.440292] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.440297] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.440303] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.440308] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.440340] nouveau D[     DRM] native mode from preferred
>[   10.440357] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.440361] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.440363] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.440365] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.440367] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.440370] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.440372] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.440374] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.440376] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.440378] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.440381] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.440383] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.440385] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.440387] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.440389] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.440392] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.440397] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.442110] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.442113] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.442123] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.442331] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.442337] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.442342] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.442346] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.442351] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.442357] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.442358] nouveau D[     DRM] encoder: 4x270000
>[   10.442359] nouveau D[     DRM] maximum: 4x270000
>[   10.442361] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.442530] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.442535] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.442540] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.442544] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.442549] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.442554] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.442556] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.442724] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.442727] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.442732] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.442737] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.442741] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.442746] nouveau D[     DRM] Branch OUI: 000000
>[   10.442748] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.442765] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.442767] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.442769] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.442770] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.442911] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.442915] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.443066] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.443071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.443075] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.443080] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.443085] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.443090] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.443107] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.443109] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.443110] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.443112] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.443253] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.443257] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.443527] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.443531] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.443536] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.443540] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.443545] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.443550] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.443817] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.443821] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.443825] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.443830] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.443835] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.443840] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.444106] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.444109] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.444114] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.444119] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.444123] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.444128] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.444395] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.444399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.444403] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.444408] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.444413] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.444418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.444685] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.444688] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.444693] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.444697] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.444702] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.444707] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.444974] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.444977] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.444982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.444987] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.444991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.444996] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.445266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.445271] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.445276] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.445280] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.445285] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.445290] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.445561] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.445564] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.445569] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.445574] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.445579] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.445589] nouveau D[     DRM] native mode from preferred
>[   10.445605] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.445608] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.445611] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.445613] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.445615] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.445617] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.445619] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.445621] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.445624] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.445626] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.445628] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.445631] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.445633] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.445635] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.445637] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.445639] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.445644] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.449447] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.449452] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.449472] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.449681] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.449686] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.449691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.449696] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.449701] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.449706] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.449708] nouveau D[     DRM] encoder: 4x270000
>[   10.449709] nouveau D[     DRM] maximum: 4x270000
>[   10.449712] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.449881] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.449886] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.449891] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.449896] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.449901] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.449907] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.449909] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.450079] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.450084] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.450089] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.450093] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.450098] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.450104] nouveau D[     DRM] Branch OUI: 000000
>[   10.450107] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.450124] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450126] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450127] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.450271] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.450423] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.450428] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.450433] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.450438] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.450443] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.450448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.450466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450467] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450469] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450471] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.450607] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.450612] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.450880] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.450885] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.450890] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.450895] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.450900] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.450905] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.451178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.451183] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.451188] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.451193] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.451197] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.451203] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.451470] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.451475] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.451480] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.451485] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.451490] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.451495] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.451764] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.451768] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.451773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.451778] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.451783] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.451788] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.452058] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.452063] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.452068] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.452073] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.452078] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.452083] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.452356] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.452360] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.452365] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.452370] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.452375] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.452380] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.452649] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.452654] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.452659] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.452664] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.452668] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.452674] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.452943] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.452948] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.452953] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.452958] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.452962] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.452974] nouveau D[     DRM] native mode from preferred
>[   10.452994] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.452997] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.453000] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.453002] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.453005] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.453007] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.453010] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.453012] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.453015] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.453019] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.453024] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.453028] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.453032] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.453034] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.453037] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.453039] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.453045] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.498597] [drm:drm_mode_addfb2] [FB:64]
>[   10.506151] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.506154] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   10.506169] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   10.506377] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   10.506380] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   10.506384] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.506388] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.506392] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.506397] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   10.506398] nouveau D[     DRM] encoder: 4x270000
>[   10.506398] nouveau D[     DRM] maximum: 4x270000
>[   10.506399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   10.506568] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.506572] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   10.506576] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.506580] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.506584] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.506588] nouveau D[     DRM] Sink OUI: 0010fa
>[   10.506589] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   10.506755] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   10.506758] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.506762] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.506767] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.506771] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.506775] nouveau D[     DRM] Branch OUI: 000000
>[   10.506777] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.506793] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.506794] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.506795] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.506796] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.506934] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.506938] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   10.507089] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   10.507092] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   10.507096] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   10.507100] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.507104] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.507112] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   10.507128] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.507129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.507130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.507131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   10.507267] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   10.507271] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.507538] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.507542] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   10.507546] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   10.507550] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   10.507554] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.507558] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.507825] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.507829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   10.507833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   10.507837] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   10.507841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   10.507845] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.508112] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.508116] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   10.508120] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   10.508124] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.508128] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.508132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.508418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.508422] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   10.508426] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   10.508430] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   10.508434] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   10.508438] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.508704] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.508707] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   10.508711] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   10.508715] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   10.508719] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   10.508724] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.508992] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.508995] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   10.508999] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   10.509003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   10.509007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   10.509012] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   10.509293] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   10.509296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.509301] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.509305] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.509310] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   10.509315] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   10.509582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   10.509585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.509590] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.509594] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   10.509599] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   10.509610] nouveau D[     DRM] native mode from preferred
>[   10.509626] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   10.509629] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   10.509631] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   10.509633] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   10.509635] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   10.509637] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   10.509639] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   10.509641] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   10.509644] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   10.509646] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   10.509648] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   10.509650] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   10.509652] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   10.509654] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   10.509656] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   10.509658] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   10.509663] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   10.551934] [drm:drm_mode_addfb2] [FB:62]
>[   10.587454] [drm:drm_mode_addfb2] [FB:64]
>[   10.620920] [drm:drm_mode_addfb2] [FB:62]
>[   10.654425] [drm:drm_mode_addfb2] [FB:64]
>[   10.687958] [drm:drm_mode_addfb2] [FB:62]
>[   10.721061] [drm:drm_mode_addfb2] [FB:64]
>[   10.754383] [drm:drm_mode_addfb2] [FB:62]
>[   10.787737] [drm:drm_mode_addfb2] [FB:64]
>[   10.821019] [drm:drm_mode_addfb2] [FB:62]
>[   10.854340] [drm:drm_mode_addfb2] [FB:64]
>[   10.887665] [drm:drm_mode_addfb2] [FB:62]
>[   10.920987] [drm:drm_mode_addfb2] [FB:64]
>[   10.954269] [drm:drm_mode_addfb2] [FB:62]
>[   10.987583] [drm:drm_mode_addfb2] [FB:64]
>[   11.020939] [drm:drm_mode_addfb2] [FB:62]
>[   11.054253] [drm:drm_mode_addfb2] [FB:64]
>[   11.186940] [drm:drm_mode_addfb2] [FB:62]
>[   11.194430] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   11.194451] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000002
>[   11.194453] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   11.194454] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   11.194455] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   11.194595] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   11.248806] [drm:drm_mode_addfb2] [FB:64]
>[   11.288248] [drm:drm_mode_addfb2] [FB:62]
>[   11.338219] [drm:drm_mode_addfb2] [FB:64]
>[   11.387839] [drm:drm_mode_addfb2] [FB:62]
>[   11.439925] [drm:drm_mode_addfb2] [FB:64]
>[   11.488262] [drm:drm_mode_addfb2] [FB:62]
>[   13.044049] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   13.044076] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   13.044081] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.044086] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.044090] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.044234] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.046379] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[   13.046548] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[   13.046557] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000840a
>[   13.046565] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.046572] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.046580] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.046632] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[   13.046804] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   13.046811] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803333
>[   13.046818] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.046824] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.046831] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.046846] nouveau T[   VBIOS][0000:01:00.0] 0x6501[0]: NV_REG	R[0x00ea80] &= 0xfffffffd |= 0x00000002
>[   13.046862] nouveau T[   VBIOS][0000:01:00.0] 0x650e[0]: SUB_DIRECT	0x66f2
>[   13.046867] nouveau T[   VBIOS][0000:01:00.0] 0x66f2[1]: AUXCH	AUX[0x00000107] 0x01
>[   13.046872] nouveau T[   VBIOS][0000:01:00.0] 0x66f8[1]: 	AUX[0x00000107] &= 0xef |= 0x10
>[   13.046878] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000107 1
>[   13.047040] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.047047] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803310
>[   13.047054] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.047060] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.047067] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.047075] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000107 1
>[   13.047095] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000010
>[   13.047098] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.047102] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.047105] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.047249] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.047256] nouveau T[   VBIOS][0000:01:00.0] 0x66fa[1]: DONE
>[   13.047260] nouveau T[   VBIOS][0000:01:00.0] 0x6511[0]: DONE
>[   13.047264] nouveau T[   VBIOS][0000:01:00.0] 0x5f17[0]: NV_REG	R[0x00e800] &= 0xfffffcff |= 0x00000300
>[   13.047280] nouveau T[   VBIOS][0000:01:00.0] 0x5f24[0]: NV_REG	R[0x00e820] &= 0xfffffcff |= 0x00000300
>[   13.047287] nouveau T[   VBIOS][0000:01:00.0] 0x5f31[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[   13.047295] nouveau T[   VBIOS][0000:01:00.0] 0x5f3e[0]: NV_REG	R[0x40612300] &= 0xfcffffff |= 0x03000000
>[   13.047302] nouveau T[   VBIOS][0000:01:00.0] 0x5f4b[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000002
>[   13.047310] nouveau T[   VBIOS][0000:01:00.0] 0x5f58[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[   13.047314] nouveau T[   VBIOS][0000:01:00.0] 0x5f61[0]: ZM_REG	R[0x4061c010] = 0x0040152f
>[   13.047318] nouveau T[   VBIOS][0000:01:00.0] 0x5f6a[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[   13.047323] nouveau T[   VBIOS][0000:01:00.0] 0x5f73[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000000
>[   13.047329] nouveau T[   VBIOS][0000:01:00.0] 0x5f80[0]: TIME	0x03e8
>[   13.048334] nouveau T[   VBIOS][0000:01:00.0] 0x5f83[0]: SUB_DIRECT	0x4a48
>[   13.048338] nouveau T[   VBIOS][0000:01:00.0] 0x4a48[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[   13.048346] nouveau T[   VBIOS][0000:01:00.0] 0x4a55[1]: TIME	0x0064
>[   13.048450] nouveau T[   VBIOS][0000:01:00.0] 0x4a58[1]: CONDITION	0x06
>[   13.048457] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   13.048471] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[ ]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[   13.048475] nouveau T[   VBIOS][0000:01:00.0] 0x4a67[ ]: RESUME
>[   13.048479] nouveau T[   VBIOS][0000:01:00.0] 0x4a68[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[   13.048493] nouveau T[   VBIOS][0000:01:00.0] 0x4a75[1]: TIME	0x0064
>[   13.048596] nouveau T[   VBIOS][0000:01:00.0] 0x4a78[1]: CONDITION	0x06
>[   13.048601] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   13.048616] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[   13.048622] nouveau T[   VBIOS][0000:01:00.0] 0x4a87[1]: RESUME
>[   13.048626] nouveau T[   VBIOS][0000:01:00.0] 0x4a88[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[   13.048633] nouveau T[   VBIOS][0000:01:00.0] 0x4a95[1]: TIME	0x0064
>[   13.048737] nouveau T[   VBIOS][0000:01:00.0] 0x4a98[1]: CONDITION	0x06
>[   13.048741] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   13.048748] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[   13.048754] nouveau T[   VBIOS][0000:01:00.0] 0x4aa7[1]: RESUME
>[   13.048758] nouveau T[   VBIOS][0000:01:00.0] 0x4aa8[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[   13.048765] nouveau T[   VBIOS][0000:01:00.0] 0x4ab5[1]: TIME	0x0064
>[   13.048868] nouveau T[   VBIOS][0000:01:00.0] 0x4ab8[1]: CONDITION	0x06
>[   13.048873] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   13.048887] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[   13.048893] nouveau T[   VBIOS][0000:01:00.0] 0x4ac7[1]: RESUME
>[   13.048897] nouveau T[   VBIOS][0000:01:00.0] 0x4ac8[1]: DONE
>[   13.048901] nouveau T[   VBIOS][0000:01:00.0] 0x5f86[0]: NV_REG	R[0x40612300] &= 0xfffcffff |= 0x00010000
>[   13.048907] nouveau T[   VBIOS][0000:01:00.0] 0x5f93[0]: TIME	0x0032
>[   13.048962] nouveau T[   VBIOS][0000:01:00.0] 0x5f96[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[   13.048971] nouveau T[   VBIOS][0000:01:00.0] 0x5fa3[0]: NV_REG	R[0x4061c034] &= 0x7fee0fff |= 0x80000000
>[   13.048978] nouveau T[   VBIOS][0000:01:00.0] 0x5fb0[0]: CONDITION_TIME	0x14 0xff
>[   13.048983] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: 	[0x14] (R[0x4061c034] & 0x80000000) == 0x00000000
>[   13.048990] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: TIME	0x000a
>[   13.049004] nouveau T[   VBIOS][0000:01:00.0] 0x5fb6[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[   13.049013] nouveau T[   VBIOS][0000:01:00.0] 0x5fc3[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x00000000
>[   13.049020] nouveau T[   VBIOS][0000:01:00.0] 0x5fd0[0]: AUXCH	AUX[0x00000102] 0x01
>[   13.049024] nouveau T[   VBIOS][0000:01:00.0] 0x5fd6[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[   13.049028] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   13.049190] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.049197] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803300
>[   13.049204] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.049210] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.049217] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.049225] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   13.049244] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[   13.049248] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.049251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.049254] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.049398] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.049407] nouveau T[   VBIOS][0000:01:00.0] 0x5fd8[0]: DP_CONDITION	0x05 0x15
>[   13.049411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[   13.049569] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.049576] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803301
>[   13.049586] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.049593] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.049599] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.049607] nouveau T[   VBIOS][0000:01:00.0] 0x5fdb[0]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[   13.049614] nouveau T[   VBIOS][0000:01:00.0] 0x5fe8[0]: AUXCH	AUX[0x0000010a] 0x01
>[   13.049618] nouveau T[   VBIOS][0000:01:00.0] 0x5fee[0]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[   13.049622] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000010a 1
>[   13.049785] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.049791] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803301
>[   13.049798] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.049805] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.049811] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.049819] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x0000010a 1
>[   13.049838] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   13.049842] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.049845] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.049849] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.049993] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.050000] nouveau T[   VBIOS][0000:01:00.0] 0x5ff0[0]: DONE
>[   13.050005] nouveau T[   VBIOS][0000:01:00.0] 0x643c[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[   13.050010] nouveau T[   VBIOS][0000:01:00.0] 0x6445[0]: NV_REG	R[0x4061c010] &= 0xff0fffff |= 0x00400000
>[   13.050017] nouveau T[   VBIOS][0000:01:00.0] 0x6452[0]: NV_REG	R[0x4061c014] &= 0xffffffff |= 0x00000000
>[   13.050023] nouveau T[   VBIOS][0000:01:00.0] 0x645f[0]: DONE
>[   13.050044] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[   13.050064] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x0000840a
>[   13.050067] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050074] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050223] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[   13.050234] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   13.050388] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.050395] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803320
>[   13.050402] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.050408] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.050415] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.050422] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   13.050441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[   13.050445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050452] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050594] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.050659] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[   13.050679] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050682] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050685] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050689] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.050854] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[   13.050962] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[   13.051156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[   13.051163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803333
>[   13.051169] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.051176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.051182] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.051193] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   13.051351] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.051358] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803321
>[   13.051364] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.051371] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.051377] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.051385] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   13.051404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[   13.051407] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.051411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.051414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.051558] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.051966] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[   13.052161] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[   13.052168] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817777
>[   13.052175] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.052181] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.052188] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.052198] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   13.052356] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.052363] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817722
>[   13.052369] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.052376] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.052383] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.052390] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   13.052410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[   13.052413] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052416] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052420] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052563] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.052571] nouveau T[   VBIOS][0000:01:00.0] 0x5ff1[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x10101010
>[   13.052582] nouveau T[   VBIOS][0000:01:00.0] 0x5ffe[0]: AUXCH	AUX[0x00000102] 0x01
>[   13.052587] nouveau T[   VBIOS][0000:01:00.0] 0x6004[0]: 	AUX[0x00000102] &= 0xdc |= 0x00
>[   13.052591] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   13.052753] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   13.052760] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817720
>[   13.052767] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.052773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   13.052780] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   13.052787] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   13.052807] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052810] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052813] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052817] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.052960] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.052967] nouveau T[   VBIOS][0000:01:00.0] 0x6006[0]: DONE
>[   13.064090] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   13.064117] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   13.064119] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.064120] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.064122] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   13.064259] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   13.067223] [drm:drm_mode_addfb2] [FB:64]
>[   13.104341] [drm:drm_mode_addfb2] [FB:62]
>[   13.155983] [drm:drm_mode_addfb2] [FB:64]
>[   13.206821] [drm:drm_mode_addfb2] [FB:62]
>[   13.237738] [drm:drm_mode_addfb2] [FB:64]
>[   13.273761] [drm:drm_mode_addfb2] [FB:62]
>[   13.304851] [drm:drm_mode_addfb2] [FB:64]
>[   13.338126] [drm:drm_mode_addfb2] [FB:62]
>[   13.419451] [drm:drm_mode_addfb2] [FB:64]
>[   13.443807] [drm:drm_mode_addfb2] [FB:62]
>[   13.897307] [drm:drm_mode_addfb2] [FB:64]
>[   14.017342] [drm:drm_mode_addfb2] [FB:62]
>[   14.041408] [drm:drm_mode_addfb2] [FB:64]
>[   14.098895] [drm:drm_mode_addfb2] [FB:62]
>[   14.123866] [drm:drm_mode_addfb2] [FB:64]
>[   14.156206] [drm:drm_mode_addfb2] [FB:62]
>[   14.188047] [drm:drm_mode_addfb2] [FB:64]
>[   14.208305] [drm:drm_mode_addfb2] [FB:62]
>[   14.238501] [drm:drm_mode_addfb2] [FB:64]
>[   14.256533] [drm:drm_mode_addfb2] [FB:62]
>[   14.287795] [drm:drm_mode_addfb2] [FB:64]
>[   16.906529] [drm:drm_mode_addfb2] [FB:62]
>[   16.936221] [drm:drm_mode_addfb2] [FB:64]
>[   16.956089] [drm:drm_mode_addfb2] [FB:62]
>[   16.986522] [drm:drm_mode_addfb2] [FB:64]
>[   17.006180] [drm:drm_mode_addfb2] [FB:62]
>[   17.035816] [drm:drm_mode_addfb2] [FB:64]
>[   17.055743] [drm:drm_mode_addfb2] [FB:62]
>[   17.086477] [drm:drm_mode_addfb2] [FB:64]
>[   17.107203] [drm:drm_mode_addfb2] [FB:62]
>[   17.135873] [drm:drm_mode_addfb2] [FB:64]
>[   17.188656] nouveau T[   VBIOS][0000:01:00.0] dec() == 2
>[   19.082103] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.082106] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   19.082122] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   19.082331] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   19.082334] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   19.082338] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.082342] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.082346] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.082351] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   19.082351] nouveau D[     DRM] encoder: 4x270000
>[   19.082352] nouveau D[     DRM] maximum: 4x270000
>[   19.082353] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   19.082522] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.082525] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   19.082529] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.082533] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.082537] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.082541] nouveau D[     DRM] Sink OUI: 0010fa
>[   19.082542] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   19.082709] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.082713] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.082717] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.082721] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.082725] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.082729] nouveau D[     DRM] Branch OUI: 000000
>[   19.082731] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.082747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.082748] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.082749] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.082749] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.082888] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.082892] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   19.083043] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   19.083047] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.083052] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.083056] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.083061] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.083066] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.083082] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.083082] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.083083] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.083084] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.083221] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.083224] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.083493] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.083496] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   19.083500] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   19.083504] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   19.083508] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.083512] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.083782] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.083786] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   19.083790] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   19.083794] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   19.083798] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   19.083802] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.084071] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.084074] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   19.084078] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   19.084082] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.084086] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.084090] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.084359] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.084362] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.084366] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   19.084370] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   19.084374] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   19.084378] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.084648] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.084651] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   19.084655] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   19.084659] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   19.084663] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   19.084667] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.084934] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.084938] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   19.084942] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   19.084946] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   19.084950] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   19.084954] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.085236] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.085240] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.085244] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.085247] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.085251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   19.085256] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   19.085523] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   19.085527] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.085531] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.085535] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.085539] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.085548] nouveau D[     DRM] native mode from preferred
>[   19.085558] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   19.085559] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   19.085561] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   19.085562] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   19.085563] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   19.085564] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   19.085565] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   19.085567] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   19.085568] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   19.085569] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   19.085570] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   19.085572] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   19.085573] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   19.085574] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   19.085575] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   19.085576] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   19.085580] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.085669] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[   19.085671] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[   19.085696] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[   19.085697] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[   19.085713] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[   19.085720] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[   19.085722] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[   19.087920] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[   19.087921] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[   19.087926] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[   19.087930] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   19.087930] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[   19.087939] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[   19.087940] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[   19.087954] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[   19.087962] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[   19.087963] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[   19.090251] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[   19.090252] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[   19.090253] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   19.090256] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[   19.090257] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[   19.090265] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[   19.091443] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[   19.091444] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[   19.091445] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[   19.127932] nouveau T[   VBIOS][0000:01:00.0] inc() == 3
>[   19.153282] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.153286] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   19.153298] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   19.153504] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   19.153509] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   19.153514] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.153518] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.153523] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.153528] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   19.153529] nouveau D[     DRM] encoder: 4x270000
>[   19.153530] nouveau D[     DRM] maximum: 4x270000
>[   19.153532] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   19.153702] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.153705] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   19.153710] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.153714] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.153719] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.153723] nouveau D[     DRM] Sink OUI: 0010fa
>[   19.153725] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   19.153893] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.153896] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.153901] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.153905] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.153909] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.153914] nouveau D[     DRM] Branch OUI: 000000
>[   19.153917] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.153933] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.153935] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.153936] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.153937] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.154075] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.154079] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   19.154233] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   19.154238] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.154242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.154247] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.154252] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.154258] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.154276] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.154277] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.154279] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.154281] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.154417] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.154423] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.154692] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.154697] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   19.154702] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   19.154706] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   19.154711] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.154717] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.154986] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.154991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   19.154995] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   19.155000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   19.155005] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   19.155010] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.155279] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.155284] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   19.155289] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   19.155294] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.155299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.155304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.155572] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.155577] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.155582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   19.155587] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   19.155592] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   19.155597] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.155865] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.155870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   19.155875] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   19.155880] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   19.155885] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   19.155890] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.156162] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.156167] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   19.156172] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   19.156177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   19.156182] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   19.156187] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.156456] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.156461] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.156466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.156471] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.156476] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   19.156481] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   19.156750] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   19.156755] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.156760] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.156765] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.156769] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.156792] nouveau D[     DRM] native mode from preferred
>[   19.156811] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   19.156815] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   19.156818] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   19.156820] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   19.156823] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   19.156825] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   19.156827] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   19.156830] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   19.156832] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   19.156835] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   19.156838] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   19.156840] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   19.156843] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   19.156845] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   19.156847] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   19.156850] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   19.156855] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.157018] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.157020] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   19.157036] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   19.157242] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   19.157247] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   19.157252] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.157257] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.157262] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.157267] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   19.157269] nouveau D[     DRM] encoder: 4x270000
>[   19.157270] nouveau D[     DRM] maximum: 4x270000
>[   19.157272] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   19.157440] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.157445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   19.157450] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.157455] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.157460] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.157465] nouveau D[     DRM] Sink OUI: 0010fa
>[   19.157467] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   19.157636] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.157641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.157646] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.157651] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.157656] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.157661] nouveau D[     DRM] Branch OUI: 000000
>[   19.157663] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.157680] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.157682] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.157684] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.157685] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.157822] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.157828] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   19.157980] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   19.157985] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.157989] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.157994] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.157999] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.158004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.158022] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.158023] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.158025] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.158027] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.158165] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.158171] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.158439] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.158444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   19.158449] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   19.158454] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   19.158459] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.158464] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.158737] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.158742] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   19.158747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   19.158752] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   19.158757] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   19.158762] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.159030] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.159035] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   19.159040] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   19.159045] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.159050] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.159055] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.159326] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.159330] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.159335] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   19.159340] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   19.159345] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   19.159350] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.159619] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.159624] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   19.159629] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   19.159634] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   19.159639] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   19.159644] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.159913] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.159918] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   19.159923] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   19.159927] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   19.159932] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   19.159938] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.160208] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.160213] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.160217] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.160222] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.160227] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   19.160232] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   19.160500] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   19.160505] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.160510] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.160515] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.160520] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.160528] nouveau D[     DRM] native mode from preferred
>[   19.160545] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   19.160548] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   19.160550] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   19.160553] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   19.160555] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   19.160558] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   19.160560] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   19.160562] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   19.160565] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   19.160568] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   19.160570] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   19.160572] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   19.160575] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   19.160577] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   19.160580] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   19.160582] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   19.160586] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.161246] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.161249] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   19.161266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   19.161475] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   19.161478] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   19.161483] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.161487] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.161492] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.161498] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   19.161499] nouveau D[     DRM] encoder: 4x270000
>[   19.161501] nouveau D[     DRM] maximum: 4x270000
>[   19.161503] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   19.161672] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.161677] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   19.161682] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.161687] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.161692] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.161697] nouveau D[     DRM] Sink OUI: 0010fa
>[   19.161699] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   19.161868] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.161873] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.161878] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.161883] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.161887] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.161893] nouveau D[     DRM] Branch OUI: 000000
>[   19.161895] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.161912] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.161913] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.161915] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.161917] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.162058] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.162063] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   19.162215] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   19.162220] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.162224] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.162229] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.162234] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.162240] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.162257] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.162259] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.162261] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.162262] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.162399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.162405] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.162674] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.162679] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   19.162684] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   19.162689] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   19.162694] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.162699] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.162968] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.162973] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   19.162978] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   19.162982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   19.162987] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   19.162993] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.163263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.163268] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   19.163273] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   19.163278] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.163283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.163288] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.163557] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.163562] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.163567] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   19.163572] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   19.163577] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   19.163582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.163851] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.163856] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   19.163861] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   19.163866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   19.163870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   19.163876] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.164147] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.164152] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   19.164157] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   19.164162] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   19.164167] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   19.164172] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.164441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.164446] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.164451] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.164456] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.164460] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   19.164465] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   19.164738] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   19.164743] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.164747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.164752] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.164757] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.164783] nouveau D[     DRM] native mode from preferred
>[   19.164795] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   19.164797] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   19.164799] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   19.164801] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   19.164802] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   19.164804] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   19.164806] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   19.164808] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   19.164810] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   19.164811] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   19.164813] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   19.164815] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   19.164817] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   19.164819] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   19.164820] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   19.164822] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   19.164826] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.164887] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.164889] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   19.164895] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   19.165101] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   19.165104] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   19.165109] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.165113] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.165118] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.165125] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   19.165126] nouveau D[     DRM] encoder: 4x270000
>[   19.165127] nouveau D[     DRM] maximum: 4x270000
>[   19.165129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   19.165296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.165299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   19.165304] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.165308] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.165313] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.165317] nouveau D[     DRM] Sink OUI: 0010fa
>[   19.165319] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   19.165486] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.165490] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.165494] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.165499] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.165503] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.165507] nouveau D[     DRM] Branch OUI: 000000
>[   19.165509] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.165526] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165527] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165528] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165529] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165669] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.165672] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   19.165825] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   19.165828] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.165833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.165837] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.165841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.165846] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.165862] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165863] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165864] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.165866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.166005] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.166008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.166278] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.166281] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   19.166286] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   19.166290] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   19.166294] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.166299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.166571] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.166574] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   19.166579] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   19.166583] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   19.166588] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   19.166593] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.166861] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.166865] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   19.166869] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   19.166874] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.166878] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.166883] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.167151] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.167154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.167159] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   19.167163] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   19.167168] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   19.167172] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.167441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.167444] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   19.167449] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   19.167453] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   19.167457] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   19.167462] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.167730] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.167733] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   19.167738] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   19.167742] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   19.167747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   19.167751] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.168020] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.168024] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.168028] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.168032] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.168037] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   19.168042] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   19.168312] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   19.168315] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.168320] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.168324] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.168329] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.168335] nouveau D[     DRM] native mode from preferred
>[   19.168346] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   19.168348] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   19.168350] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   19.168352] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   19.168354] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   19.168356] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   19.168357] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   19.168359] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   19.168361] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   19.168363] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   19.168365] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   19.168367] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   19.168369] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   19.168370] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   19.168372] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   19.168374] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   19.168376] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.751633] pool (6152) used greatest stack depth: 12432 bytes left
>[   19.791722] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.791726] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   19.791736] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   19.791944] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   19.791947] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   19.791951] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.791955] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.791960] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.791964] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   19.791965] nouveau D[     DRM] encoder: 4x270000
>[   19.791966] nouveau D[     DRM] maximum: 4x270000
>[   19.791967] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   19.792134] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.792137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   19.792141] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.792145] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.792149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.792153] nouveau D[     DRM] Sink OUI: 0010fa
>[   19.792154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   19.792323] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   19.792326] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.792330] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.792334] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.792338] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.792342] nouveau D[     DRM] Branch OUI: 000000
>[   19.792344] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.792360] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792361] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792362] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792363] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792502] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.792505] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   19.792658] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   19.792663] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   19.792667] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   19.792671] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.792675] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.792680] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   19.792695] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792695] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792696] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792697] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   19.792835] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   19.792841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.793110] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.793113] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   19.793117] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   19.793121] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   19.793125] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.793129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.793400] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.793405] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   19.793409] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   19.793414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   19.793419] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   19.793423] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.793691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.793694] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   19.793698] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   19.793702] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.793706] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.793710] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.793977] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.793982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   19.793986] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   19.793991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   19.793995] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   19.794000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.794270] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.794274] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   19.794278] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   19.794283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   19.794287] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   19.794292] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.794561] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.794564] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   19.794569] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   19.794573] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   19.794577] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   19.794582] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   19.794849] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   19.794852] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.794856] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.794861] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.794866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   19.794870] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   19.795141] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   19.795144] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.795149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.795153] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   19.795158] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   19.795171] nouveau D[     DRM] native mode from preferred
>[   19.795188] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   19.795191] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   19.795193] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   19.795195] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   19.795197] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   19.795199] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   19.795201] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   19.795203] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   19.795205] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   19.795207] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   19.795209] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   19.795211] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   19.795213] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   19.795215] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   19.795217] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   19.795219] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   19.795228] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   19.795355] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[   19.795357] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1]
>[   19.795368] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> PORT:1d
>[   19.795370] nouveau D[     I2C][0000:01:00.0] AUXCH(3): 9: 0x00000000 8
>[   19.795387] nouveau D[     I2C][0000:01:00.0] AUXCH(3): sink not detected
>[   19.795396] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:03: -> NULL
>[   19.795399] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> PORT:01
>[   19.797577] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:01: -> NULL
>[   19.797581] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-1] disconnected
>[   19.797591] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[   19.797598] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   19.797600] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2]
>[   19.797611] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> PORT:1c
>[   19.797613] nouveau D[     I2C][0000:01:00.0] AUXCH(2): 9: 0x00000000 8
>[   19.797630] nouveau D[     I2C][0000:01:00.0] AUXCH(2): sink not detected
>[   19.797638] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:02: -> NULL
>[   19.797640] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> PORT:00
>[   19.799879] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:X:00: -> NULL
>[   19.799883] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-2] disconnected
>[   19.799888] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   19.799893] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[   19.799895] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[   19.799905] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> PORT:06
>[   19.801059] nouveau D[     I2C][0000:01:00.0][0x00000000] PAD:S:00: -> NULL
>[   19.801061] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[   19.801063] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[   20.015143] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.015147] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   20.015157] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   20.015364] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   20.015367] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   20.015371] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.015375] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.015379] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.015384] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   20.015385] nouveau D[     DRM] encoder: 4x270000
>[   20.015386] nouveau D[     DRM] maximum: 4x270000
>[   20.015387] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   20.015555] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.015559] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   20.015563] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.015567] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.015572] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.015577] nouveau D[     DRM] Sink OUI: 0010fa
>[   20.015578] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   20.015747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.015751] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.015756] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.015760] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.015764] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.015768] nouveau D[     DRM] Branch OUI: 000000
>[   20.015770] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.015787] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.015787] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.015788] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.015789] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.015929] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.015935] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   20.016088] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   20.016091] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.016095] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.016099] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.016103] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.016108] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.016123] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.016124] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.016125] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.016126] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.016266] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.016270] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.016538] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.016542] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   20.016546] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   20.016550] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   20.016554] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.016558] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.016828] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.016831] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   20.016836] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   20.016841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   20.016845] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   20.016849] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.017117] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.017120] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   20.017124] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   20.017129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.017133] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.017138] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.017407] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.017410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.017414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   20.017418] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   20.017422] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   20.017426] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.017695] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.017698] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   20.017702] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   20.017706] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   20.017710] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   20.017714] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.017982] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.017987] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   20.017992] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   20.017997] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   20.018002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   20.018007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.018277] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.018283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.018287] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.018292] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.018296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   20.018302] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   20.018571] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   20.018576] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.018581] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.018586] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.018590] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.018603] nouveau D[     DRM] native mode from preferred
>[   20.018619] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   20.018622] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   20.018624] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   20.018627] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   20.018629] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   20.018631] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   20.018632] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   20.018634] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   20.018637] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   20.018639] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   20.018645] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   20.018647] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   20.018649] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   20.018651] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   20.018652] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   20.018653] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   20.018670] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.021402] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   20.021420] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   20.021421] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.021422] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.021423] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.021563] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   20.057605] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.057610] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   20.057628] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   20.057836] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   20.057841] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   20.057846] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.057851] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.057856] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.057861] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   20.057863] nouveau D[     DRM] encoder: 4x270000
>[   20.057864] nouveau D[     DRM] maximum: 4x270000
>[   20.057866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   20.058036] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.058039] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   20.058044] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.058049] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.058053] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.058058] nouveau D[     DRM] Sink OUI: 0010fa
>[   20.058060] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   20.058230] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.058233] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.058237] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.058241] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.058245] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.058249] nouveau D[     DRM] Branch OUI: 000000
>[   20.058251] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.058267] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058268] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058269] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058270] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.058414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   20.058564] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   20.058568] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.058572] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.058577] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.058581] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.058586] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.058602] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058603] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058603] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058604] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.058742] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.058746] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.059015] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.059020] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   20.059025] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   20.059030] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   20.059034] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.059038] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.059306] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.059310] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   20.059314] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   20.059318] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   20.059322] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   20.059326] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.059594] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.059597] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   20.059601] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   20.059605] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.059609] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.059613] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.059881] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.059884] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.059888] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   20.059892] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   20.059896] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   20.059900] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.060170] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.060174] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   20.060178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   20.060182] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   20.060186] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   20.060190] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.060457] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.060460] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   20.060464] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   20.060469] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   20.060473] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   20.060476] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.060744] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.060747] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.060751] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.060755] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.060759] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   20.060763] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   20.061033] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   20.061036] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.061040] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.061044] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.061048] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.061058] nouveau D[     DRM] native mode from preferred
>[   20.061068] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   20.061070] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   20.061072] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   20.061073] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   20.061074] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   20.061075] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   20.061076] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   20.061078] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   20.061079] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   20.061080] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   20.061081] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   20.061083] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   20.061084] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   20.061085] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   20.061086] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   20.061087] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   20.061094] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.088773] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.088778] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   20.088790] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   20.088995] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   20.088999] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   20.089003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.089012] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.089017] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.089022] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   20.089023] nouveau D[     DRM] encoder: 4x270000
>[   20.089024] nouveau D[     DRM] maximum: 4x270000
>[   20.089025] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   20.089196] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.089199] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   20.089203] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.089208] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.089213] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.089218] nouveau D[     DRM] Sink OUI: 0010fa
>[   20.089219] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   20.089387] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.089390] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.089394] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.089399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.089403] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.089407] nouveau D[     DRM] Branch OUI: 000000
>[   20.089409] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.089425] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089426] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089427] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089427] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089565] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.089568] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   20.089720] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   20.089723] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.089728] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.089733] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.089738] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.089743] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.089758] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089759] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089759] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089760] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.089898] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.089901] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.090171] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.090175] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   20.090179] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   20.090183] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   20.090188] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.090193] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.090463] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.090466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   20.090471] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   20.090475] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   20.090480] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   20.090485] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.090754] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.090757] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   20.090761] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   20.090765] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.090769] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.090773] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.091042] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.091045] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.091049] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   20.091053] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   20.091057] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   20.091061] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.091331] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.091334] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   20.091339] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   20.091344] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   20.091348] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   20.091352] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.091620] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.091624] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   20.091628] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   20.091633] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   20.091638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   20.091642] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.091910] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.091913] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.091917] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.091921] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.091926] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   20.091931] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   20.092200] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   20.092203] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.092207] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.092212] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.092217] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.092229] nouveau D[     DRM] native mode from preferred
>[   20.092240] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   20.092242] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   20.092244] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   20.092245] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   20.092246] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   20.092247] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   20.092249] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   20.092250] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   20.092251] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   20.092252] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   20.092253] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   20.092255] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   20.092256] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   20.092257] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   20.092258] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   20.092259] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   20.092264] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.093422] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.093426] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   20.093435] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   20.093646] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   20.093652] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   20.093657] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.093661] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.093666] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.093672] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   20.093673] nouveau D[     DRM] encoder: 4x270000
>[   20.093674] nouveau D[     DRM] maximum: 4x270000
>[   20.093677] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   20.093845] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.093850] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   20.093854] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.093859] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.093865] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.093871] nouveau D[     DRM] Sink OUI: 0010fa
>[   20.093873] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   20.094041] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.094044] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.094049] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.094053] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.094057] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.094061] nouveau D[     DRM] Branch OUI: 000000
>[   20.094062] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.094079] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094080] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094081] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094082] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094221] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.094224] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   20.094376] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   20.094380] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.094385] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.094389] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.094394] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.094399] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.094414] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094415] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094416] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094416] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.094554] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.094557] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.094827] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.094830] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   20.094834] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   20.094838] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   20.094842] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.094846] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.095115] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.095118] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   20.095122] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   20.095126] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   20.095130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   20.095135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.095404] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.095410] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   20.095415] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   20.095420] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.095425] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.095430] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.095698] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.095701] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.095705] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   20.095709] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   20.095713] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   20.095717] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.095985] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.095990] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   20.095995] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   20.095999] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   20.096004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   20.096009] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.096278] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.096281] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   20.096285] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   20.096289] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   20.096293] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   20.096299] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.096571] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.096575] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.096580] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.096585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.096590] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   20.096595] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   20.096869] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   20.096873] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.096878] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.096883] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.096888] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.096897] nouveau D[     DRM] native mode from preferred
>[   20.096908] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   20.096910] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   20.096911] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   20.096913] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   20.096914] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   20.096915] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   20.096916] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   20.096917] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   20.096919] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   20.096920] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   20.096921] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   20.096922] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   20.096924] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   20.096925] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   20.096926] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   20.096927] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   20.096932] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.111309] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.111314] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   20.111334] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   20.111544] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   20.111550] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   20.111554] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.111559] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.111564] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.111569] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   20.111570] nouveau D[     DRM] encoder: 4x270000
>[   20.111571] nouveau D[     DRM] maximum: 4x270000
>[   20.111573] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   20.111746] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.111751] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   20.111756] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.111760] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.111765] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.111770] nouveau D[     DRM] Sink OUI: 0010fa
>[   20.111772] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   20.111943] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.111948] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.111953] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.111958] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.111963] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.111968] nouveau D[     DRM] Branch OUI: 000000
>[   20.111970] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.111988] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.111989] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.111991] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.111993] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.112130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.112135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   20.112288] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   20.112291] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.112296] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.112301] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.112305] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.112310] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.112325] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.112325] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.112326] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.112327] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.112466] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.112470] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.112737] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.112740] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   20.112744] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   20.112748] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   20.112753] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.112757] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.113025] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.113028] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   20.113032] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   20.113036] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   20.113040] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   20.113045] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.113314] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.113318] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   20.113322] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   20.113327] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.113331] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.113335] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.113605] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.113608] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.113612] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   20.113616] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   20.113620] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   20.113624] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.113893] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.113896] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   20.113900] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   20.113904] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   20.113908] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   20.113913] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.114182] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.114186] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   20.114190] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   20.114194] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   20.114198] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   20.114202] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.114468] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.114471] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.114475] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.114479] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.114483] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   20.114487] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   20.114759] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   20.114763] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.114767] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.114772] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.114776] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.114787] nouveau D[     DRM] native mode from preferred
>[   20.114801] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   20.114804] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   20.114805] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   20.114806] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   20.114808] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   20.114809] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   20.114810] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   20.114811] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   20.114812] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   20.114814] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   20.114815] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   20.114816] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   20.114817] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   20.114819] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   20.114820] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   20.114821] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   20.114826] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.121045] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.121049] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[   20.121060] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[   20.121269] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[   20.121274] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41840a11
>[   20.121279] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.121283] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.121288] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.121293] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[   20.121294] nouveau D[     DRM] encoder: 4x270000
>[   20.121295] nouveau D[     DRM] maximum: 4x270000
>[   20.121297] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000400 3
>[   20.121464] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.121467] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41fa1000
>[   20.121471] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.121476] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.121480] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.121485] nouveau D[     DRM] Sink OUI: 0010fa
>[   20.121487] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000500 3
>[   20.121659] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   20.121664] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.121670] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.121675] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.121681] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.121687] nouveau D[     DRM] Branch OUI: 000000
>[   20.121691] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.121708] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.121710] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.121711] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.121712] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.121851] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.121855] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[   20.122007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[   20.122010] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x41000000
>[   20.122015] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xc0010000
>[   20.122019] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.122023] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.122029] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[   20.122046] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.122047] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.122048] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.122049] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   20.122186] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[   20.122190] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.122457] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.122461] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[   20.122465] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[   20.122470] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa0221006
>[   20.122474] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.122479] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.122749] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.122752] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x04011704
>[   20.122756] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x781521a5
>[   20.122761] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa7b16f02
>[   20.122765] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259e4c55
>[   20.122770] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.123042] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.123045] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0054500c
>[   20.123050] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010000
>[   20.123054] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.123059] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.123063] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.123333] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.123336] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[   20.123341] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x83ef0101
>[   20.123345] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x08b0a040
>[   20.123350] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20307034
>[   20.123355] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.123628] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.123633] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xcf4b0036
>[   20.123638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000010
>[   20.123642] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfc000000
>[   20.123656] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x6c6f4300
>[   20.123670] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.123940] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.123945] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c20726f
>[   20.123950] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x200a4443
>[   20.123954] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[   20.123959] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00001000
>[   20.123963] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[   20.124232] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[   20.124235] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.124239] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.124243] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.124248] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x10000000
>[   20.124253] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[   20.124523] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[   20.124526] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.124530] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.124535] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   20.124539] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   20.124551] nouveau D[     DRM] native mode from preferred
>[   20.124566] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[   20.124569] [drm:drm_mode_debug_printmodeline] Modeline 46:"2880x1800" 60 337750 2880 2928 2960 3040 1800 1803 1809 1852 0x48 0x9
>[   20.124571] [drm:drm_mode_debug_printmodeline] Modeline 48:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>[   20.124573] [drm:drm_mode_debug_printmodeline] Modeline 49:"1920x1080" 60 173000 1920 2048 2248 2576 1080 1083 1088 1120 0x0 0x6
>[   20.124575] [drm:drm_mode_debug_printmodeline] Modeline 51:"1600x1200" 60 161000 1600 1712 1880 2160 1200 1203 1207 1245 0x0 0x6
>[   20.124576] [drm:drm_mode_debug_printmodeline] Modeline 50:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x0 0x6
>[   20.124578] [drm:drm_mode_debug_printmodeline] Modeline 52:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x0 0x6
>[   20.124584] [drm:drm_mode_debug_printmodeline] Modeline 53:"1280x1024" 60 109000 1280 1368 1496 1712 1024 1027 1034 1063 0x0 0x6
>[   20.124587] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x960" 60 101250 1280 1360 1488 1696 960 963 967 996 0x0 0x6
>[   20.124589] [drm:drm_mode_debug_printmodeline] Modeline 55:"1152x864" 60 81750 1152 1216 1336 1520 864 867 871 897 0x0 0x6
>[   20.124591] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x6
>[   20.124593] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 60 38250 800 832 912 1024 600 603 607 624 0x0 0x6
>[   20.124595] [drm:drm_mode_debug_printmodeline] Modeline 59:"640x480" 59 23750 640 664 720 800 480 483 487 500 0x0 0x6
>[   20.124597] [drm:drm_mode_debug_printmodeline] Modeline 58:"720x400" 60 22250 720 744 808 896 400 403 413 417 0x0 0x6
>[   20.124599] [drm:drm_mode_debug_printmodeline] Modeline 60:"640x400" 60 20000 640 664 720 800 400 403 409 417 0x0 0x6
>[   20.124601] [drm:drm_mode_debug_printmodeline] Modeline 61:"640x350" 60 17500 640 664 720 800 350 353 363 366 0x0 0x6
>[   20.124606] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   20.168725] [drm:drm_mode_addfb2] [FB:62]
>[   20.188214] [drm:drm_mode_addfb2] [FB:64]
>[   20.215895] [drm:drm_mode_addfb2] [FB:62]
>[   20.251256] [drm:drm_mode_addfb2] [FB:64]
>[   20.267124] [drm:drm_mode_addfb2] [FB:62]
>[   20.283693] [drm:drm_mode_addfb2] [FB:64]
>[   20.300331] [drm:drm_mode_addfb2] [FB:62]
>[   20.316979] [drm:drm_mode_addfb2] [FB:64]
>[   20.333631] [drm:drm_mode_addfb2] [FB:62]
>[   20.350710] [drm:drm_mode_addfb2] [FB:64]
>[   20.367024] [drm:drm_mode_addfb2] [FB:62]
>[   20.383550] [drm:drm_mode_addfb2] [FB:64]
>[   20.400271] [drm:drm_mode_addfb2] [FB:62]
>[   20.418110] [drm:drm_mode_addfb2] [FB:64]
>[   20.450235] [drm:drm_mode_addfb2] [FB:62]
>[   20.466875] [drm:drm_mode_addfb2] [FB:64]
>[   20.483470] [drm:drm_mode_addfb2] [FB:62]
>[   20.500128] [drm:drm_mode_addfb2] [FB:64]
>[   20.516778] [drm:drm_mode_addfb2] [FB:62]
>[   20.549497] [drm:drm_mode_addfb2] [FB:64]
>[   20.568160] [drm:drm_mode_addfb2] [FB:62]
>[   20.600179] [drm:drm_mode_addfb2] [FB:64]
>[   20.633402] [drm:drm_mode_addfb2] [FB:62]
>[   20.666796] [drm:drm_mode_addfb2] [FB:64]
>[   20.704660] [drm:drm_mode_addfb2] [FB:62]
>[   21.493493] [drm:drm_mode_addfb2] [FB:64]
>[   21.523090] [drm:drm_mode_addfb2] [FB:62]
>[   21.538582] [drm:drm_mode_addfb2] [FB:64]
>[   21.555678] [drm:drm_mode_addfb2] [FB:62]
>[   21.573501] [drm:drm_mode_addfb2] [FB:64]
>[   21.602525] [drm:drm_mode_addfb2] [FB:62]
>[   21.622142] [drm:drm_mode_addfb2] [FB:64]
>[   21.650122] [drm:drm_mode_addfb2] [FB:62]
>[   21.668825] [drm:drm_mode_addfb2] [FB:64]
>[   21.688488] [drm:drm_mode_addfb2] [FB:62]
>[   21.708630] [drm:drm_mode_addfb2] [FB:64]
>[   21.771868] [drm:drm_mode_addfb2] [FB:62]
>[   21.894413] [drm:drm_mode_addfb2] [FB:64]
>[   21.985716] [drm:drm_mode_addfb2] [FB:62]
>[   22.078410] [drm:drm_mode_addfb2] [FB:64]
>[   22.088053] [drm:drm_mode_addfb2] [FB:62]
>[   22.105420] [drm:drm_mode_addfb2] [FB:64]
>[   22.164447] traps: gom-flickr-mine[6350] trap int3 ip:7fbfb009413a sp:7ffc9176dd30 error:0
>[   22.284258] [drm:drm_mode_addfb2] [FB:62]
>[   22.573302] [drm:drm_mode_addfb2] [FB:64]
>[   22.619908] [drm:drm_mode_addfb2] [FB:62]
>[   22.654990] [drm:drm_mode_addfb2] [FB:64]
>[   22.685009] [drm:drm_mode_addfb2] [FB:62]
>[   22.719403] [drm:drm_mode_addfb2] [FB:64]
>[   22.756356] [drm:drm_mode_addfb2] [FB:62]
>[   22.770219] [drm:drm_mode_addfb2] [FB:64]
>[   22.786846] [drm:drm_mode_addfb2] [FB:62]
>[   22.804556] [drm:drm_mode_addfb2] [FB:64]
>[   22.820233] [drm:drm_mode_addfb2] [FB:62]
>[   22.844541] [drm:drm_mode_addfb2] [FB:64]
>[   23.016416] [drm:drm_mode_addfb2] [FB:62]
>[   23.087311] task557[6814]: segfault at 1e8 ip 00007fd73afa1e33 sp 00007fd57f67db90 error 4 in libgstlibav.so[7fd73af7c000+36000]
>[   24.674097] [drm:drm_mode_addfb2] [FB:64]
>[   31.993066] [drm:drm_mode_addfb2] [FB:62]
>[   32.013361] [drm:drm_mode_addfb2] [FB:64]
>[   34.241899] [drm:drm_mode_addfb2] [FB:62]
>[   37.093652] [drm:drm_mode_addfb2] [FB:64]
>[   37.444527] [drm:drm_mode_addfb2] [FB:62]
>[   39.832337] [drm:drm_mode_addfb2] [FB:64]
>[   46.841455] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   46.841516] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000002
>[   46.841520] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   46.841524] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   46.841528] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   46.841671] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.727588] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[   49.727621] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   49.727626] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.727630] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.727634] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.727778] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.729940] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[   49.730117] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[   49.730126] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0000840a
>[   49.730133] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.730140] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.730147] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.730156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[   49.730329] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[   49.730336] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803333
>[   49.730343] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.730351] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.730358] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.730379] nouveau T[   VBIOS][0000:01:00.0] 0x6501[0]: NV_REG	R[0x00ea80] &= 0xfffffffd |= 0x00000002
>[   49.730394] nouveau T[   VBIOS][0000:01:00.0] 0x650e[0]: SUB_DIRECT	0x66f2
>[   49.730400] nouveau T[   VBIOS][0000:01:00.0] 0x66f2[1]: AUXCH	AUX[0x00000107] 0x01
>[   49.730404] nouveau T[   VBIOS][0000:01:00.0] 0x66f8[1]: 	AUX[0x00000107] &= 0xef |= 0x10
>[   49.730411] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000107 1
>[   49.730578] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.730585] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803310
>[   49.730592] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.730599] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.730606] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.730614] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000107 1
>[   49.730634] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000010
>[   49.730638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.730641] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.730645] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.730789] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.730797] nouveau T[   VBIOS][0000:01:00.0] 0x66fa[1]: DONE
>[   49.730800] nouveau T[   VBIOS][0000:01:00.0] 0x6511[0]: DONE
>[   49.730805] nouveau T[   VBIOS][0000:01:00.0] 0x5f17[0]: NV_REG	R[0x00e800] &= 0xfffffcff |= 0x00000300
>[   49.730821] nouveau T[   VBIOS][0000:01:00.0] 0x5f24[0]: NV_REG	R[0x00e820] &= 0xfffffcff |= 0x00000300
>[   49.730829] nouveau T[   VBIOS][0000:01:00.0] 0x5f31[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[   49.730836] nouveau T[   VBIOS][0000:01:00.0] 0x5f3e[0]: NV_REG	R[0x40612300] &= 0xfcffffff |= 0x03000000
>[   49.730872] nouveau T[   VBIOS][0000:01:00.0] 0x5f4b[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000002
>[   49.730888] nouveau T[   VBIOS][0000:01:00.0] 0x5f58[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[   49.730893] nouveau T[   VBIOS][0000:01:00.0] 0x5f61[0]: ZM_REG	R[0x4061c010] = 0x0040152f
>[   49.730897] nouveau T[   VBIOS][0000:01:00.0] 0x5f6a[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[   49.730902] nouveau T[   VBIOS][0000:01:00.0] 0x5f73[0]: NV_REG	R[0x4061c138] &= 0xfffffffc |= 0x00000000
>[   49.730909] nouveau T[   VBIOS][0000:01:00.0] 0x5f80[0]: TIME	0x03e8
>[   49.731913] nouveau T[   VBIOS][0000:01:00.0] 0x5f83[0]: SUB_DIRECT	0x4a48
>[   49.731918] nouveau T[   VBIOS][0000:01:00.0] 0x4a48[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[   49.731933] nouveau T[   VBIOS][0000:01:00.0] 0x4a55[1]: TIME	0x0064
>[   49.732037] nouveau T[   VBIOS][0000:01:00.0] 0x4a58[1]: CONDITION	0x06
>[   49.732044] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   49.732060] nouveau T[   VBIOS][0000:01:00.0] 0x4a5a[ ]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[   49.732063] nouveau T[   VBIOS][0000:01:00.0] 0x4a67[ ]: RESUME
>[   49.732068] nouveau T[   VBIOS][0000:01:00.0] 0x4a68[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[   49.732083] nouveau T[   VBIOS][0000:01:00.0] 0x4a75[1]: TIME	0x0064
>[   49.732186] nouveau T[   VBIOS][0000:01:00.0] 0x4a78[1]: CONDITION	0x06
>[   49.732192] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   49.732207] nouveau T[   VBIOS][0000:01:00.0] 0x4a7a[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[   49.732214] nouveau T[   VBIOS][0000:01:00.0] 0x4a87[1]: RESUME
>[   49.732218] nouveau T[   VBIOS][0000:01:00.0] 0x4a88[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[   49.732225] nouveau T[   VBIOS][0000:01:00.0] 0x4a95[1]: TIME	0x0064
>[   49.732328] nouveau T[   VBIOS][0000:01:00.0] 0x4a98[1]: CONDITION	0x06
>[   49.732333] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   49.732349] nouveau T[   VBIOS][0000:01:00.0] 0x4a9a[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[   49.732356] nouveau T[   VBIOS][0000:01:00.0] 0x4aa7[1]: RESUME
>[   49.732360] nouveau T[   VBIOS][0000:01:00.0] 0x4aa8[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[   49.732367] nouveau T[   VBIOS][0000:01:00.0] 0x4ab5[1]: TIME	0x0064
>[   49.732471] nouveau T[   VBIOS][0000:01:00.0] 0x4ab8[1]: CONDITION	0x06
>[   49.732476] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[   49.732491] nouveau T[   VBIOS][0000:01:00.0] 0x4aba[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[   49.732497] nouveau T[   VBIOS][0000:01:00.0] 0x4ac7[1]: RESUME
>[   49.732501] nouveau T[   VBIOS][0000:01:00.0] 0x4ac8[1]: DONE
>[   49.732505] nouveau T[   VBIOS][0000:01:00.0] 0x5f86[0]: NV_REG	R[0x40612300] &= 0xfffcffff |= 0x00010000
>[   49.732520] nouveau T[   VBIOS][0000:01:00.0] 0x5f93[0]: TIME	0x0032
>[   49.732575] nouveau T[   VBIOS][0000:01:00.0] 0x5f96[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[   49.732590] nouveau T[   VBIOS][0000:01:00.0] 0x5fa3[0]: NV_REG	R[0x4061c034] &= 0x7fee0fff |= 0x80000000
>[   49.732597] nouveau T[   VBIOS][0000:01:00.0] 0x5fb0[0]: CONDITION_TIME	0x14 0xff
>[   49.732602] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: 	[0x14] (R[0x4061c034] & 0x80000000) == 0x00000000
>[   49.732617] nouveau T[   VBIOS][0000:01:00.0] 0x5fb3[0]: TIME	0x000a
>[   49.732632] nouveau T[   VBIOS][0000:01:00.0] 0x5fb6[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[   49.732648] nouveau T[   VBIOS][0000:01:00.0] 0x5fc3[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x00000000
>[   49.732655] nouveau T[   VBIOS][0000:01:00.0] 0x5fd0[0]: AUXCH	AUX[0x00000102] 0x01
>[   49.732659] nouveau T[   VBIOS][0000:01:00.0] 0x5fd6[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[   49.732664] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   49.732829] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.732836] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803300
>[   49.732847] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.732854] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.732861] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.732869] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   49.732890] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[   49.732895] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.732900] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.732906] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733051] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.733059] nouveau T[   VBIOS][0000:01:00.0] 0x5fd8[0]: DP_CONDITION	0x05 0x15
>[   49.733063] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[   49.733221] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.733228] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803301
>[   49.733234] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.733240] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.733246] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.733254] nouveau T[   VBIOS][0000:01:00.0] 0x5fdb[0]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[   49.733261] nouveau T[   VBIOS][0000:01:00.0] 0x5fe8[0]: AUXCH	AUX[0x0000010a] 0x01
>[   49.733265] nouveau T[   VBIOS][0000:01:00.0] 0x5fee[0]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[   49.733269] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000010a 1
>[   49.733435] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.733441] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803301
>[   49.733447] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.733453] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.733460] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.733467] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x0000010a 1
>[   49.733486] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[   49.733489] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733492] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733495] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733638] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.733644] nouveau T[   VBIOS][0000:01:00.0] 0x5ff0[0]: DONE
>[   49.733649] nouveau T[   VBIOS][0000:01:00.0] 0x643c[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[   49.733653] nouveau T[   VBIOS][0000:01:00.0] 0x6445[0]: NV_REG	R[0x4061c010] &= 0xff0fffff |= 0x00400000
>[   49.733660] nouveau T[   VBIOS][0000:01:00.0] 0x6452[0]: NV_REG	R[0x4061c014] &= 0xffffffff |= 0x00000000
>[   49.733666] nouveau T[   VBIOS][0000:01:00.0] 0x645f[0]: DONE
>[   49.733686] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[   49.733705] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x0000840a
>[   49.733709] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733712] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733715] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.733866] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[   49.733876] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   49.734034] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.734041] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00803320
>[   49.734047] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.734053] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.734059] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.734066] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   49.734085] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[   49.734088] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734091] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734094] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734237] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.734300] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[   49.734319] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734322] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734325] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734328] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.734492] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[   49.734600] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[   49.734801] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[   49.734808] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803333
>[   49.734814] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.734820] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.734826] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.734836] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   49.734997] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.735003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01803321
>[   49.735010] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.735016] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.735022] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.735029] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   49.735048] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[   49.735051] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.735054] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.735057] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.735200] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.735607] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[   49.735808] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[   49.735815] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817777
>[   49.735821] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.735826] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.735833] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.735846] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   49.736003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.736010] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817722
>[   49.736016] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.736022] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.736028] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.736035] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   49.736055] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[   49.736058] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736061] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736064] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736207] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.736214] nouveau T[   VBIOS][0000:01:00.0] 0x5ff1[0]: NV_REG	R[0x4061c110] &= 0xe0e0e0e0 |= 0x10101010
>[   49.736221] nouveau T[   VBIOS][0000:01:00.0] 0x5ffe[0]: AUXCH	AUX[0x00000102] 0x01
>[   49.736224] nouveau T[   VBIOS][0000:01:00.0] 0x6004[0]: 	AUX[0x00000102] &= 0xdc |= 0x00
>[   49.736228] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[   49.736394] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[   49.736401] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817720
>[   49.736407] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.736413] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[   49.736419] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xde000000
>[   49.736426] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[   49.736445] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736448] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736451] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736454] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[   49.736597] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[   49.736603] nouveau T[   VBIOS][0000:01:00.0] 0x6006[0]: DONE
>[   52.673215] [drm:drm_mode_addfb2] [FB:62]

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