Attachment 118665 Details for Bug 91278 – valley vm fault dump

valley vm fault dump

valley_x64_490_00000000 (text/plain), 1.78 MB, created by Andy Furniss on 2015-10-05 08:54:37 UTC

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Description:

Filename:

MIME Type:

Creator: Andy Furniss

Created: 2015-10-05 08:54:37 UTC

Size: 1.78 MB

patch

obsolete

>VM fault report.
>
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD TONGA (DRM 3.1.0, LLVM 3.8.0)
>
>Failing VM page: 0x0015703d
>
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>           1    0x0000000100111       0x0000000100112       TRACE
>           2    -- hole --
>          37    0x0000000100114       0x0000000100139       SAMPLER_TEXTURE
>           9    -- hole --
>           2    0x0000000100142       0x0000000100144       SAMPLER_TEXTURE
>          44    -- hole --
>           2    0x0000000100170       0x0000000100172       SAMPLER_TEXTURE
>         178    -- hole --
>           1    0x0000000100224       0x0000000100225       USER_SHADER
>          22    -- hole --
>           1    0x000000010023b       0x000000010023c       IB2
>        5416    -- hole --
>          44    0x0000000101764       0x0000000101790       SAMPLER_TEXTURE
>          32    -- hole --
>          16    0x00000001017b0       0x00000001017c0       BORDER_COLORS
>          20    -- hole --
>         256    0x00000001017d4       0x00000001018d4       CONST_BUFFER, DESCRIPTORS
>        1260    -- hole --
>         172    0x0000000101dc0       0x0000000101e6c       SAMPLER_TEXTURE
>         212    -- hole --
>         172    0x0000000101f40       0x0000000101fec       SAMPLER_TEXTURE
>         148    -- hole --
>          87    0x0000000102080       0x00000001020d7       SAMPLER_TEXTURE
>         105    -- hole --
>         343    0x0000000102140       0x0000000102297       SAMPLER_TEXTURE
>         131    -- hole --
>          12    0x000000010231a       0x0000000102326       SAMPLER_TEXTURE
>         486    -- hole --
>          12    0x000000010250c       0x0000000102518       SAMPLER_TEXTURE
>         360    -- hole --
>         683    0x0000000102680       0x000000010292b       SAMPLER_TEXTURE
>         285    -- hole --
>         256    0x0000000102a48       0x0000000102b48       VERTEX_BUFFER
>         180    -- hole --
>           4    0x0000000102bfc       0x0000000102c00       SAMPLER_TEXTURE
>          64    -- hole --
>         684    0x0000000102c40       0x0000000102eec       SAMPLER_TEXTURE
>         115    -- hole --
>          25    0x0000000102f5f       0x0000000102f78       VERTEX_BUFFER
>           8    -- hole --
>         343    0x0000000102f80       0x00000001030d7       SAMPLER_TEXTURE
>         586    -- hole --
>           2    0x0000000103321       0x0000000103323       VERTEX_BUFFER
>           2    -- hole --
>           2    0x0000000103325       0x0000000103327       VERTEX_BUFFER
>           2    0x0000000103327       0x0000000103329       VERTEX_BUFFER
>          28    -- hole --
>           2    0x0000000103345       0x0000000103347       VERTEX_BUFFER
>           2    0x0000000103347       0x0000000103349       VERTEX_BUFFER
>           2    0x0000000103349       0x000000010334b       VERTEX_BUFFER
>           2    0x000000010334b       0x000000010334d       VERTEX_BUFFER
>           2    0x000000010334d       0x000000010334f       VERTEX_BUFFER
>           2    0x000000010334f       0x0000000103351       VERTEX_BUFFER
>           2    0x0000000103351       0x0000000103353       VERTEX_BUFFER
>           2    0x0000000103353       0x0000000103355       VERTEX_BUFFER
>           2    0x0000000103355       0x0000000103357       VERTEX_BUFFER
>           2    0x0000000103357       0x0000000103359       VERTEX_BUFFER
>          76    -- hole --
>           1    0x00000001033a5       0x00000001033a6       SAMPLER_TEXTURE
>           1    0x00000001033a6       0x00000001033a7       USER_SHADER
>           1    0x00000001033a7       0x00000001033a8       USER_SHADER
>           9    -- hole --
>           1    0x00000001033b1       0x00000001033b2       USER_SHADER
>           1    0x00000001033b2       0x00000001033b3       USER_SHADER
>          24    -- hole --
>         115    0x00000001033cb       0x000000010343e       VERTEX_BUFFER
>         150    -- hole --
>          44    0x00000001034d4       0x0000000103500       SAMPLER_TEXTURE
>         172    0x0000000103500       0x00000001035ac       SAMPLER_TEXTURE
>         212    -- hole --
>         172    0x0000000103680       0x000000010372c       SAMPLER_TEXTURE
>          87    0x000000010372c       0x0000000103783       SAMPLER_TEXTURE
>           4    -- hole --
>           2    0x0000000103787       0x0000000103789       VERTEX_BUFFER
>           2    -- hole --
>           2    0x000000010378b       0x000000010378d       VERTEX_BUFFER
>           2    -- hole --
>           2    0x000000010378f       0x0000000103791       VERTEX_BUFFER
>           2    0x0000000103791       0x0000000103793       VERTEX_BUFFER
>           2    0x0000000103793       0x0000000103795       VERTEX_BUFFER
>           2    0x0000000103795       0x0000000103797       VERTEX_BUFFER
>           2    0x0000000103797       0x0000000103799       VERTEX_BUFFER
>           2    0x0000000103799       0x000000010379b       VERTEX_BUFFER
>           2    0x000000010379b       0x000000010379d       VERTEX_BUFFER
>           2    0x000000010379d       0x000000010379f       VERTEX_BUFFER
>           2    0x000000010379f       0x00000001037a1       VERTEX_BUFFER
>           2    0x00000001037a1       0x00000001037a3       VERTEX_BUFFER
>          57    -- hole --
>          23    0x00000001037dc       0x00000001037f3       SAMPLER_TEXTURE
>         197    -- hole --
>          17    0x00000001038b8       0x00000001038c9       INDEX_BUFFER
>          55    -- hole --
>          87    0x0000000103900       0x0000000103957       SAMPLER_TEXTURE
>         233    -- hole --
>          87    0x0000000103a40       0x0000000103a97       SAMPLER_TEXTURE
>        2345    -- hole --
>       20741    0x00000001043c0       0x00000001094c5       CP_DMA, COLOR_BUFFER_MSAA
>          44    0x00000001094c5       0x00000001094f1       SAMPLER_TEXTURE
>          15    -- hole --
>       20741    0x0000000109500       0x000000010e605       CP_DMA, COLOR_BUFFER_MSAA
>          32    -- hole --
>          23    0x000000010e625       0x000000010e63c       SAMPLER_TEXTURE
>           4    -- hole --
>       20741    0x000000010e640       0x0000000113745       CP_DMA, COLOR_BUFFER_MSAA
>          48    0x0000000113745       0x0000000113775       HTILE
>          11    -- hole --
>       20741    0x0000000113780       0x0000000118885       CP_DMA, COLOR_BUFFER_MSAA
>          10    -- hole --
>           1    0x000000011888f       0x0000000118890       USER_SHADER
>           1    0x0000000118890       0x0000000118891       USER_SHADER
>          15    -- hole --
>       23040    0x00000001188a0       0x000000011e2a0       DEPTH_BUFFER_MSAA
>           1    0x000000011e2a0       0x000000011e2a1       USER_SHADER
>       36900    -- hole --
>          44    0x00000001272c5       0x00000001272f1       SAMPLER_TEXTURE
>        1787    -- hole --
>          51    0x00000001279ec       0x0000000127a1f       VERTEX_BUFFER
>         440    -- hole --
>         256    0x0000000127bd7       0x0000000127cd7       HTILE
>          95    -- hole --
>           1    0x0000000127d36       0x0000000127d37       USER_SHADER
>           1    0x0000000127d37       0x0000000127d38       USER_SHADER
>           4    -- hole --
>           1    0x0000000127d3c       0x0000000127d3d       USER_SHADER
>           1    0x0000000127d3d       0x0000000127d3e       USER_SHADER
>         473    -- hole --
>          78    0x0000000127f17       0x0000000127f65       VERTEX_BUFFER
>           2    -- hole --
>           7    0x0000000127f67       0x0000000127f6e       INDEX_BUFFER
>          18    -- hole --
>          87    0x0000000127f80       0x0000000127fd7       SAMPLER_TEXTURE
>        2023    -- hole --
>         289    0x00000001287be       0x00000001288df       VERTEX_BUFFER
>        1156    -- hole --
>         289    0x0000000128d63       0x0000000128e84       VERTEX_BUFFER
>         688    0x0000000128e84       0x0000000129134       INDEX_BUFFER
>         716    -- hole --
>         256    0x0000000129400       0x0000000129500       CONST_BUFFER, DESCRIPTORS
>          64    -- hole --
>         684    0x0000000129540       0x00000001297ec       SAMPLER_TEXTURE
>         660    -- hole --
>        1367    0x0000000129a80       0x0000000129fd7       SAMPLER_TEXTURE
>        1280    -- hole --
>          63    0x000000012a4d7       0x000000012a516       VERTEX_BUFFER
>          42    -- hole --
>         684    0x000000012a540       0x000000012a7ec       SAMPLER_TEXTURE
>         363    -- hole --
>          15    0x000000012a957       0x000000012a966       VERTEX_BUFFER
>         282    -- hole --
>         343    0x000000012aa80       0x000000012abd7       SAMPLER_TEXTURE
>         192    -- hole --
>          47    0x000000012ac97       0x000000012acc6       VERTEX_BUFFER
>         122    -- hole --
>        1367    0x000000012ad40       0x000000012b297       SAMPLER_TEXTURE
>          20    -- hole --
>          15    0x000000012b2ab       0x000000012b2ba       VERTEX_BUFFER
>         135    -- hole --
>          44    0x000000012b341       0x000000012b36d       SAMPLER_TEXTURE
>         339    -- hole --
>         128    0x000000012b4c0       0x000000012b540       SAMPLER_TEXTURE
>          57    -- hole --
>          63    0x000000012b579       0x000000012b5b8       VERTEX_BUFFER
>         450    -- hole --
>           4    0x000000012b77a       0x000000012b77e       VERTEX_BUFFER
>         114    -- hole --
>           2    0x000000012b7f0       0x000000012b7f2       VERTEX_BUFFER
>           1    0x000000012b7f2       0x000000012b7f3       USER_SHADER
>           1    0x000000012b7f3       0x000000012b7f4       USER_SHADER
>           1    -- hole --
>           1    0x000000012b7f5       0x000000012b7f6       USER_SHADER
>          10    -- hole --
>        1367    0x000000012b800       0x000000012bd57       SAMPLER_TEXTURE
>          28    -- hole --
>          11    0x000000012bd73       0x000000012bd7e       VERTEX_BUFFER
>         874    -- hole --
>          16    0x000000012c0e8       0x000000012c0f8       VERTEX_BUFFER
>           4    0x000000012c0f8       0x000000012c0fc       VERTEX_BUFFER
>         100    -- hole --
>          32    0x000000012c160       0x000000012c180       SAMPLER_TEXTURE
>          24    0x000000012c180       0x000000012c198       VERTEX_BUFFER
>         379    -- hole --
>           3    0x000000012c313       0x000000012c316       VERTEX_BUFFER
>          31    -- hole --
>          47    0x000000012c335       0x000000012c364       VERTEX_BUFFER
>         755    -- hole --
>           2    0x000000012c657       0x000000012c659       VERTEX_BUFFER
>           1    0x000000012c659       0x000000012c65a       VERTEX_BUFFER
>          11    0x000000012c65a       0x000000012c665       VERTEX_BUFFER
>          14    0x000000012c665       0x000000012c673       VERTEX_BUFFER
>          18    0x000000012c673       0x000000012c685       VERTEX_BUFFER
>          76    0x000000012c685       0x000000012c6d1       VERTEX_BUFFER
>          17    -- hole --
>         101    0x000000012c6e2       0x000000012c747       VERTEX_BUFFER
>          23    -- hole --
>         101    0x000000012c75e       0x000000012c7c3       VERTEX_BUFFER
>          23    -- hole --
>          27    0x000000012c7da       0x000000012c7f5       VERTEX_BUFFER
>          26    0x000000012c7f5       0x000000012c80f       VERTEX_BUFFER
>          27    0x000000012c80f       0x000000012c82a       VERTEX_BUFFER
>         341    -- hole --
>           1    0x000000012c97f       0x000000012c980       VERTEX_BUFFER
>          87    0x000000012c980       0x000000012c9d7       SAMPLER_TEXTURE
>         105    -- hole --
>          87    0x000000012ca40       0x000000012ca97       SAMPLER_TEXTURE
>        1024    -- hole --
>           1    0x000000012ce97       0x000000012ce98       USER_SHADER
>           1    0x000000012ce98       0x000000012ce99       USER_SHADER
>           1    0x000000012ce99       0x000000012ce9a       USER_SHADER
>           1    0x000000012ce9a       0x000000012ce9b       USER_SHADER
>           1    0x000000012ce9b       0x000000012ce9c       USER_SHADER
>           1    0x000000012ce9c       0x000000012ce9d       USER_SHADER
>           1    0x000000012ce9d       0x000000012ce9e       USER_SHADER
>           7    -- hole --
>          10    0x000000012cea5       0x000000012ceaf       INDEX_BUFFER
>        4625    -- hole --
>       16384    0x000000012e0c0       0x00000001320c0       DEPTH_BUFFER
>        9847    -- hole --
>           7    0x0000000134737       0x000000013473e       VERTEX_BUFFER
>           2    -- hole --
>          87    0x0000000134740       0x0000000134797       SAMPLER_TEXTURE
>         105    -- hole --
>          87    0x0000000134800       0x0000000134857       SAMPLER_TEXTURE
>        1295    -- hole --
>          16    0x0000000134d66       0x0000000134d76       VERTEX_BUFFER
>          44    0x0000000134d76       0x0000000134da2       SAMPLER_TEXTURE
>          30    -- hole --
>        4608    0x0000000134dc0       0x0000000135fc0       SCRATCH_BUFFER
>         634    -- hole --
>           6    0x000000013623a       0x0000000136240       INDEX_BUFFER
>         126    -- hole --
>           1    0x00000001362be       0x00000001362bf       INDEX_BUFFER
>         113    -- hole --
>           1    0x0000000136330       0x0000000136331       USER_SHADER
>           1    0x0000000136331       0x0000000136332       VERTEX_BUFFER
>        2047    -- hole --
>           2    0x0000000136b31       0x0000000136b33       INDEX_BUFFER
>           1    0x0000000136b33       0x0000000136b34       USER_SHADER
>         610    -- hole --
>           1    0x0000000136d96       0x0000000136d97       USER_SHADER
>          32    -- hole --
>           1    0x0000000136db7       0x0000000136db8       USER_SHADER
>           7    -- hole --
>           1    0x0000000136dbf       0x0000000136dc0       VERTEX_BUFFER
>       13504    -- hole --
>          87    0x000000013a280       0x000000013a2d7       SAMPLER_TEXTURE
>          18    -- hole --
>           1    0x000000013a2e9       0x000000013a2ea       USER_SHADER
>           1    0x000000013a2ea       0x000000013a2eb       USER_SHADER
>          21    -- hole --
>          87    0x000000013a300       0x000000013a357       SAMPLER_TEXTURE
>          36    -- hole --
>           1    0x000000013a37b       0x000000013a37c       USER_SHADER
>           1    0x000000013a37c       0x000000013a37d       USER_SHADER
>           3    -- hole --
>          87    0x000000013a380       0x000000013a3d7       SAMPLER_TEXTURE
>          38    -- hole --
>           1    0x000000013a3fd       0x000000013a3fe       USER_SHADER
>           1    0x000000013a3fe       0x000000013a3ff       USER_SHADER
>           1    0x000000013a3ff       0x000000013a400       USER_SHADER
>          87    0x000000013a400       0x000000013a457       SAMPLER_TEXTURE
>          27    -- hole --
>           1    0x000000013a472       0x000000013a473       USER_SHADER
>           1    0x000000013a473       0x000000013a474       USER_SHADER
>           9    0x000000013a474       0x000000013a47d       VERTEX_BUFFER
>           2    0x000000013a47d       0x000000013a47f       INDEX_BUFFER
>           1    -- hole --
>          87    0x000000013a480       0x000000013a4d7       SAMPLER_TEXTURE
>          87    0x000000013a4d7       0x000000013a52e       SAMPLER_TEXTURE
>         210    -- hole --
>          87    0x000000013a600       0x000000013a657       SAMPLER_TEXTURE
>          41    -- hole --
>        1367    0x000000013a680       0x000000013abd7       SAMPLER_TEXTURE
>         851    -- hole --
>          23    0x000000013af2a       0x000000013af41       SAMPLER_TEXTURE
>          16    -- hole --
>         114    0x000000013af51       0x000000013afc3       VERTEX_BUFFER
>          14    -- hole --
>           1    0x000000013afd1       0x000000013afd2       USER_SHADER
>           1    0x000000013afd2       0x000000013afd3       USER_SHADER
>           1    0x000000013afd3       0x000000013afd4       VERTEX_BUFFER
>           1    0x000000013afd4       0x000000013afd5       INDEX_BUFFER
>           1    0x000000013afd5       0x000000013afd6       VERTEX_BUFFER
>           1    0x000000013afd6       0x000000013afd7       INDEX_BUFFER
>          36    -- hole --
>           3    0x000000013affb       0x000000013affe       INDEX_BUFFER
>           2    -- hole --
>        1367    0x000000013b000       0x000000013b557       SAMPLER_TEXTURE
>          22    -- hole --
>           1    0x000000013b56d       0x000000013b56e       INDEX_BUFFER
>       22041    -- hole --
>           1    0x0000000140b87       0x0000000140b88       USER_SHADER
>           1    0x0000000140b88       0x0000000140b89       USER_SHADER
>           1    0x0000000140b89       0x0000000140b8a       USER_SHADER
>           1    0x0000000140b8a       0x0000000140b8b       USER_SHADER
>           1    0x0000000140b8b       0x0000000140b8c       USER_SHADER
>           1    0x0000000140b8c       0x0000000140b8d       USER_SHADER
>       25715    -- hole --
>          11    0x0000000147000       0x000000014700b       VERTEX_BUFFER
>           8    0x000000014700b       0x0000000147013       VERTEX_BUFFER
>         493    -- hole --
>          87    0x0000000147200       0x0000000147257       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x0000000147280       0x00000001472d7       SAMPLER_TEXTURE
>        1384    -- hole --
>           1    0x000000014783f       0x0000000147840       VERTEX_BUFFER
>          11    -- hole --
>           1    0x000000014784b       0x000000014784c       VERTEX_BUFFER
>           4    -- hole --
>          52    0x0000000147850       0x0000000147884       VERTEX_BUFFER
>           4    -- hole --
>          39    0x0000000147888       0x00000001478af       VERTEX_BUFFER
>           6    -- hole --
>           2    0x00000001478b5       0x00000001478b7       VERTEX_BUFFER
>         339    -- hole --
>          56    0x0000000147a0a       0x0000000147a42       VERTEX_BUFFER
>          56    0x0000000147a42       0x0000000147a7a       VERTEX_BUFFER
>         152    -- hole --
>          52    0x0000000147b12       0x0000000147b46       VERTEX_BUFFER
>        1772    -- hole --
>          11    0x0000000148232       0x000000014823d       VERTEX_BUFFER
>         282    -- hole --
>          44    0x0000000148357       0x0000000148383       VERTEX_BUFFER
>         363    -- hole --
>          57    0x00000001484ee       0x0000000148527       VERTEX_BUFFER
>         688    -- hole --
>         289    0x00000001487d7       0x00000001488f8       VERTEX_BUFFER
>         289    0x00000001488f8       0x0000000148a19       VERTEX_BUFFER
>         289    0x0000000148a19       0x0000000148b3a       VERTEX_BUFFER
>         289    0x0000000148b3a       0x0000000148c5b       VERTEX_BUFFER
>         289    0x0000000148c5b       0x0000000148d7c       VERTEX_BUFFER
>         289    0x0000000148d7c       0x0000000148e9d       VERTEX_BUFFER
>         289    0x0000000148e9d       0x0000000148fbe       VERTEX_BUFFER
>        1689    -- hole --
>         289    0x0000000149657       0x0000000149778       VERTEX_BUFFER
>        4285    -- hole --
>          53    0x000000014a835       0x000000014a86a       VERTEX_BUFFER
>         400    -- hole --
>         289    0x000000014a9fa       0x000000014ab1b       VERTEX_BUFFER
>        1148    -- hole --
>          58    0x000000014af97       0x000000014afd1       VERTEX_BUFFER
>        2153    -- hole --
>          51    0x000000014b83a       0x000000014b86d       VERTEX_BUFFER
>        1455    -- hole --
>          56    0x000000014be1c       0x000000014be54       VERTEX_BUFFER
>          76    -- hole --
>          70    0x000000014bea0       0x000000014bee6       VERTEX_BUFFER
>          19    0x000000014bee6       0x000000014bef9       VERTEX_BUFFER
>         127    -- hole --
>          46    0x000000014bf78       0x000000014bfa6       VERTEX_BUFFER
>        1100    -- hole --
>           2    0x000000014c3f2       0x000000014c3f4       VERTEX_BUFFER
>        1955    -- hole --
>          51    0x000000014cb97       0x000000014cbca       VERTEX_BUFFER
>        1677    -- hole --
>          89    0x000000014d257       0x000000014d2b0       SAMPLER_TEXTURE
>        1715    -- hole --
>         289    0x000000014d963       0x000000014da84       VERTEX_BUFFER
>          60    -- hole --
>          87    0x000000014dac0       0x000000014db17       SAMPLER_TEXTURE
>           9    -- hole --
>          50    0x000000014db20       0x000000014db52       VERTEX_BUFFER
>          46    -- hole --
>          87    0x000000014db80       0x000000014dbd7       SAMPLER_TEXTURE
>          84    -- hole --
>          13    0x000000014dc2b       0x000000014dc38       INDEX_BUFFER
>           8    -- hole --
>          87    0x000000014dc40       0x000000014dc97       SAMPLER_TEXTURE
>          14    -- hole --
>           6    0x000000014dca5       0x000000014dcab       INDEX_BUFFER
>         940    -- hole --
>         289    0x000000014e057       0x000000014e178       VERTEX_BUFFER
>           8    -- hole --
>          87    0x000000014e180       0x000000014e1d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000014e200       0x000000014e257       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000014e280       0x000000014e2d7       SAMPLER_TEXTURE
>         172    -- hole --
>          84    0x000000014e383       0x000000014e3d7       VERTEX_BUFFER
>          11    0x000000014e3d7       0x000000014e3e2       INDEX_BUFFER
>         259    -- hole --
>          45    0x000000014e4e5       0x000000014e512       SAMPLER_TEXTURE
>         115    -- hole --
>          67    0x000000014e585       0x000000014e5c8       VERTEX_BUFFER
>        1009    -- hole --
>          12    0x000000014e9b9       0x000000014e9c5       INDEX_BUFFER
>         316    -- hole --
>         101    0x000000014eb01       0x000000014eb66       VERTEX_BUFFER
>          50    -- hole --
>          87    0x000000014eb98       0x000000014ebef       SAMPLER_TEXTURE
>          64    -- hole --
>         173    0x000000014ec2f       0x000000014ecdc       SAMPLER_TEXTURE
>          89    0x000000014ecdc       0x000000014ed35       VERTEX_BUFFER
>          11    -- hole --
>          87    0x000000014ed40       0x000000014ed97       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000014edc0       0x000000014ee17       SAMPLER_TEXTURE
>       11207    -- hole --
>          42    0x00000001519de       0x0000000151a08       VERTEX_BUFFER
>        2315    -- hole --
>          29    0x0000000152313       0x0000000152330       VERTEX_BUFFER
>           5    -- hole --
>           9    0x0000000152335       0x000000015233e       VERTEX_BUFFER
>          89    -- hole --
>          41    0x0000000152397       0x00000001523c0       VERTEX_BUFFER
>         791    -- hole --
>          29    0x00000001526d7       0x00000001526f4       VERTEX_BUFFER
>          90    -- hole --
>           6    0x000000015274e       0x0000000152754       VERTEX_BUFFER
>         280    -- hole --
>         115    0x000000015286c       0x00000001528df       VERTEX_BUFFER
>        1485    -- hole --
>          14    0x0000000152eac       0x0000000152eba       VERTEX_BUFFER
>        1933    -- hole --
>          29    0x0000000153647       0x0000000153664       VERTEX_BUFFER
>        1932    -- hole --
>           2    0x0000000153df0       0x0000000153df2       VERTEX_BUFFER
>           2    0x0000000153df2       0x0000000153df4       VERTEX_BUFFER
>           4    -- hole --
>           2    0x0000000153df8       0x0000000153dfa       VERTEX_BUFFER
>          10    -- hole --
>           2    0x0000000153e04       0x0000000153e06       VERTEX_BUFFER
>           2    0x0000000153e06       0x0000000153e08       VERTEX_BUFFER
>         242    -- hole --
>          99    0x0000000153efa       0x0000000153f5d       VERTEX_BUFFER
>        8506    -- hole --
>          29    0x0000000156097       0x00000001560b4       VERTEX_BUFFER
>          99    -- hole --
>          29    0x0000000156117       0x0000000156134       VERTEX_BUFFER
>         371    -- hole --
>          16    0x00000001562a7       0x00000001562b7       VERTEX_BUFFER
>         646    -- hole --
>           2    0x000000015653d       0x000000015653f       VERTEX_BUFFER
>         756    -- hole --
>           2    0x0000000156833       0x0000000156835       VERTEX_BUFFER
>          10    0x0000000156835       0x000000015683f       VERTEX_BUFFER
>         506    -- hole --
>           3    0x0000000156a39       0x0000000156a3c       VERTEX_BUFFER
>         105    -- hole --
>           2    0x0000000156aa5       0x0000000156aa7       VERTEX_BUFFER
>         528    -- hole --
>           2    0x0000000156cb7       0x0000000156cb9       VERTEX_BUFFER
>          94    -- hole --
>          14    0x0000000156d17       0x0000000156d25       VERTEX_BUFFER
>         114    -- hole --
>         256    0x0000000156d97       0x0000000156e97       CONST_BUFFER, DESCRIPTORS, VERTEX_BUFFER
>         289    -- hole --
>           2    0x0000000156fb8       0x0000000156fba       VERTEX_BUFFER
>         114    -- hole --
>           1    0x000000015702c       0x000000015702d       VERTEX_BUFFER
>          16    -- hole --
>           1    0x000000015703d       0x000000015703e       VERTEX_BUFFER
>         729    -- hole --
>          56    0x0000000157317       0x000000015734f       VERTEX_BUFFER
>         532    -- hole --
>          97    0x0000000157563       0x00000001575c4       VERTEX_BUFFER
>         396    -- hole --
>          29    0x0000000157750       0x000000015776d       VERTEX_BUFFER
>         106    -- hole --
>          23    0x00000001577d7       0x00000001577ee       VERTEX_BUFFER
>         233    -- hole --
>         102    0x00000001578d7       0x000000015793d       VERTEX_BUFFER
>         400    -- hole --
>          29    0x0000000157acd       0x0000000157aea       VERTEX_BUFFER
>         109    -- hole --
>          27    0x0000000157b57       0x0000000157b72       VERTEX_BUFFER
>         105    -- hole --
>          14    0x0000000157bdb       0x0000000157be9       VERTEX_BUFFER
>          13    0x0000000157be9       0x0000000157bf6       VERTEX_BUFFER
>        1473    -- hole --
>         115    0x00000001581b7       0x000000015822a       VERTEX_BUFFER
>        4269    -- hole --
>          30    0x00000001592d7       0x00000001592f5       VERTEX_BUFFER
>         115    -- hole --
>           4    0x0000000159368       0x000000015936c       INDEX_BUFFER
>         574    -- hole --
>           4    0x00000001595aa       0x00000001595ae       VERTEX_BUFFER
>         120    -- hole --
>           2    0x0000000159626       0x0000000159628       VERTEX_BUFFER
>         232    -- hole --
>           4    0x0000000159710       0x0000000159714       VERTEX_BUFFER
>           1    0x0000000159714       0x0000000159715       VERTEX_BUFFER
>         646    -- hole --
>          63    0x000000015999b       0x00000001599da       VERTEX_BUFFER
>          39    0x00000001599da       0x0000000159a01       VERTEX_BUFFER
>        1347    -- hole --
>         101    0x0000000159f44       0x0000000159fa9       VERTEX_BUFFER
>         982    -- hole --
>          16    0x000000015a37f       0x000000015a38f       VERTEX_BUFFER
>        1135    -- hole --
>           2    0x000000015a7fe       0x000000015a800       VERTEX_BUFFER
>         279    -- hole --
>          18    0x000000015a917       0x000000015a929       VERTEX_BUFFER
>          23    -- hole --
>          87    0x000000015a940       0x000000015a997       SAMPLER_TEXTURE
>        1403    -- hole --
>           7    0x000000015af12       0x000000015af19       VERTEX_BUFFER
>         682    -- hole --
>          12    0x000000015b1c3       0x000000015b1cf       VERTEX_BUFFER
>         202    -- hole --
>           5    0x000000015b299       0x000000015b29e       VERTEX_BUFFER
>         225    -- hole --
>           8    0x000000015b37f       0x000000015b387       VERTEX_BUFFER
>           8    0x000000015b387       0x000000015b38f       VERTEX_BUFFER
>           8    0x000000015b38f       0x000000015b397       VERTEX_BUFFER
>           8    0x000000015b397       0x000000015b39f       VERTEX_BUFFER
>        2465    -- hole --
>          87    0x000000015bd40       0x000000015bd97       SAMPLER_TEXTURE
>         666    -- hole --
>          58    0x000000015c031       0x000000015c06b       VERTEX_BUFFER
>         466    -- hole --
>         115    0x000000015c23d       0x000000015c2b0       VERTEX_BUFFER
>         385    -- hole --
>         289    0x000000015c431       0x000000015c552       VERTEX_BUFFER
>         289    0x000000015c552       0x000000015c673       VERTEX_BUFFER
>         289    0x000000015c673       0x000000015c794       VERTEX_BUFFER
>          27    -- hole --
>          16    0x000000015c7af       0x000000015c7bf       VERTEX_BUFFER
>           1    -- hole --
>          87    0x000000015c7c0       0x000000015c817       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015c840       0x000000015c897       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015c8c0       0x000000015c917       SAMPLER_TEXTURE
>          27    -- hole --
>          14    0x000000015c932       0x000000015c940       VERTEX_BUFFER
>          87    0x000000015c940       0x000000015c997       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015c9c0       0x000000015ca17       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015ca40       0x000000015ca97       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015cac0       0x000000015cb17       SAMPLER_TEXTURE
>          27    -- hole --
>           8    0x000000015cb32       0x000000015cb3a       VERTEX_BUFFER
>           6    -- hole --
>          87    0x000000015cb40       0x000000015cb97       SAMPLER_TEXTURE
>          37    -- hole --
>           3    0x000000015cbbc       0x000000015cbbf       VERTEX_BUFFER
>           1    -- hole --
>          87    0x000000015cbc0       0x000000015cc17       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015cc40       0x000000015cc97       SAMPLER_TEXTURE
>         115    0x000000015cc97       0x000000015cd0a       VERTEX_BUFFER
>         118    -- hole --
>          87    0x000000015cd80       0x000000015cdd7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015ce00       0x000000015ce57       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015ce80       0x000000015ced7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015cf00       0x000000015cf57       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015cf80       0x000000015cfd7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d000       0x000000015d057       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d080       0x000000015d0d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d100       0x000000015d157       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d180       0x000000015d1d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d200       0x000000015d257       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d280       0x000000015d2d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d300       0x000000015d357       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d380       0x000000015d3d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d400       0x000000015d457       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d480       0x000000015d4d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d500       0x000000015d557       SAMPLER_TEXTURE
>          14    -- hole --
>           8    0x000000015d565       0x000000015d56d       VERTEX_BUFFER
>          19    -- hole --
>          87    0x000000015d580       0x000000015d5d7       SAMPLER_TEXTURE
>          14    0x000000015d5d7       0x000000015d5e5       VERTEX_BUFFER
>          27    -- hole --
>          87    0x000000015d600       0x000000015d657       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d680       0x000000015d6d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d700       0x000000015d757       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d780       0x000000015d7d7       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d800       0x000000015d857       SAMPLER_TEXTURE
>          41    -- hole --
>          87    0x000000015d880       0x000000015d8d7       SAMPLER_TEXTURE
>          14    -- hole --
>          14    0x000000015d8e5       0x000000015d8f3       VERTEX_BUFFER
>          13    -- hole --
>          87    0x000000015d900       0x000000015d957       SAMPLER_TEXTURE
>          35    -- hole --
>          31    0x000000015d97a       0x000000015d999       VERTEX_BUFFER
>          11    -- hole --
>           5    0x000000015d9a4       0x000000015d9a9       VERTEX_BUFFER
>          29    0x000000015d9a9       0x000000015d9c6       VERTEX_BUFFER
>           7    0x000000015d9c6       0x000000015d9cd       VERTEX_BUFFER
>          34    -- hole --
>          13    0x000000015d9ef       0x000000015d9fc       VERTEX_BUFFER
>           4    -- hole --
>          87    0x000000015da00       0x000000015da57       SAMPLER_TEXTURE
>           7    0x000000015da57       0x000000015da5e       VERTEX_BUFFER
>          11    -- hole --
>          21    0x000000015da69       0x000000015da7e       VERTEX_BUFFER
>           2    -- hole --
>          87    0x000000015da80       0x000000015dad7       SAMPLER_TEXTURE
>          29    0x000000015dad7       0x000000015daf4       VERTEX_BUFFER
>          12    -- hole --
>          87    0x000000015db00       0x000000015db57       SAMPLER_TEXTURE
>          29    0x000000015db57       0x000000015db74       VERTEX_BUFFER
>           7    0x000000015db74       0x000000015db7b       VERTEX_BUFFER
>           5    -- hole --
>          87    0x000000015db80       0x000000015dbd7       SAMPLER_TEXTURE
>          21    0x000000015dbd7       0x000000015dbec       VERTEX_BUFFER
>          20    -- hole --
>          87    0x000000015dc00       0x000000015dc57       SAMPLER_TEXTURE
>          17    -- hole --
>           5    0x000000015dc68       0x000000015dc6d       VERTEX_BUFFER
>           3    -- hole --
>           5    0x000000015dc70       0x000000015dc75       VERTEX_BUFFER
>           5    -- hole --
>           3    0x000000015dc7a       0x000000015dc7d       VERTEX_BUFFER
>           3    -- hole --
>          87    0x000000015dc80       0x000000015dcd7       SAMPLER_TEXTURE
>         115    -- hole --
>         115    0x000000015dd4a       0x000000015ddbd       VERTEX_BUFFER
>        1024    0x000000015ddbd       0x000000015e1bd       INDEX_BUFFER
>         256    0x000000015e1bd       0x000000015e2bd       CONST_BUFFER, DESCRIPTORS, VERTEX_BUFFER
>         115    -- hole --
>         115    0x000000015e330       0x000000015e3a3       VERTEX_BUFFER
>         115    -- hole --
>         114    0x000000015e416       0x000000015e488       VERTEX_BUFFER
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB begin ------------------
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000001
>[1;32mNOP[0m:
>        [31mTrace point ID: 1
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDIRECT_BUFFER_CIK[0m:
>        0x0023b000
>        0x00000001
>        0x00000090
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;32mDMA_DATA[0m:
>        [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                          SRC_SEL = DATA
>                          DSL_SEL = DST_ADDR
>                          ENGINE = ME
>        [1;33mSRC_ADDR_LO[0m <- 0
>        [1;33mSRC_ADDR_HI[0m <- 0
>        [1;33mDST_ADDR_LO[0m <- 0x094c0000
>        [1;33mDST_ADDR_HI[0m <- 1
>        [1;33mCOMMAND[0m <- BYTE_COUNT = 20480
>                   DISABLE_WR_CONFIRM = 0
>                   SRC_SWAP = NONE
>                   DST_SWAP = NONE
>                   SAS = MEMORY
>                   DAS = MEMORY
>                   SAIC = INCREMENT
>                   DAIC = INCREMENT
>                   RAW_WAIT = 1
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 0
>                         TC_ACTION_ENA = 0
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;32mDMA_DATA[0m:
>        [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                          SRC_SEL = DATA
>                          DSL_SEL = DST_ADDR
>                          ENGINE = ME
>        [1;33mSRC_ADDR_LO[0m <- 0
>        [1;33mSRC_ADDR_HI[0m <- 0
>        [1;33mDST_ADDR_LO[0m <- 0x0e600000
>        [1;33mDST_ADDR_HI[0m <- 1
>        [1;33mCOMMAND[0m <- BYTE_COUNT = 20480
>                   DISABLE_WR_CONFIRM = 0
>                   SRC_SWAP = NONE
>                   DST_SWAP = NONE
>                   SAS = MEMORY
>                   DAS = MEMORY
>                   SAIC = INCREMENT
>                   DAIC = INCREMENT
>                   RAW_WAIT = 1
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 0
>                         TC_ACTION_ENA = 0
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;32mDMA_DATA[0m:
>        [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                          SRC_SEL = DATA
>                          DSL_SEL = DST_ADDR
>                          ENGINE = ME
>        [1;33mSRC_ADDR_LO[0m <- 0
>        [1;33mSRC_ADDR_HI[0m <- 0
>        [1;33mDST_ADDR_LO[0m <- 0x13740000
>        [1;33mDST_ADDR_HI[0m <- 1
>        [1;33mCOMMAND[0m <- BYTE_COUNT = 20480
>                   DISABLE_WR_CONFIRM = 0
>                   SRC_SWAP = NONE
>                   DST_SWAP = NONE
>                   SAS = MEMORY
>                   DAS = MEMORY
>                   SAIC = INCREMENT
>                   DAIC = INCREMENT
>                   RAW_WAIT = 1
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 0
>                         TC_ACTION_ENA = 0
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;32mDMA_DATA[0m:
>        [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                          SRC_SEL = DATA
>                          DSL_SEL = DST_ADDR
>                          ENGINE = ME
>        [1;33mSRC_ADDR_LO[0m <- 0
>        [1;33mSRC_ADDR_HI[0m <- 0
>        [1;33mDST_ADDR_LO[0m <- 0x18880000
>        [1;33mDST_ADDR_HI[0m <- 1
>        [1;33mCOMMAND[0m <- BYTE_COUNT = 20480
>                   DISABLE_WR_CONFIRM = 0
>                   SRC_SWAP = NONE
>                   DST_SWAP = NONE
>                   SAS = MEMORY
>                   DAS = MEMORY
>                   SAIC = INCREMENT
>                   DAIC = INCREMENT
>                   RAW_WAIT = 1
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 0
>                         TC_ACTION_ENA = 0
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                              STREAMOUT_1_EN = 0
>                              STREAMOUT_2_EN = 0
>                              STREAMOUT_3_EN = 0
>                              RAST_STREAM = 0
>                              RAST_STREAM_MASK = 0
>                              USE_RAST_STREAM_MASK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x01043c00
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 255
>                           FMASK_TILE_MAX = 255
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 1
>                          COMPRESSION = 1
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 3
>                            NUM_FRAGMENTS = 3
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 1
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x01094c00
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 159
>        [1;33mCB_COLOR0_FMASK[0m <- 0x0108bc00
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR0_DCC_BASE[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_BASE[0m <- 0x01095000
>        [1;33mCB_COLOR1_PITCH[0m <- TILE_MAX = 255
>                           FMASK_TILE_MAX = 255
>        [1;33mCB_COLOR1_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR1_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 1
>                          COMPRESSION = 1
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR1_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 3
>                            NUM_FRAGMENTS = 3
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR1_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 1
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR1_CMASK[0m <- 0x010e6000
>        [1;33mCB_COLOR1_CMASK_SLICE[0m <- TILE_MAX = 159
>        [1;33mCB_COLOR1_FMASK[0m <- 0x010dd000
>        [1;33mCB_COLOR1_FMASK_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR1_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR1_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR1_DCC_BASE[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR2_BASE[0m <- 0x010e6400
>        [1;33mCB_COLOR2_PITCH[0m <- TILE_MAX = 255
>                           FMASK_TILE_MAX = 255
>        [1;33mCB_COLOR2_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR2_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR2_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 1
>                          COMPRESSION = 1
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR2_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 3
>                            NUM_FRAGMENTS = 3
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR2_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 1
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR2_CMASK[0m <- 0x01137400
>        [1;33mCB_COLOR2_CMASK_SLICE[0m <- TILE_MAX = 159
>        [1;33mCB_COLOR2_FMASK[0m <- 0x0112e400
>        [1;33mCB_COLOR2_FMASK_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR2_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR2_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR2_DCC_BASE[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR3_BASE[0m <- 0x01137800
>        [1;33mCB_COLOR3_PITCH[0m <- TILE_MAX = 255
>                           FMASK_TILE_MAX = 255
>        [1;33mCB_COLOR3_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR3_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR3_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 1
>                          COMPRESSION = 1
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR3_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 3
>                            NUM_FRAGMENTS = 3
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR3_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 1
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR3_CMASK[0m <- 0x01188800
>        [1;33mCB_COLOR3_CMASK_SLICE[0m <- TILE_MAX = 159
>        [1;33mCB_COLOR3_FMASK[0m <- 0x0117f800
>        [1;33mCB_COLOR3_FMASK_SLICE[0m <- TILE_MAX = 0x08fff
>        [1;33mCB_COLOR3_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR3_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR3_DCC_BASE[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR4_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR5_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR6_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR7_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x01137450
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P8_32X32_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 3
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_256B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 1
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_256B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 1
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x01188a00
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x011d0a00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x01188a00
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x011d0a00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 255
>                         HEIGHT_TILE_MAX = 143
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 0x08fff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CLEAR[0m <- 1.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1920
>                                   BR_Y = 1080
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 1
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_LINE_CNTL[0m <- EXPAND_LINE_WIDTH = 1
>                           LAST_PIXEL = 1
>                           PERPENDICULAR_ENDCAP_ENA = 0
>                           DX10_DIAMOND_TEST_ENA = 0
>        [1;33mPA_SC_AA_CONFIG[0m <- MSAA_NUM_SAMPLES = 3
>                           AA_MASK_CENTROID_DTMN = 0
>                           MAX_SAMPLE_DIST = 8
>                           MSAA_EXPOSED_SAMPLES = 3
>                           DETAIL_TO_EXPOSED_MODE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 3
>                   PS_ITER_SAMPLES = 0
>                   MASK_EXPORT_NUM_SAMPLES = 3
>                   ALPHA_TO_MASK_NUM_SAMPLES = 3
>                   HIGH_QUALITY_INTERSECTIONS = 1
>                   INCOHERENT_EQAA_READS = 0
>                   INTERPOLATE_COMP_Z = 0
>                   INTERPOLATE_SRC_Z = 0
>                   STATIC_ANCHOR_ASSOCIATIONS = 1
>                   ALPHA_TO_MASK_EQAA_DISABLE = 0
>                   OVERRASTERIZATION_AMOUNT = 0
>                   ENABLE_POSTZ_OVERRASTERIZATION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                             WALK_ALIGNMENT = 0
>                             WALK_ALIGN8_PRIM_FITS_ST = 0
>                             WALK_FENCE_ENABLE = 0
>                             WALK_FENCE_SIZE = 0
>                             SUPERTILE_WALK_ORDER_ENABLE = 0
>                             TILE_WALK_ORDER_ENABLE = 0
>                             TILE_COVER_DISABLE = 0
>                             TILE_COVER_NO_SCISSOR = 0
>                             ZMM_LINE_EXTENT = 0
>                             ZMM_LINE_OFFSET = 0
>                             ZMM_RECT_EXTENT = 0
>                             KILL_PIX_POST_HI_Z = 0
>                             KILL_PIX_POST_DETAIL_MASK = 0
>                             PS_ITER_SAMPLE = 0
>                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
>                             MULTI_GPU_SUPERTILE_ENABLE = 0
>                             GPU_ID_OVERRIDE_ENABLE = 0
>                             GPU_ID_OVERRIDE = 0
>                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                             FORCE_EOV_CNTDWN_ENABLE = 0
>                             FORCE_EOV_REZ_ENABLE = 0
>                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                             OUT_OF_ORDER_WATER_MARK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                   AA_MASK_X1Y0 = 0xffff
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                   AA_MASK_X1Y1 = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND_RED[0m <- 0
>        [1;33mCB_BLEND_GREEN[0m <- 0
>        [1;33mCB_BLEND_BLUE[0m <- 0
>        [1;33mCB_BLEND_ALPHA[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_UCP_0_X[0m <- 0
>        [1;33mPA_CL_UCP_0_Y[0m <- 0
>        [1;33mPA_CL_UCP_0_Z[0m <- 0
>        [1;33mPA_CL_UCP_0_W[0m <- 0
>        [1;33mPA_CL_UCP_1_X[0m <- 0
>        [1;33mPA_CL_UCP_1_Y[0m <- 0
>        [1;33mPA_CL_UCP_1_Z[0m <- 0
>        [1;33mPA_CL_UCP_1_W[0m <- 0
>        [1;33mPA_CL_UCP_2_X[0m <- 0
>        [1;33mPA_CL_UCP_2_Y[0m <- 0
>        [1;33mPA_CL_UCP_2_Z[0m <- 0
>        [1;33mPA_CL_UCP_2_W[0m <- 0
>        [1;33mPA_CL_UCP_3_X[0m <- 0
>        [1;33mPA_CL_UCP_3_Y[0m <- 0
>        [1;33mPA_CL_UCP_3_Z[0m <- 0
>        [1;33mPA_CL_UCP_3_W[0m <- 0
>        [1;33mPA_CL_UCP_4_X[0m <- 0
>        [1;33mPA_CL_UCP_4_Y[0m <- 0
>        [1;33mPA_CL_UCP_4_Z[0m <- 0
>        [1;33mPA_CL_UCP_4_W[0m <- 0
>        [1;33mPA_CL_UCP_5_X[0m <- 0
>        [1;33mPA_CL_UCP_5_Y[0m <- 0
>        [1;33mPA_CL_UCP_5_Z[0m <- 0
>        [1;33mPA_CL_UCP_5_W[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x56e82300
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e82100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 0x017d4700
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0x017d4c00
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x017d5000
>        [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e82400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e82600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e81900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 0x017d5a00
>        [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 0x017d5800
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_6[0m <- 0x017d5b00
>        [1;33mSPI_SHADER_USER_DATA_GS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_4[0m <- 0x017d6000
>        [1;33mSPI_SHADER_USER_DATA_GS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x017d6400
>        [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0x017d6200
>        [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_6[0m <- 0x017d6500
>        [1;33mSPI_SHADER_USER_DATA_HS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_4[0m <- 0x017d6a00
>        [1;33mSPI_SHADER_USER_DATA_HS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e82b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 1920
>                                    BR_Y = 1080
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 1
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_ALWAYS
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_FRONT_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_FRONT_OFFSET[0m <- 80.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_OFFSET[0m <- 80.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                HS_EN = 0
>                                ES_EN = ES_STAGE_OFF
>                                GS_EN = 0
>                                VS_EN = VS_STAGE_REAL
>                                DYNAMIC_HS = 0
>                                DISPATCH_DRAW_EN = 0
>                                DIS_DEALLOC_ACCUM_0 = 0
>                                DIS_DEALLOC_ACCUM_1 = 0
>                                VS_WAVE_ID_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01002240
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x011e2a00
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 1024
>                            WAVESIZE = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 0
>                              MAX_PRIMGRP_IN_WAVE = 2
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_OUT_PRIM_TYPE[0m <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
>                                OUTPRIM_TYPE_1 = 0
>                                OUTPRIM_TYPE_2 = 0
>                                OUTPRIM_TYPE_3 = 0
>                                UNIQUE_TYPE_PER_STREAM = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000002
>[1;32mNOP[0m:
>        [31mTrace point ID: 2
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 1
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x56e83100
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e82f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e83200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e83400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e83900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e83b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 960.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 960.0f
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 540.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 540.0f
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 1
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 1
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_LEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x011888f0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01188900
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 0
>                              MAX_PRIMGRP_IN_WAVE = 2
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1962
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000003
>[1;32mNOP[0m:
>        [31mTrace point ID: 3
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e83f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e84100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e84300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 330
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000004
>[1;32mNOP[0m:
>        [31mTrace point ID: 4
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e84700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e84900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e84b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 42
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000005
>[1;32mNOP[0m:
>        [31mTrace point ID: 5
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e84f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e85100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e85300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e85800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e85a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000006
>[1;32mNOP[0m:
>        [31mTrace point ID: 6
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e85e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e86000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e86200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 444
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000007
>[1;32mNOP[0m:
>        [31mTrace point ID: 7
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e86600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e86800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e86a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 60
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000008
>[1;32mNOP[0m:
>        [31mTrace point ID: 8
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e86e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e87000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e87200
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e87700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e87900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3342
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000009
>[1;32mNOP[0m:
>        [31mTrace point ID: 9
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e87d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e87f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e88100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 156
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000000a
>[1;32mNOP[0m:
>        [31mTrace point ID: 10
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e88500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e88700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e88900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e88e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e89000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19344
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000000b
>[1;32mNOP[0m:
>        [31mTrace point ID: 11
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e89400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e89600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e89800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2820
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000000c
>[1;32mNOP[0m:
>        [31mTrace point ID: 12
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e89c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e89e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8a000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1182
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000000d
>[1;32mNOP[0m:
>        [31mTrace point ID: 13
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8a400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8a600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e8a800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e8ad00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8af00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 14418
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000000e
>[1;32mNOP[0m:
>        [31mTrace point ID: 14
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8b300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8b500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8b700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2100
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000000f
>[1;32mNOP[0m:
>        [31mTrace point ID: 15
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8bb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8bd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8bf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 7140
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000010
>[1;32mNOP[0m:
>        [31mTrace point ID: 16
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8c300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8c500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8c700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5202
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000011
>[1;32mNOP[0m:
>        [31mTrace point ID: 17
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8cb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8cd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8cf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 30
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000012
>[1;32mNOP[0m:
>        [31mTrace point ID: 18
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8d300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8d500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8d700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1686
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000013
>[1;32mNOP[0m:
>        [31mTrace point ID: 19
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8db00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8dd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8df00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 36
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000014
>[1;32mNOP[0m:
>        [31mTrace point ID: 20
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8e300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8e500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e8e700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e8ec00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8ee00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19350
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000015
>[1;32mNOP[0m:
>        [31mTrace point ID: 21
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8f200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8f400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8f600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2832
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000016
>[1;32mNOP[0m:
>        [31mTrace point ID: 22
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e8fa00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e8fc00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e8fe00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12072
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000017
>[1;32mNOP[0m:
>        [31mTrace point ID: 23
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e90200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e90400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e90600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 10662
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000018
>[1;32mNOP[0m:
>        [31mTrace point ID: 24
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e90a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e90c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e90e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 162
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000019
>[1;32mNOP[0m:
>        [31mTrace point ID: 25
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e91200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e91400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e91600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8382
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000001a
>[1;32mNOP[0m:
>        [31mTrace point ID: 26
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e91a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e91c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e91e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1242
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000001b
>[1;32mNOP[0m:
>        [31mTrace point ID: 27
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e92200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e92400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e92600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e92b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e92d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19332
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000001c
>[1;32mNOP[0m:
>        [31mTrace point ID: 28
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e93100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e93300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e93500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2832
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000001d
>[1;32mNOP[0m:
>        [31mTrace point ID: 29
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e93900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e93b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e93d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12078
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000001e
>[1;32mNOP[0m:
>        [31mTrace point ID: 30
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e94100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e94300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e94500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 10662
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000001f
>[1;32mNOP[0m:
>        [31mTrace point ID: 31
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e94900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e94b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e94d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 180
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000020
>[1;32mNOP[0m:
>        [31mTrace point ID: 32
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e95100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e95300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e95500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8352
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000021
>[1;32mNOP[0m:
>        [31mTrace point ID: 33
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e95900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e95b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e95d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1230
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000022
>[1;32mNOP[0m:
>        [31mTrace point ID: 34
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x56e96100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x56e96300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x56e96500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x56e96a00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x56e96c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5058
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000023
>[1;32mNOP[0m:
>        [31mTrace point ID: 35
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1bd000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1bd200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1bd400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 630
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000024
>[1;32mNOP[0m:
>        [31mTrace point ID: 36
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1bd800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1bda00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1bdc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4464
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000025
>[1;32mNOP[0m:
>        [31mTrace point ID: 37
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1be000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1be200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1be400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4710
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000026
>[1;32mNOP[0m:
>        [31mTrace point ID: 38
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1be800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1bea00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1bec00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000027
>[1;32mNOP[0m:
>        [31mTrace point ID: 39
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1bf000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1bf200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1bf400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6222
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000028
>[1;32mNOP[0m:
>        [31mTrace point ID: 40
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1bf800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1bfa00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1bfc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 912
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000029
>[1;32mNOP[0m:
>        [31mTrace point ID: 41
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c0000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c0200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1c0400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1c0900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c0b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1236
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000002a
>[1;32mNOP[0m:
>        [31mTrace point ID: 42
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c0f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c1100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c1300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 84
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000002b
>[1;32mNOP[0m:
>        [31mTrace point ID: 43
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c1700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c1900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1c1b00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1c2000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c2200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4848
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000002c
>[1;32mNOP[0m:
>        [31mTrace point ID: 44
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c2600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c2800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c2a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 360
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000002d
>[1;32mNOP[0m:
>        [31mTrace point ID: 45
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c2e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c3000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c3200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000002e
>[1;32mNOP[0m:
>        [31mTrace point ID: 46
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c3600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c3800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1c3a00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1c3f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c4100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5046
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000002f
>[1;32mNOP[0m:
>        [31mTrace point ID: 47
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c4500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c4700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c4900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 738
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000030
>[1;32mNOP[0m:
>        [31mTrace point ID: 48
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c4d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c4f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c5100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 180
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000031
>[1;32mNOP[0m:
>        [31mTrace point ID: 49
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c5500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c5700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1c5900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1c5e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c6000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2136
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000032
>[1;32mNOP[0m:
>        [31mTrace point ID: 50
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c6400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c6600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c6800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1284
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000033
>[1;32mNOP[0m:
>        [31mTrace point ID: 51
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c6c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c6e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c7000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000034
>[1;32mNOP[0m:
>        [31mTrace point ID: 52
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c7400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c7600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c7800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 942
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000035
>[1;32mNOP[0m:
>        [31mTrace point ID: 53
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c7c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c7e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c8000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1140
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000036
>[1;32mNOP[0m:
>        [31mTrace point ID: 54
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c8400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c8600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c8800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1074
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000037
>[1;32mNOP[0m:
>        [31mTrace point ID: 55
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c8c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c8e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c9000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 648
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000038
>[1;32mNOP[0m:
>        [31mTrace point ID: 56
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c9400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c9600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1c9800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000039
>[1;32mNOP[0m:
>        [31mTrace point ID: 57
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1c9c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1c9e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ca000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 162
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000003a
>[1;32mNOP[0m:
>        [31mTrace point ID: 58
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ca400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ca600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1ca800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1cad00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1caf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2124
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000003b
>[1;32mNOP[0m:
>        [31mTrace point ID: 59
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1cb300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1cb500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cb700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1290
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000003c
>[1;32mNOP[0m:
>        [31mTrace point ID: 60
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1cbb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1cbd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cbf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1518
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000003d
>[1;32mNOP[0m:
>        [31mTrace point ID: 61
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1cc300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1cc500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cc700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 954
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000003e
>[1;32mNOP[0m:
>        [31mTrace point ID: 62
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ccb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ccd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ccf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1140
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000003f
>[1;32mNOP[0m:
>        [31mTrace point ID: 63
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1cd300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1cd500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cd700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1062
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000040
>[1;32mNOP[0m:
>        [31mTrace point ID: 64
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1cdb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1cdd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cdf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 648
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000041
>[1;32mNOP[0m:
>        [31mTrace point ID: 65
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ce300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ce500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ce700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000042
>[1;32mNOP[0m:
>        [31mTrace point ID: 66
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ceb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ced00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cef00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 162
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000043
>[1;32mNOP[0m:
>        [31mTrace point ID: 67
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1cf300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1cf500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1cf700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1cfc00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1cfe00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8454
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000044
>[1;32mNOP[0m:
>        [31mTrace point ID: 68
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d0200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d0400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d0600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5202
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000045
>[1;32mNOP[0m:
>        [31mTrace point ID: 69
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d0a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d0c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d0e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6012
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000046
>[1;32mNOP[0m:
>        [31mTrace point ID: 70
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d1200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d1400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d1600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3042
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000047
>[1;32mNOP[0m:
>        [31mTrace point ID: 71
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d1a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d1c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d1e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2346
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000048
>[1;32mNOP[0m:
>        [31mTrace point ID: 72
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d2200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d2400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d2600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1926
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000049
>[1;32mNOP[0m:
>        [31mTrace point ID: 73
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d2a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d2c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d2e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1044
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000004a
>[1;32mNOP[0m:
>        [31mTrace point ID: 74
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d3200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d3400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d3600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000004b
>[1;32mNOP[0m:
>        [31mTrace point ID: 75
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d3a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d3c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d3e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5556
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000004c
>[1;32mNOP[0m:
>        [31mTrace point ID: 76
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d4200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d4400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d4600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3438
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000004d
>[1;32mNOP[0m:
>        [31mTrace point ID: 77
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d4a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d4c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d4e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3978
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000004e
>[1;32mNOP[0m:
>        [31mTrace point ID: 78
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d5200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d5400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d5600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1920
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000004f
>[1;32mNOP[0m:
>        [31mTrace point ID: 79
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d5a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d5c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d5e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1530
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000050
>[1;32mNOP[0m:
>        [31mTrace point ID: 80
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d6200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d6400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d6600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1242
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000051
>[1;32mNOP[0m:
>        [31mTrace point ID: 81
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d6a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d6c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d6e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 690
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000052
>[1;32mNOP[0m:
>        [31mTrace point ID: 82
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d7200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d7400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1d7600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1d7b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d7d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 7740
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000053
>[1;32mNOP[0m:
>        [31mTrace point ID: 83
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d8100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d8300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d8500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12774
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000054
>[1;32mNOP[0m:
>        [31mTrace point ID: 84
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d8900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d8b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d8d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3066
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000055
>[1;32mNOP[0m:
>        [31mTrace point ID: 85
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d9100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d9300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d9500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8730
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000056
>[1;32mNOP[0m:
>        [31mTrace point ID: 86
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1d9900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1d9b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1d9d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 11406
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000057
>[1;32mNOP[0m:
>        [31mTrace point ID: 87
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1da100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1da300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1da500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5172
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000058
>[1;32mNOP[0m:
>        [31mTrace point ID: 88
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1da900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1dab00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1dad00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 390
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000059
>[1;32mNOP[0m:
>        [31mTrace point ID: 89
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1db100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1db300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1db500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 294
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000005a
>[1;32mNOP[0m:
>        [31mTrace point ID: 90
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1db900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1dbb00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1dbd00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1dc200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1dc400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 942
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000005b
>[1;32mNOP[0m:
>        [31mTrace point ID: 91
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1dc800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1dca00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1dcc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 246
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000005c
>[1;32mNOP[0m:
>        [31mTrace point ID: 92
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1dd000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1dd200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1dd400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 444
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000005d
>[1;32mNOP[0m:
>        [31mTrace point ID: 93
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1dd800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1dda00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ddc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 456
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000005e
>[1;32mNOP[0m:
>        [31mTrace point ID: 94
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1de000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1de200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1de400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 336
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000005f
>[1;32mNOP[0m:
>        [31mTrace point ID: 95
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1de800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1dea00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1dec00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000060
>[1;32mNOP[0m:
>        [31mTrace point ID: 96
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1df500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1df700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1df900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1dfe00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e0000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 1
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 1
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033b10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033b20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 183
>        [1;33mVGT_DMA_BASE[0m <- 0x5936be28
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 183
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000061
>[1;32mNOP[0m:
>        [31mTrace point ID: 97
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e0900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e0b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e0d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 312
>        [1;33mVGT_DMA_BASE[0m <- 0x4e3e1776
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 312
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000062
>[1;32mNOP[0m:
>        [31mTrace point ID: 98
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e1600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e1800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e1a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 456
>        [1;33mVGT_DMA_BASE[0m <- 0x4dc37180
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 456
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000063
>[1;32mNOP[0m:
>        [31mTrace point ID: 99
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e2300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e2500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1e2700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1e2c00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e2e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1116
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaa6d6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 861
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000064
>[1;32mNOP[0m:
>        [31mTrace point ID: 100
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e3700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e3900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e3b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 255
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaad90
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 255
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000065
>[1;32mNOP[0m:
>        [31mTrace point ID: 101
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e4400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e4600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1e4800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1e4d00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e4f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033a60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033a70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 255
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaad90
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 255
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000066
>[1;32mNOP[0m:
>        [31mTrace point ID: 102
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e5800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e5a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1e5c00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1e6100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e6300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033b10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033b20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1845
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c391a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1431
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000067
>[1;32mNOP[0m:
>        [31mTrace point ID: 103
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e6c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e6e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e7000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 414
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c4448
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 414
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000068
>[1;32mNOP[0m:
>        [31mTrace point ID: 104
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e7900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e7b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1e7d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1e8200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e8400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033a60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033a70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 414
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c4448
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 414
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000069
>[1;32mNOP[0m:
>        [31mTrace point ID: 105
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1e8d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1e8f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1e9100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1e9600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1e9800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033b10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033b20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 90
>        [1;33mVGT_DMA_BASE[0m <- 0x36b32ec6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 90
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000006a
>[1;32mNOP[0m:
>        [31mTrace point ID: 106
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ea100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ea300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1ea500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1eaa00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1eac00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033a60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033a70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 90
>        [1;33mVGT_DMA_BASE[0m <- 0x36b32ec6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 90
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000006b
>[1;32mNOP[0m:
>        [31mTrace point ID: 107
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1eb500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1eb700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1eb900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1ebe00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ec000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033b10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033b20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 228
>        [1;33mVGT_DMA_BASE[0m <- 0x3623f7ba
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 228
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000006c
>[1;32mNOP[0m:
>        [31mTrace point ID: 108
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ec900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ecb00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1ecd00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1ed200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ed400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033a60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033a70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 228
>        [1;33mVGT_DMA_BASE[0m <- 0x3623f7ba
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 228
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000006d
>[1;32mNOP[0m:
>        [31mTrace point ID: 109
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1edd00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1edf00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1ee100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1ee600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1ee800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033b10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033b20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 336
>        [1;33mVGT_DMA_BASE[0m <- 0x2ceae2dc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 336
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000006e
>[1;32mNOP[0m:
>        [31mTrace point ID: 110
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ef100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ef300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1ef500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1efa00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1efc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033a60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033a70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 336
>        [1;33mVGT_DMA_BASE[0m <- 0x2ceae2dc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 336
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000006f
>[1;32mNOP[0m:
>        [31mTrace point ID: 111
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f0500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f0700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1f0900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1f0e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f1000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033b10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033b20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 294
>        [1;33mVGT_DMA_BASE[0m <- 0x27f6d9fc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 294
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000070
>[1;32mNOP[0m:
>        [31mTrace point ID: 112
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f1900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f1b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1f1d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1f2200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f2400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01033a60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01033a70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 294
>        [1;33mVGT_DMA_BASE[0m <- 0x27f6d9fc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 294
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000071
>[1;32mNOP[0m:
>        [31mTrace point ID: 113
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 1
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f2d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f2f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1f3100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1f3600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f3800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136db70
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0136d960
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 2289
>        [1;33mVGT_DMA_BASE[0m <- 0x5936adb4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 156
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000072
>[1;32mNOP[0m:
>        [31mTrace point ID: 114
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f4100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f4300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f4500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7197
>        [1;33mVGT_DMA_BASE[0m <- 0x4e3de1ac
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1926
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000073
>[1;32mNOP[0m:
>        [31mTrace point ID: 115
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f4e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f5000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f5200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7263
>        [1;33mVGT_DMA_BASE[0m <- 0x4dc33c52
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 900
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000074
>[1;32mNOP[0m:
>        [31mTrace point ID: 116
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f5b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f5d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1f5f00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1f6400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f6600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5205
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca86e4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 582
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000075
>[1;32mNOP[0m:
>        [31mTrace point ID: 117
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f6f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f7100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f7300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4623
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca8b70
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 288
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000076
>[1;32mNOP[0m:
>        [31mTrace point ID: 118
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f7d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f7f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1f8100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1f8600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f8800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136b330
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01363300
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4623
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca8b70
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 288
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000077
>[1;32mNOP[0m:
>        [31mTrace point ID: 119
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f9200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1f9400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1f9600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 13575
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bdd76
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3762
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000078
>[1;32mNOP[0m:
>        [31mTrace point ID: 120
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1f9f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1fa100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1fa300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1fa800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1faa00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136db70
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0136d960
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9813
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bfada
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1890
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000079
>[1;32mNOP[0m:
>        [31mTrace point ID: 121
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1fb300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1fb500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1fb700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7923
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c099e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 948
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000007a
>[1;32mNOP[0m:
>        [31mTrace point ID: 122
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1fc100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1fc300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1fc500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1fca00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1fcc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136b330
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01363300
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 8
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7923
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c099e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 948
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000007b
>[1;32mNOP[0m:
>        [31mTrace point ID: 123
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1fd500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1fd700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1fd900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e1fde00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1fe000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136db70
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0136d960
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 12
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1599
>        [1;33mVGT_DMA_BASE[0m <- 0x36b322fc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 150
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000007c
>[1;32mNOP[0m:
>        [31mTrace point ID: 124
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1fe900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1feb00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e1fed00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4488
>        [1;33mVGT_DMA_BASE[0m <- 0x3623d672
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 450
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000007d
>[1;32mNOP[0m:
>        [31mTrace point ID: 125
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e1ff700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e1ff900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e1ffb00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e200000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e200200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136b330
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01363300
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4488
>        [1;33mVGT_DMA_BASE[0m <- 0x3623d672
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 450
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000007e
>[1;32mNOP[0m:
>        [31mTrace point ID: 126
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e200c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e200e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e201000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9015
>        [1;33mVGT_DMA_BASE[0m <- 0x2cea9f0e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1482
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000007f
>[1;32mNOP[0m:
>        [31mTrace point ID: 127
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e201900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e201b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e201d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e202200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e202400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136db70
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0136d960
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 10
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7533
>        [1;33mVGT_DMA_BASE[0m <- 0x2ceaaaa2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 750
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000080
>[1;32mNOP[0m:
>        [31mTrace point ID: 128
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e202e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e203000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e203200
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e203700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e203900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136b330
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01363300
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7533
>        [1;33mVGT_DMA_BASE[0m <- 0x2ceaaaa2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 750
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000081
>[1;32mNOP[0m:
>        [31mTrace point ID: 129
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e204200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e204400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e204600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e204b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e204d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136db70
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0136d960
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5283
>        [1;33mVGT_DMA_BASE[0m <- 0x27f6b302
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 288
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000082
>[1;32mNOP[0m:
>        [31mTrace point ID: 130
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e205700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e205900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e205b00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e206000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e206200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136b330
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01363300
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5283
>        [1;33mVGT_DMA_BASE[0m <- 0x27f6b302
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 288
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000083
>[1;32mNOP[0m:
>        [31mTrace point ID: 131
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e206b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e206d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e206f00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e207400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e207600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0136db70
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0136d960
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 8
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 102
>        [1;33mVGT_DMA_BASE[0m <- 0x3b56d0a8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 102
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000084
>[1;32mNOP[0m:
>        [31mTrace point ID: 132
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e207f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e208100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e208300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 102
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd4078
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 102
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000085
>[1;32mNOP[0m:
>        [31mTrace point ID: 133
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e208c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e208e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e209000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 60
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd6000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000086
>[1;32mNOP[0m:
>        [31mTrace point ID: 134
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e209900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e209b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e209d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e20a200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e20a400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000087
>[1;32mNOP[0m:
>        [31mTrace point ID: 135
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e20ad00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e20af00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000088
>[1;32mNOP[0m:
>        [31mTrace point ID: 136
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e20b900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e20bb00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e20bd00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e20c200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e20c400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 18
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000089
>[1;32mNOP[0m:
>        [31mTrace point ID: 137
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e20cd00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e20cf00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e20d100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e20d600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e20d800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a2e90
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a2ea0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 8
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x3b56d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 84
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000008a
>[1;32mNOP[0m:
>        [31mTrace point ID: 138
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e20e100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e20e300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e20e500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 162
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd4000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 60
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000008b
>[1;32mNOP[0m:
>        [31mTrace point ID: 139
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e20ee00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e20f000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e20f200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 48
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd6018
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000008c
>[1;32mNOP[0m:
>        [31mTrace point ID: 140
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e20fb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e20fd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e20ff00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e210400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e210600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x362be000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 72
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000008d
>[1;32mNOP[0m:
>        [31mTrace point ID: 141
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 1
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e210f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e211100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e211300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e211800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e211a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a4720
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a4730
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x362be000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 72
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000008e
>[1;32mNOP[0m:
>        [31mTrace point ID: 142
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 1
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e212300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e212500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e212700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e212c00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e212e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a2e90
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a2ea0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x362be000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 72
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000008f
>[1;32mNOP[0m:
>        [31mTrace point ID: 143
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e213700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e213900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e213b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 8
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x362be000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 72
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000090
>[1;32mNOP[0m:
>        [31mTrace point ID: 144
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 1
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e214400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e214600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e214800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e214d00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e214f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 1
>                            POS_Y_FLOAT_ENA = 1
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 1
>                             POS_Y_FLOAT_ENA = 1
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a4720
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a4730
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x362be000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 72
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000091
>[1;32mNOP[0m:
>        [31mTrace point ID: 145
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 1
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e215800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e215a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e215c00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e216100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e216300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a3fd0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a3fe0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 16
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3684
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d060
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3684
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000092
>[1;32mNOP[0m:
>        [31mTrace point ID: 146
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e216d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e216f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e217100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e217300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a3ff0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a37b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3684
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d060
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3684
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000093
>[1;32mNOP[0m:
>        [31mTrace point ID: 147
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e217c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e217e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e218000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e218500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e218700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a3fd0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a3fe0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4980
>        [1;33mVGT_DMA_BASE[0m <- 0x3affb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4860
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000094
>[1;32mNOP[0m:
>        [31mTrace point ID: 148
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e219000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e219200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e219400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e219900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e219b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000095
>[1;32mNOP[0m:
>        [31mTrace point ID: 149
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21a400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21a600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000096
>[1;32mNOP[0m:
>        [31mTrace point ID: 150
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21b000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21b200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000097
>[1;32mNOP[0m:
>        [31mTrace point ID: 151
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21bc00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21be00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 31
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000098
>[1;32mNOP[0m:
>        [31mTrace point ID: 152
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21c900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21cb00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e21cd00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e21cf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013a3ff0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a37b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000099
>[1;32mNOP[0m:
>        [31mTrace point ID: 153
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21d900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21db00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000009a
>[1;32mNOP[0m:
>        [31mTrace point ID: 154
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21e000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21e200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e21e400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e21e900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e21eb00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 1
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0127d360
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0127d370
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 11016
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000009b
>[1;32mNOP[0m:
>        [31mTrace point ID: 155
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21ef00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21f100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e21f300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 11016
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000009c
>[1;32mNOP[0m:
>        [31mTrace point ID: 156
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21f700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e21f900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e21fb00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 11016
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000009d
>[1;32mNOP[0m:
>        [31mTrace point ID: 157
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e21ff00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e220100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e220300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 11016
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000009e
>[1;32mNOP[0m:
>        [31mTrace point ID: 158
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e220700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e220900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e220b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 10506
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000009f
>[1;32mNOP[0m:
>        [31mTrace point ID: 159
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e220f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e221100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e221300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3450
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a0
>[1;32mNOP[0m:
>        [31mTrace point ID: 160
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e221700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e221900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e221b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 21840
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a1
>[1;32mNOP[0m:
>        [31mTrace point ID: 161
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e221f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e222100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e222300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 21936
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a2
>[1;32mNOP[0m:
>        [31mTrace point ID: 162
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e222700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e222900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e222b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 21936
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a3
>[1;32mNOP[0m:
>        [31mTrace point ID: 163
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e222f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e223100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e223300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 21936
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a4
>[1;32mNOP[0m:
>        [31mTrace point ID: 164
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e223700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e223900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e223b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 14814
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a5
>[1;32mNOP[0m:
>        [31mTrace point ID: 165
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e223f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e224100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e224300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12534
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a6
>[1;32mNOP[0m:
>        [31mTrace point ID: 166
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e224700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e224900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e224b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 9030
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a7
>[1;32mNOP[0m:
>        [31mTrace point ID: 167
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e224f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e225100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e225300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8532
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a8
>[1;32mNOP[0m:
>        [31mTrace point ID: 168
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e225700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e225900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e225b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5520
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000a9
>[1;32mNOP[0m:
>        [31mTrace point ID: 169
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e225f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e226100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e226300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5520
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000aa
>[1;32mNOP[0m:
>        [31mTrace point ID: 170
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e226700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e226900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e226b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5520
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ab
>[1;32mNOP[0m:
>        [31mTrace point ID: 171
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e226f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e227100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e227300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5520
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ac
>[1;32mNOP[0m:
>        [31mTrace point ID: 172
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e227700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e227900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e227b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5520
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ad
>[1;32mNOP[0m:
>        [31mTrace point ID: 173
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e227f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e228100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e228300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5442
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ae
>[1;32mNOP[0m:
>        [31mTrace point ID: 174
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e228700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e228900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e228b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 120
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000af
>[1;32mNOP[0m:
>        [31mTrace point ID: 175
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e228f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e229100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e229300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e229800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e229a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0127d3c0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0127d3d0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b0
>[1;32mNOP[0m:
>        [31mTrace point ID: 176
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e229e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22a000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22a200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b1
>[1;32mNOP[0m:
>        [31mTrace point ID: 177
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22a600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22a800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22aa00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b2
>[1;32mNOP[0m:
>        [31mTrace point ID: 178
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22ae00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22b000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22b200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b3
>[1;32mNOP[0m:
>        [31mTrace point ID: 179
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22b600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22b800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22ba00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b4
>[1;32mNOP[0m:
>        [31mTrace point ID: 180
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22be00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22c000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22c200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b5
>[1;32mNOP[0m:
>        [31mTrace point ID: 181
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22c600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22c800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22ca00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b6
>[1;32mNOP[0m:
>        [31mTrace point ID: 182
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22ce00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22d000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e22d200
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e22d700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22d900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 1
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 1
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012b7f20
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013a37c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 11
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 1
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000ab179
>        [1;33mVGT_DMA_BASE[0m <- 0x5e066d0e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 7188
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b7
>[1;32mNOP[0m:
>        [31mTrace point ID: 183
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000a9565
>        [1;33mVGT_DMA_BASE[0m <- 0x5e06a536
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 768
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b8
>[1;32mNOP[0m:
>        [31mTrace point ID: 184
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 19652
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000a9265
>        [1;33mVGT_DMA_BASE[0m <- 0x5e06ab36
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 26412
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000b9
>[1;32mNOP[0m:
>        [31mTrace point ID: 185
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000cd76
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000a2b39
>        [1;33mVGT_DMA_BASE[0m <- 0x5e07798e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 10968
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ba
>[1;32mNOP[0m:
>        [31mTrace point ID: 186
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009988
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000a0061
>        [1;33mVGT_DMA_BASE[0m <- 0x5e07cf3e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 28488
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000bb
>[1;32mNOP[0m:
>        [31mTrace point ID: 187
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22dd00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22df00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e22e100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e22e600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22e800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00099119
>        [1;33mVGT_DMA_BASE[0m <- 0x5e08adce
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4008
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000bc
>[1;32mNOP[0m:
>        [31mTrace point ID: 188
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22ec00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22ee00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e22f000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e22f500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e22f700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00098171
>        [1;33mVGT_DMA_BASE[0m <- 0x5e08cd1e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8346
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000bd
>[1;32mNOP[0m:
>        [31mTrace point ID: 189
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000960d7
>        [1;33mVGT_DMA_BASE[0m <- 0x5e090e52
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8700
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000be
>[1;32mNOP[0m:
>        [31mTrace point ID: 190
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00093edb
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09524a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2292
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000bf
>[1;32mNOP[0m:
>        [31mTrace point ID: 191
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e22fb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e22fd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e22ff00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e230400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e230600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000935e7
>        [1;33mVGT_DMA_BASE[0m <- 0x5e096432
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1620
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c0
>[1;32mNOP[0m:
>        [31mTrace point ID: 192
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00092f93
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0970da
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c1
>[1;32mNOP[0m:
>        [31mTrace point ID: 193
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 19652
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00092f63
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09713a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 408
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c2
>[1;32mNOP[0m:
>        [31mTrace point ID: 194
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 2312
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00092dcb
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09746a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4194
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c3
>[1;32mNOP[0m:
>        [31mTrace point ID: 195
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000089ba
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00091d69
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09952e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 192
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c4
>[1;32mNOP[0m:
>        [31mTrace point ID: 196
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 21964
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00091ca9
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0996ae
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2304
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c5
>[1;32mNOP[0m:
>        [31mTrace point ID: 197
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000d8c0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000913a9
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09a8ae
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 768
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c6
>[1;32mNOP[0m:
>        [31mTrace point ID: 198
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009988
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000910a9
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09aeae
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1818
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c7
>[1;32mNOP[0m:
>        [31mTrace point ID: 199
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00011a3a
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009098f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09bce2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c8
>[1;32mNOP[0m:
>        [31mTrace point ID: 200
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e230a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e230c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e230e00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e231300
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e231500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009095f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09bd42
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1104
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000c9
>[1;32mNOP[0m:
>        [31mTrace point ID: 201
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009050f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09c5e2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ca
>[1;32mNOP[0m:
>        [31mTrace point ID: 202
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 19652
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000904df
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09c642
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 96
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000cb
>[1;32mNOP[0m:
>        [31mTrace point ID: 203
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 2312
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009047f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09c702
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 96
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000cc
>[1;32mNOP[0m:
>        [31mTrace point ID: 204
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009080
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009041f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09c7c2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 288
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000cd
>[1;32mNOP[0m:
>        [31mTrace point ID: 205
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e231900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e231b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e231d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e232200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e232400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000902ff
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09ca02
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2736
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ce
>[1;32mNOP[0m:
>        [31mTrace point ID: 206
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008f84f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09df62
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2736
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000cf
>[1;32mNOP[0m:
>        [31mTrace point ID: 207
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008ed9f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09f4c2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 672
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d0
>[1;32mNOP[0m:
>        [31mTrace point ID: 208
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e232800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e232a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e232c00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e233100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e233300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008eaff
>        [1;33mVGT_DMA_BASE[0m <- 0x5e09fa02
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2736
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d1
>[1;32mNOP[0m:
>        [31mTrace point ID: 209
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008e04f
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a0f62
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2628
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d2
>[1;32mNOP[0m:
>        [31mTrace point ID: 210
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008d60b
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a23ea
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 612
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d3
>[1;32mNOP[0m:
>        [31mTrace point ID: 211
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e233700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e233900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e233b00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e234000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e234200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008d3a7
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a28b2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1290
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d4
>[1;32mNOP[0m:
>        [31mTrace point ID: 212
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008ce9d
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a32c6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1362
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d5
>[1;32mNOP[0m:
>        [31mTrace point ID: 213
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008c94b
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a3d6a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 330
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d6
>[1;32mNOP[0m:
>        [31mTrace point ID: 214
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e234600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e234800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e234a00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e234f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e235100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008c801
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a3ffe
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1131
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d7
>[1;32mNOP[0m:
>        [31mTrace point ID: 215
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008c396
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a48d4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 753
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d8
>[1;32mNOP[0m:
>        [31mTrace point ID: 216
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008c0a5
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a4eb6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 168
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000d9
>[1;32mNOP[0m:
>        [31mTrace point ID: 217
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e235500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e235700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e235900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e235e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e236000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008bffd
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a5006
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 501
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000da
>[1;32mNOP[0m:
>        [31mTrace point ID: 218
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008be08
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a53f0
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000db
>[1;32mNOP[0m:
>        [31mTrace point ID: 219
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 19652
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008bdfc
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a5408
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 177
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000dc
>[1;32mNOP[0m:
>        [31mTrace point ID: 220
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 2312
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008bd4b
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a556a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1104
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000dd
>[1;32mNOP[0m:
>        [31mTrace point ID: 221
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000089ba
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b8fb
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a5e0a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000de
>[1;32mNOP[0m:
>        [31mTrace point ID: 222
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 21964
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b8cb
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a5e6a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 576
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000df
>[1;32mNOP[0m:
>        [31mTrace point ID: 223
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000d8c0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b68b
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a62ea
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 192
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e0
>[1;32mNOP[0m:
>        [31mTrace point ID: 224
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009988
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b5cb
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a646a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 720
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e1
>[1;32mNOP[0m:
>        [31mTrace point ID: 225
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00011a3a
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b2fb
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a6a0a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e2
>[1;32mNOP[0m:
>        [31mTrace point ID: 226
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000e64c
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b2ef
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a6a22
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 189
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e3
>[1;32mNOP[0m:
>        [31mTrace point ID: 227
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e236400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e236600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e236800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e236d00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e236f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000d8c0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008b232
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a6b9c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 768
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e4
>[1;32mNOP[0m:
>        [31mTrace point ID: 228
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e237300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e237500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e237700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e237c00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e237e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008af32
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a719c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1104
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e5
>[1;32mNOP[0m:
>        [31mTrace point ID: 229
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008aae2
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a7a3c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e6
>[1;32mNOP[0m:
>        [31mTrace point ID: 230
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 19652
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008aab2
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a7a9c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1392
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e7
>[1;32mNOP[0m:
>        [31mTrace point ID: 231
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000cd76
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008a542
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a857c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1044
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e8
>[1;32mNOP[0m:
>        [31mTrace point ID: 232
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009988
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008a12e
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0a8da4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3408
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000e9
>[1;32mNOP[0m:
>        [31mTrace point ID: 233
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00011a3a
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000893de
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aa844
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 192
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ea
>[1;32mNOP[0m:
>        [31mTrace point ID: 234
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000e64c
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008931e
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aa9c4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000eb
>[1;32mNOP[0m:
>        [31mTrace point ID: 235
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e238200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e238400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e238600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e238b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e238d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000b4a0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00088d1e
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0ab5c4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 576
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ec
>[1;32mNOP[0m:
>        [31mTrace point ID: 236
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e239100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e239300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e239500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e239a00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e239c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00088ade
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aba44
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2670
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ed
>[1;32mNOP[0m:
>        [31mTrace point ID: 237
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00088070
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0acf20
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2736
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ee
>[1;32mNOP[0m:
>        [31mTrace point ID: 238
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000875c0
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0ae480
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 672
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ef
>[1;32mNOP[0m:
>        [31mTrace point ID: 239
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23a000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23a200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e23a400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e23a900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23ab00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00087320
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0ae9c0
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 276
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f0
>[1;32mNOP[0m:
>        [31mTrace point ID: 240
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0008720c
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aebe8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f1
>[1;32mNOP[0m:
>        [31mTrace point ID: 241
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 19652
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00087200
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aec00
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 96
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f2
>[1;32mNOP[0m:
>        [31mTrace point ID: 242
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 11560
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000871a0
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aecc0
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 351
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f3
>[1;32mNOP[0m:
>        [31mTrace point ID: 243
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000b4a0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00087041
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aef7e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f4
>[1;32mNOP[0m:
>        [31mTrace point ID: 244
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009504
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00087011
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0aefde
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 645
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f5
>[1;32mNOP[0m:
>        [31mTrace point ID: 245
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000115b6
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00086d8c
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0af4e8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f6
>[1;32mNOP[0m:
>        [31mTrace point ID: 246
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00009988
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00086d5c
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0af548
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1098
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f7
>[1;32mNOP[0m:
>        [31mTrace point ID: 247
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00011a3a
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00086912
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0afddc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f8
>[1;32mNOP[0m:
>        [31mTrace point ID: 248
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0000e64c
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000868e2
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0afe3c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 384
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000f9
>[1;32mNOP[0m:
>        [31mTrace point ID: 249
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23af00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23b100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e23b300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e23b800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23ba00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00086762
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0b013c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 732
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000fa
>[1;32mNOP[0m:
>        [31mTrace point ID: 250
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x000080b2
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00086486
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0b06f4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1041
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000fb
>[1;32mNOP[0m:
>        [31mTrace point ID: 251
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x00010164
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00086075
>        [1;33mVGT_DMA_BASE[0m <- 0x5e0b0f16
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 315
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000fc
>[1;32mNOP[0m:
>        [31mTrace point ID: 252
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23bd00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23bf00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e23c100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e23c600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23c800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012b7f30
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012b7f50
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000fd
>[1;32mNOP[0m:
>        [31mTrace point ID: 253
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23cb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23cd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23cf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000fe
>[1;32mNOP[0m:
>        [31mTrace point ID: 254
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23d200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23d400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23d600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000000ff
>[1;32mNOP[0m:
>        [31mTrace point ID: 255
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23d900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23db00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23dd00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000100
>[1;32mNOP[0m:
>        [31mTrace point ID: 256
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23e000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23e200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23e400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000101
>[1;32mNOP[0m:
>        [31mTrace point ID: 257
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23e700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23e900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23eb00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000102
>[1;32mNOP[0m:
>        [31mTrace point ID: 258
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23ee00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23f000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23f200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000103
>[1;32mNOP[0m:
>        [31mTrace point ID: 259
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23f500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23f700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e23f900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000104
>[1;32mNOP[0m:
>        [31mTrace point ID: 260
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e23fc00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e23fe00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e240000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000105
>[1;32mNOP[0m:
>        [31mTrace point ID: 261
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e240300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e240500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e240700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000106
>[1;32mNOP[0m:
>        [31mTrace point ID: 262
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e240a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e240c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e240e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000107
>[1;32mNOP[0m:
>        [31mTrace point ID: 263
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e241100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e241300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e241500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000108
>[1;32mNOP[0m:
>        [31mTrace point ID: 264
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e241800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e241a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e241c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000109
>[1;32mNOP[0m:
>        [31mTrace point ID: 265
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e241f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e242100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e242300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000010a
>[1;32mNOP[0m:
>        [31mTrace point ID: 266
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e242600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e242800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e242a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000010b
>[1;32mNOP[0m:
>        [31mTrace point ID: 267
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e242d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e242f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e243100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000010c
>[1;32mNOP[0m:
>        [31mTrace point ID: 268
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e243400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e243600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e243800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0014e2f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e97800
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000010d
>[1;32mNOP[0m:
>        [31mTrace point ID: 269
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e243b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e243d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e243f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000010e
>[1;32mNOP[0m:
>        [31mTrace point ID: 270
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e244200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e244400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e244600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x000918f6
>        [1;33mVGT_DMA_BASE[0m <- 0x29010c00
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000010f
>[1;32mNOP[0m:
>        [31mTrace point ID: 271
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e244900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e244b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e244d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000110
>[1;32mNOP[0m:
>        [31mTrace point ID: 272
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e245000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e245200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e245400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000111
>[1;32mNOP[0m:
>        [31mTrace point ID: 273
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e245700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e245900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e245b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000112
>[1;32mNOP[0m:
>        [31mTrace point ID: 274
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e245e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e246000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e246200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000113
>[1;32mNOP[0m:
>        [31mTrace point ID: 275
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e246500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e246700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e246900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000114
>[1;32mNOP[0m:
>        [31mTrace point ID: 276
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e246c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e246e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e247000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000115
>[1;32mNOP[0m:
>        [31mTrace point ID: 277
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e247300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e247500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e247700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000116
>[1;32mNOP[0m:
>        [31mTrace point ID: 278
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e247a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e247c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e247e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000117
>[1;32mNOP[0m:
>        [31mTrace point ID: 279
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e248100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e248300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e248500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000118
>[1;32mNOP[0m:
>        [31mTrace point ID: 280
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e248800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e248a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e248c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000119
>[1;32mNOP[0m:
>        [31mTrace point ID: 281
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e248f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e249100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e249300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000011a
>[1;32mNOP[0m:
>        [31mTrace point ID: 282
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e249600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e249800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e249a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000011b
>[1;32mNOP[0m:
>        [31mTrace point ID: 283
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e249d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e249f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24a100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00157ef6
>        [1;33mVGT_DMA_BASE[0m <- 0x28e84000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000011c
>[1;32mNOP[0m:
>        [31mTrace point ID: 284
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24a400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24a600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24a800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000011d
>[1;32mNOP[0m:
>        [31mTrace point ID: 285
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24ab00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24ad00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24af00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0009c6f6
>        [1;33mVGT_DMA_BASE[0m <- 0x28ffb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000011e
>[1;32mNOP[0m:
>        [31mTrace point ID: 286
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR2_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR3_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0127bd70
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P8_32X32_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 1
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_INVALID
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_1KB
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 1
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x012e0c00
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x012e0c00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x012e0c00
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x012e0c00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 511
>                         HEIGHT_TILE_MAX = 511
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 0x3ffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CLEAR[0m <- 1.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 4096
>                                   BR_Y = 4096
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 1
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_LINE_CNTL[0m <- EXPAND_LINE_WIDTH = 0
>                           LAST_PIXEL = 1
>                           PERPENDICULAR_ENDCAP_ENA = 0
>                           DX10_DIAMOND_TEST_ENA = 0
>        [1;33mPA_SC_AA_CONFIG[0m <- MSAA_NUM_SAMPLES = 0
>                           AA_MASK_CENTROID_DTMN = 0
>                           MAX_SAMPLE_DIST = 0
>                           MSAA_EXPOSED_SAMPLES = 0
>                           DETAIL_TO_EXPOSED_MODE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                   PS_ITER_SAMPLES = 0
>                   MASK_EXPORT_NUM_SAMPLES = 0
>                   ALPHA_TO_MASK_NUM_SAMPLES = 0
>                   HIGH_QUALITY_INTERSECTIONS = 1
>                   INCOHERENT_EQAA_READS = 0
>                   INTERPOLATE_COMP_Z = 0
>                   INTERPOLATE_SRC_Z = 0
>                   STATIC_ANCHOR_ASSOCIATIONS = 1
>                   ALPHA_TO_MASK_EQAA_DISABLE = 0
>                   OVERRASTERIZATION_AMOUNT = 0
>                   ENABLE_POSTZ_OVERRASTERIZATION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                             WALK_ALIGNMENT = 0
>                             WALK_ALIGN8_PRIM_FITS_ST = 0
>                             WALK_FENCE_ENABLE = 0
>                             WALK_FENCE_SIZE = 0
>                             SUPERTILE_WALK_ORDER_ENABLE = 0
>                             TILE_WALK_ORDER_ENABLE = 0
>                             TILE_COVER_DISABLE = 0
>                             TILE_COVER_NO_SCISSOR = 0
>                             ZMM_LINE_EXTENT = 0
>                             ZMM_LINE_OFFSET = 0
>                             ZMM_RECT_EXTENT = 0
>                             KILL_PIX_POST_HI_Z = 0
>                             KILL_PIX_POST_DETAIL_MASK = 0
>                             PS_ITER_SAMPLE = 0
>                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
>                             MULTI_GPU_SUPERTILE_ENABLE = 0
>                             GPU_ID_OVERRIDE_ENABLE = 0
>                             GPU_ID_OVERRIDE = 0
>                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                             FORCE_EOV_CNTDWN_ENABLE = 0
>                             FORCE_EOV_REZ_ENABLE = 0
>                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                             OUT_OF_ORDER_WATER_MARK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x5e24b500
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24b300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24b600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e24b800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24bd00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 4096
>                                    BR_Y = 4096
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 1
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_ALWAYS
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01002240
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce970
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 0
>                              MAX_PRIMGRP_IN_WAVE = 2
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000011f
>[1;32mNOP[0m:
>        [31mTrace point ID: 287
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x5e24c300
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24c100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24c400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e24c600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e24cb00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24cd00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 1
>                              POLY_OFFSET_BACK_ENABLE = 1
>                              POLY_OFFSET_PARA_ENABLE = 1
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 1
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_LEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_FRONT_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_FRONT_OFFSET[0m <- 80.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_OFFSET[0m <- 80.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce980
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce990
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 0
>                              MAX_PRIMGRP_IN_WAVE = 2
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1962
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000120
>[1;32mNOP[0m:
>        [31mTrace point ID: 288
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24d100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24d300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e24d500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e24da00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24dc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000121
>[1;32mNOP[0m:
>        [31mTrace point ID: 289
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24e000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24e200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e24e400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e24e900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24eb00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3342
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000122
>[1;32mNOP[0m:
>        [31mTrace point ID: 290
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24ef00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e24f100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e24f300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e24f800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e24fa00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19344
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000123
>[1;32mNOP[0m:
>        [31mTrace point ID: 291
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e24fe00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e250000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e250200
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e250700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e250900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 14418
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000124
>[1;32mNOP[0m:
>        [31mTrace point ID: 292
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e250d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e250f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e251100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e251600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e251800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19350
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000125
>[1;32mNOP[0m:
>        [31mTrace point ID: 293
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e251c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e251e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e252000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e252500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e252700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19332
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000126
>[1;32mNOP[0m:
>        [31mTrace point ID: 294
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e252b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e252d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e252f00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e253400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e253600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5058
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000127
>[1;32mNOP[0m:
>        [31mTrace point ID: 295
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e253a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e253c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e253e00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e254300
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e254500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1236
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000128
>[1;32mNOP[0m:
>        [31mTrace point ID: 296
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e254900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e254b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e254d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e255200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e255400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4848
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000129
>[1;32mNOP[0m:
>        [31mTrace point ID: 297
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e255800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e255a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e255c00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e256100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e256300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5046
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000012a
>[1;32mNOP[0m:
>        [31mTrace point ID: 298
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e256700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e256900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e256b00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e257000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e257200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2136
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000012b
>[1;32mNOP[0m:
>        [31mTrace point ID: 299
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e257600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e257800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e257a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1284
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000012c
>[1;32mNOP[0m:
>        [31mTrace point ID: 300
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e257e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e258000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e258200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000012d
>[1;32mNOP[0m:
>        [31mTrace point ID: 301
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e258600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e258800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e258a00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e258f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e259100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2124
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000012e
>[1;32mNOP[0m:
>        [31mTrace point ID: 302
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e259500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e259700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e259900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1290
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000012f
>[1;32mNOP[0m:
>        [31mTrace point ID: 303
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e259d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e259f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25a100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1518
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000130
>[1;32mNOP[0m:
>        [31mTrace point ID: 304
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25a500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25a700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e25a900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e25ae00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25b000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8454
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000131
>[1;32mNOP[0m:
>        [31mTrace point ID: 305
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25b400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25b600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25b800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5202
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000132
>[1;32mNOP[0m:
>        [31mTrace point ID: 306
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25bc00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25be00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25c000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6012
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000133
>[1;32mNOP[0m:
>        [31mTrace point ID: 307
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25c400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25c600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25c800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5556
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000134
>[1;32mNOP[0m:
>        [31mTrace point ID: 308
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25cc00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25ce00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25d000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3438
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000135
>[1;32mNOP[0m:
>        [31mTrace point ID: 309
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25d400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25d600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25d800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3978
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000136
>[1;32mNOP[0m:
>        [31mTrace point ID: 310
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25dc00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25de00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e25e000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e25e500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25e700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 7740
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000137
>[1;32mNOP[0m:
>        [31mTrace point ID: 311
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25eb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25ed00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25ef00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12774
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000138
>[1;32mNOP[0m:
>        [31mTrace point ID: 312
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25f300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25f500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e25f700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3066
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000139
>[1;32mNOP[0m:
>        [31mTrace point ID: 313
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e25fb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e25fd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e25ff00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e260400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e260600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 942
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000013a
>[1;32mNOP[0m:
>        [31mTrace point ID: 314
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e260a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e260c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e260e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 246
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000013b
>[1;32mNOP[0m:
>        [31mTrace point ID: 315
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e261200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e261400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e261600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 444
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000013c
>[1;32mNOP[0m:
>        [31mTrace point ID: 316
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e261a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e261c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e261e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 456
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000013d
>[1;32mNOP[0m:
>        [31mTrace point ID: 317
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e262700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e262900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e262b00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e263000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e263200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 1
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 1
>                              POLY_OFFSET_BACK_ENABLE = 1
>                              POLY_OFFSET_PARA_ENABLE = 1
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_FRONT_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_FRONT_OFFSET[0m <- 80.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_OFFSET[0m <- 80.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5205
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca86e4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 582
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000013e
>[1;32mNOP[0m:
>        [31mTrace point ID: 318
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e263b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e263d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e263f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e264100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 13575
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bdd76
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3762
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000013f
>[1;32mNOP[0m:
>        [31mTrace point ID: 319
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e264a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e264c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e264e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e265000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9813
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bfada
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1890
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000140
>[1;32mNOP[0m:
>        [31mTrace point ID: 320
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e265900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e265b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e265d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e266200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e266400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 102
>        [1;33mVGT_DMA_BASE[0m <- 0x3b56d0a8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 102
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000141
>[1;32mNOP[0m:
>        [31mTrace point ID: 321
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e266d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e266f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e267100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 102
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd4078
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 102
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000142
>[1;32mNOP[0m:
>        [31mTrace point ID: 322
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e267a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e267c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e267e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 60
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd6000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000143
>[1;32mNOP[0m:
>        [31mTrace point ID: 323
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e268700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e268900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e268b00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e269000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e269200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 19
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000144
>[1;32mNOP[0m:
>        [31mTrace point ID: 324
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e269b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e269d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e269f00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e26a400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e26a600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 12
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000145
>[1;32mNOP[0m:
>        [31mTrace point ID: 325
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e26af00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e26b100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e26b300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e26b800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e26ba00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013afd10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013afd20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x3b56d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 84
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000146
>[1;32mNOP[0m:
>        [31mTrace point ID: 326
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e26c300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e26c500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e26c700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 162
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd4000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 60
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000147
>[1;32mNOP[0m:
>        [31mTrace point ID: 327
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e26d000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e26d200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e26d400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 48
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd6018
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000148
>[1;32mNOP[0m:
>        [31mTrace point ID: 328
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e26dd00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e26df00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e26e100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e26e600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e26e800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 6
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x362be000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 72
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000149
>[1;32mNOP[0m:
>        [31mTrace point ID: 329
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e26f000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e26f200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e26f400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e26f900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9c0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9d0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1116
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaa6d6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 861
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000014a
>[1;32mNOP[0m:
>        [31mTrace point ID: 330
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e270100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e270300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 255
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaad90
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 255
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000014b
>[1;32mNOP[0m:
>        [31mTrace point ID: 331
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e270b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e270d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1845
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c391a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1431
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000014c
>[1;32mNOP[0m:
>        [31mTrace point ID: 332
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e271600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e271800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e271a00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e271f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e272100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b890
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 27
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3684
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d060
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3684
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000014d
>[1;32mNOP[0m:
>        [31mTrace point ID: 333
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e272a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e272c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e272e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e273000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b8b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 11
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3684
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d060
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3684
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000014e
>[1;32mNOP[0m:
>        [31mTrace point ID: 334
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e273900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e273b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e273d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e274200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e274400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b890
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4980
>        [1;33mVGT_DMA_BASE[0m <- 0x3affb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4860
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000014f
>[1;32mNOP[0m:
>        [31mTrace point ID: 335
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e274d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e274f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e275100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e275300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b8b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4980
>        [1;33mVGT_DMA_BASE[0m <- 0x3affb000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4860
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000150
>[1;32mNOP[0m:
>        [31mTrace point ID: 336
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e275c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e275e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e276000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e276500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e276700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b890
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 120
>        [1;33mVGT_DMA_BASE[0m <- 0x3affd5f8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 120
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000151
>[1;32mNOP[0m:
>        [31mTrace point ID: 337
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e277000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e277200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e277400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e277600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b8b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 120
>        [1;33mVGT_DMA_BASE[0m <- 0x3affd5f8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 120
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000152
>[1;32mNOP[0m:
>        [31mTrace point ID: 338
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e277f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e278100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e278300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e278800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e278a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b890
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000153
>[1;32mNOP[0m:
>        [31mTrace point ID: 339
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e279300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e279500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000154
>[1;32mNOP[0m:
>        [31mTrace point ID: 340
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e279f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27a100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000155
>[1;32mNOP[0m:
>        [31mTrace point ID: 341
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27ab00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27ad00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000156
>[1;32mNOP[0m:
>        [31mTrace point ID: 342
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27b700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27b900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000157
>[1;32mNOP[0m:
>        [31mTrace point ID: 343
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27c300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27c500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e27c700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e27c900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b8b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000158
>[1;32mNOP[0m:
>        [31mTrace point ID: 344
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27d200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27d400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 6
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000159
>[1;32mNOP[0m:
>        [31mTrace point ID: 345
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27d900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27db00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e27dd00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e27e200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e27e400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 3072.0f
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 1
>                              POLY_OFFSET_BACK_ENABLE = 1
>                              POLY_OFFSET_PARA_ENABLE = 1
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_FRONT_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_FRONT_OFFSET[0m <- 80.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_OFFSET[0m <- 80.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce980
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce990
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1962
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000015a
>[1;32mNOP[0m:
>        [31mTrace point ID: 346
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27e800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27ea00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e27ec00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e27f100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e27f300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000015b
>[1;32mNOP[0m:
>        [31mTrace point ID: 347
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e27f700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e27f900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e27fb00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e280000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e280200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3342
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000015c
>[1;32mNOP[0m:
>        [31mTrace point ID: 348
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e280600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e280800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e280a00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e280f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e281100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19344
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000015d
>[1;32mNOP[0m:
>        [31mTrace point ID: 349
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e281500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e281700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e281900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e281e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e282000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 14418
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000015e
>[1;32mNOP[0m:
>        [31mTrace point ID: 350
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e282400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e282600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e282800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e282d00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e282f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19350
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000015f
>[1;32mNOP[0m:
>        [31mTrace point ID: 351
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e283300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e283500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e283700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e283c00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e283e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19332
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000160
>[1;32mNOP[0m:
>        [31mTrace point ID: 352
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e284200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e284400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e284600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e284b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e284d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5058
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000161
>[1;32mNOP[0m:
>        [31mTrace point ID: 353
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e285100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e285300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e285500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e285a00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e285c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1236
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000162
>[1;32mNOP[0m:
>        [31mTrace point ID: 354
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e286000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e286200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e286400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e286900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e286b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4848
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000163
>[1;32mNOP[0m:
>        [31mTrace point ID: 355
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e286f00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e287100
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e287300
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e287800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e287a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5046
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000164
>[1;32mNOP[0m:
>        [31mTrace point ID: 356
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e287e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e288000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e288200
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e288700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e288900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2136
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000165
>[1;32mNOP[0m:
>        [31mTrace point ID: 357
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e288d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e288f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e289100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1284
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000166
>[1;32mNOP[0m:
>        [31mTrace point ID: 358
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e289500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e289700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e289900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000167
>[1;32mNOP[0m:
>        [31mTrace point ID: 359
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e289d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e289f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e28a100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e28a600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28a800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2124
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000168
>[1;32mNOP[0m:
>        [31mTrace point ID: 360
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28ac00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28ae00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28b000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1290
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000169
>[1;32mNOP[0m:
>        [31mTrace point ID: 361
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28b400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28b600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28b800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1518
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000016a
>[1;32mNOP[0m:
>        [31mTrace point ID: 362
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28bc00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28be00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e28c000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e28c500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28c700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8454
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000016b
>[1;32mNOP[0m:
>        [31mTrace point ID: 363
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28cb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28cd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28cf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5202
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000016c
>[1;32mNOP[0m:
>        [31mTrace point ID: 364
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28d300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28d500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28d700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 6012
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000016d
>[1;32mNOP[0m:
>        [31mTrace point ID: 365
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28db00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28dd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28df00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5556
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000016e
>[1;32mNOP[0m:
>        [31mTrace point ID: 366
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28e300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28e500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28e700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3438
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000016f
>[1;32mNOP[0m:
>        [31mTrace point ID: 367
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28eb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28ed00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28ef00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3978
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000170
>[1;32mNOP[0m:
>        [31mTrace point ID: 368
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e28f300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e28f500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e28f700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e28fc00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e28fe00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 7740
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000171
>[1;32mNOP[0m:
>        [31mTrace point ID: 369
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e290200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e290400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e290600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12774
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000172
>[1;32mNOP[0m:
>        [31mTrace point ID: 370
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e290a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e290c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e290e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3066
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000173
>[1;32mNOP[0m:
>        [31mTrace point ID: 371
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e291200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e291400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e291600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 8730
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000174
>[1;32mNOP[0m:
>        [31mTrace point ID: 372
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e291a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e291c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e291e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 11406
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000175
>[1;32mNOP[0m:
>        [31mTrace point ID: 373
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e292200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e292400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e292600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5172
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000176
>[1;32mNOP[0m:
>        [31mTrace point ID: 374
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e292a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e292c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e292e00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e293300
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e293500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 942
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000177
>[1;32mNOP[0m:
>        [31mTrace point ID: 375
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e293900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e293b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e293d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 246
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000178
>[1;32mNOP[0m:
>        [31mTrace point ID: 376
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e294100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e294300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e294500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 444
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000179
>[1;32mNOP[0m:
>        [31mTrace point ID: 377
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e294900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e294b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e294d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 456
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000017a
>[1;32mNOP[0m:
>        [31mTrace point ID: 378
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e295600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e295800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e295a00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e295f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e296100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 1
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 1
>                              POLY_OFFSET_BACK_ENABLE = 1
>                              POLY_OFFSET_PARA_ENABLE = 1
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_FRONT_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_FRONT_OFFSET[0m <- 80.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_OFFSET[0m <- 80.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7197
>        [1;33mVGT_DMA_BASE[0m <- 0x4e3de1ac
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1926
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000017b
>[1;32mNOP[0m:
>        [31mTrace point ID: 379
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e296a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e296c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e296e00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e297300
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e297500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 6369
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca7dcc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1164
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000017c
>[1;32mNOP[0m:
>        [31mTrace point ID: 380
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e297e00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e298000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e298200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e298400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 6369
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca7dcc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1164
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000017d
>[1;32mNOP[0m:
>        [31mTrace point ID: 381
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e298d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e298f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e299100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e299300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5205
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca86e4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 582
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000017e
>[1;32mNOP[0m:
>        [31mTrace point ID: 382
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e299c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e299e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e29a000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29a200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5205
>        [1;33mVGT_DMA_BASE[0m <- 0x4dca86e4
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 582
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000017f
>[1;32mNOP[0m:
>        [31mTrace point ID: 383
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e29ab00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e29ad00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e29af00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29b100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 13575
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bdd76
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3762
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000180
>[1;32mNOP[0m:
>        [31mTrace point ID: 384
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e29ba00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e29bc00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e29be00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29c000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 13575
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bdd76
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3762
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000181
>[1;32mNOP[0m:
>        [31mTrace point ID: 385
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e29c900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e29cb00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e29cd00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29cf00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9813
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bfada
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1890
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000182
>[1;32mNOP[0m:
>        [31mTrace point ID: 386
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e29d800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e29da00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e29dc00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29de00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9813
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9bfada
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1890
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000183
>[1;32mNOP[0m:
>        [31mTrace point ID: 387
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e29e700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e29e900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e29eb00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e29f000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29f200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1599
>        [1;33mVGT_DMA_BASE[0m <- 0x36b322fc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 150
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000184
>[1;32mNOP[0m:
>        [31mTrace point ID: 388
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e29fb00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e29fd00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e29ff00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4488
>        [1;33mVGT_DMA_BASE[0m <- 0x3623d672
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 450
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000185
>[1;32mNOP[0m:
>        [31mTrace point ID: 389
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a0800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a0a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a0c00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a0e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9015
>        [1;33mVGT_DMA_BASE[0m <- 0x2cea9f0e
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1482
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000186
>[1;32mNOP[0m:
>        [31mTrace point ID: 390
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a1700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a1900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a1b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a1d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7533
>        [1;33mVGT_DMA_BASE[0m <- 0x2ceaaaa2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 750
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000187
>[1;32mNOP[0m:
>        [31mTrace point ID: 391
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a2600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a2800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a2a00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a2c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b870
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b880
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 7533
>        [1;33mVGT_DMA_BASE[0m <- 0x2ceaaaa2
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 750
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000188
>[1;32mNOP[0m:
>        [31mTrace point ID: 392
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a3500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a3700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a3900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a3b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 7
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9b0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 5283
>        [1;33mVGT_DMA_BASE[0m <- 0x27f6b302
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 288
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000189
>[1;32mNOP[0m:
>        [31mTrace point ID: 393
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a4400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a4600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2a4800
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a4d00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a4f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 8
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 102
>        [1;33mVGT_DMA_BASE[0m <- 0x3b56d0a8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 102
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000018a
>[1;32mNOP[0m:
>        [31mTrace point ID: 394
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a5800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a5a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a5c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 102
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd4078
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 102
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000018b
>[1;32mNOP[0m:
>        [31mTrace point ID: 395
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a6500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a6700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a6900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 60
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd6000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 12
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000018c
>[1;32mNOP[0m:
>        [31mTrace point ID: 396
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a7200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a7400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2a7600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a7b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a7d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000018d
>[1;32mNOP[0m:
>        [31mTrace point ID: 397
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a8600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a8800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 5
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000018e
>[1;32mNOP[0m:
>        [31mTrace point ID: 398
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2a9200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2a9400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2a9600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2a9b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2a9d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 23
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 114
>        [1;33mVGT_DMA_BASE[0m <- 0x362be090
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 114
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000018f
>[1;32mNOP[0m:
>        [31mTrace point ID: 399
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2aa600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2aa800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2aaa00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2aaf00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2ab100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x013afd10
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x013afd20
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 8
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 186
>        [1;33mVGT_DMA_BASE[0m <- 0x3b56d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 84
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000190
>[1;32mNOP[0m:
>        [31mTrace point ID: 400
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2aba00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2abc00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2abe00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 162
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd4000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 60
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000191
>[1;32mNOP[0m:
>        [31mTrace point ID: 401
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2ac700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2ac900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2acb00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 48
>        [1;33mVGT_DMA_BASE[0m <- 0x3afd6018
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000192
>[1;32mNOP[0m:
>        [31mTrace point ID: 402
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2ad300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2ad500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2ad700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2adc00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce9c0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce9d0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 312
>        [1;33mVGT_DMA_BASE[0m <- 0x4e3e1776
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 312
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000193
>[1;32mNOP[0m:
>        [31mTrace point ID: 403
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2ae400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2ae600
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1116
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaa6d6
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 861
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000194
>[1;32mNOP[0m:
>        [31mTrace point ID: 404
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2aee00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2af000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 255
>        [1;33mVGT_DMA_BASE[0m <- 0x4dcaad90
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 255
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000195
>[1;32mNOP[0m:
>        [31mTrace point ID: 405
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2af800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2afa00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 1845
>        [1;33mVGT_DMA_BASE[0m <- 0x4e9c391a
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1431
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000196
>[1;32mNOP[0m:
>        [31mTrace point ID: 406
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b0200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2b0400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 294
>        [1;33mVGT_DMA_BASE[0m <- 0x27f6d9fc
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 294
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000197
>[1;32mNOP[0m:
>        [31mTrace point ID: 407
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b0d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b0f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2b1100
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2b1600
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2b1800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b890
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 4
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 120
>        [1;33mVGT_DMA_BASE[0m <- 0x3affd5f8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 120
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000198
>[1;32mNOP[0m:
>        [31mTrace point ID: 408
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b2100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b2300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2b2500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2b2700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b8b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 120
>        [1;33mVGT_DMA_BASE[0m <- 0x3affd5f8
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 120
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000199
>[1;32mNOP[0m:
>        [31mTrace point ID: 409
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b3000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b3200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2b3400
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2b3900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2b3b00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b890
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000019a
>[1;32mNOP[0m:
>        [31mTrace point ID: 410
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b4400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b4600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000019b
>[1;32mNOP[0m:
>        [31mTrace point ID: 411
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b5000
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b5200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000019c
>[1;32mNOP[0m:
>        [31mTrace point ID: 412
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b5c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b5e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000019d
>[1;32mNOP[0m:
>        [31mTrace point ID: 413
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b6800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b6a00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000019e
>[1;32mNOP[0m:
>        [31mTrace point ID: 414
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b7400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b7600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2b7800
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2b7a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0140b8b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0140b8c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 32
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x0000019f
>[1;32mNOP[0m:
>        [31mTrace point ID: 415
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b8300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b8500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 10
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3732
>        [1;33mVGT_DMA_BASE[0m <- 0x3a47d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 48
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a0
>[1;32mNOP[0m:
>        [31mTrace point ID: 416
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b8a00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b8c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2b8e00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2b9300
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2b9500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1024.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 3072.0f
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 1
>                              POLY_OFFSET_BACK_ENABLE = 1
>                              POLY_OFFSET_PARA_ENABLE = 1
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_FRONT_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_FRONT_OFFSET[0m <- 80.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_SCALE[0m <- 64.0f
>        [1;33mPA_SU_POLY_OFFSET_BACK_OFFSET[0m <- 80.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x012ce980
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 5
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 1
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_32_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x012ce990
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1962
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a1
>[1;32mNOP[0m:
>        [31mTrace point ID: 417
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2b9900
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2b9b00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2b9d00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2ba200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2ba400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2688
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a2
>[1;32mNOP[0m:
>        [31mTrace point ID: 418
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2ba800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2baa00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2bac00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2bb100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2bb300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 3342
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a3
>[1;32mNOP[0m:
>        [31mTrace point ID: 419
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2bb700
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2bb900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x5e2bbb00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x5e2bc000
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2bc200
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19344
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a4
>[1;32mNOP[0m:
>        [31mTrace point ID: 420
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2bc600
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x5e2bc800
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x5e2bca00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2820
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a5
>[1;32mNOP[0m:
>        [31mTrace point ID: 421
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x5e2bce00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29400000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x29400200
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x29400700
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29400900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 14418
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a6
>[1;32mNOP[0m:
>        [31mTrace point ID: 422
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29400d00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29400f00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29401100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2100
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a7
>[1;32mNOP[0m:
>        [31mTrace point ID: 423
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29401500
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29401700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x29401900
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x29401e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29402000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19350
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a8
>[1;32mNOP[0m:
>        [31mTrace point ID: 424
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29402400
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29402600
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29402800
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2832
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001a9
>[1;32mNOP[0m:
>        [31mTrace point ID: 425
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29402c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29402e00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x29403000
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x29403500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29403700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 19332
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001aa
>[1;32mNOP[0m:
>        [31mTrace point ID: 426
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29403b00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29403d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29403f00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 2832
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001ab
>[1;32mNOP[0m:
>        [31mTrace point ID: 427
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29404300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29404500
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x29404700
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x29404c00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29404e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 5058
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001ac
>[1;32mNOP[0m:
>        [31mTrace point ID: 428
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29405200
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29405400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x29405600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x29405b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29405d00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 1236
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001ad
>[1;32mNOP[0m:
>        [31mTrace point ID: 429
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x29406100
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x29406300
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x29406500
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x29406a00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x29406c00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00008454
>        [1;33mVGT_DMA_BASE[0m <- 0x038b8000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 4848
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001ae
>[1;32mNOP[0m:
>        [31mTrace point ID: 430
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00111000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x000001af
>[1;32mNOP[0m:
>        [31mTrace point ID: 431
>        [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>------------------- IB end -------------------

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Attachments on bug 91278: 117012 | 117013 | 117739 | 117964 | 118448 | 118665 | 118824 | 119679

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