Attachment 120588 Details for Bug 93436 – R600_DEBUG=check_vm capture of VM fault

R600_DEBUG=check_vm capture of VM fault

glretrace_30772_00000000 (text/plain), 2.09 MB, created by Shawn Starr on 2015-12-18 23:58:59 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Shawn Starr

Created: 2015-12-18 23:58:59 UTC

Size: 2.09 MB

patch

obsolete

>VM fault report.
>
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD BONAIRE (DRM 2.43.0, LLVM 3.8.0)
>
>Failing VM page: 0x00095080
>
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>          16    0x0000000000871       0x0000000000881       BORDER_COLORS
>           1    0x0000000000881       0x0000000000882       USER_SHADER
>           1    -- hole --
>           1    0x0000000000883       0x0000000000884       CONST_BUFFER
>         192    -- hole --
>          64    0x0000000000944       0x0000000000984       SAMPLER_TEXTURE
>         136    -- hole --
>           1    0x0000000000a0c       0x0000000000a0d       VERTEX_BUFFER
>           8    -- hole --
>           1    0x0000000000a15       0x0000000000a16       VERTEX_BUFFER
>          74    -- hole --
>          64    0x0000000000a60       0x0000000000aa0       INDEX_BUFFER
>          68    -- hole --
>           1    0x0000000000ae4       0x0000000000ae5       VERTEX_BUFFER
>          15    -- hole --
>           1    0x0000000000af4       0x0000000000af5       SAMPLER_TEXTURE
>           5    -- hole --
>           1    0x0000000000afa       0x0000000000afb       SAMPLER_TEXTURE
>           1    0x0000000000afb       0x0000000000afc       SAMPLER_TEXTURE
>           7    -- hole --
>           1    0x0000000000b03       0x0000000000b04       INDEX_BUFFER
>       16004    -- hole --
>         256    0x0000000004988       0x0000000004a88       CONST_BUFFER, DESCRIPTORS
>         200    -- hole --
>          18    0x0000000004b50       0x0000000004b62       HTILE
>         363    -- hole --
>           1    0x0000000004ccd       0x0000000004cce       CONST_BUFFER
>        1105    -- hole --
>           1    0x000000000511f       0x0000000005120       USER_SHADER
>          31    -- hole --
>           1    0x000000000513f       0x0000000005140       USER_SHADER
>          72    -- hole --
>           1    0x0000000005188       0x0000000005189       USER_SHADER
>           1    0x0000000005189       0x000000000518a       USER_SHADER
>           1    0x000000000518a       0x000000000518b       USER_SHADER
>           1    -- hole --
>           1    0x000000000518c       0x000000000518d       USER_SHADER
>           1    0x000000000518d       0x000000000518e       USER_SHADER
>           1    0x000000000518e       0x000000000518f       USER_SHADER
>           1    0x000000000518f       0x0000000005190       USER_SHADER
>         100    -- hole --
>         120    0x00000000051f4       0x000000000526c       SAMPLER_TEXTURE
>         115    -- hole --
>           1    0x00000000052df       0x00000000052e0       IB2
>         287    -- hole --
>           1    0x00000000053ff       0x0000000005400       USER_SHADER
>          12    -- hole --
>           4    0x000000000540c       0x0000000005410       SAMPLER_TEXTURE
>         281    -- hole --
>         256    0x0000000005529       0x0000000005629       VERTEX_BUFFER
>         256    0x0000000005629       0x0000000005729       INDEX_BUFFER
>         746    -- hole --
>           1    0x0000000005a13       0x0000000005a14       USER_SHADER
>          73    -- hole --
>           1    0x0000000005a5d       0x0000000005a5e       CONST_BUFFER
>         299    -- hole --
>           1    0x0000000005b89       0x0000000005b8a       SAMPLER_TEXTURE
>           6    -- hole --
>        1024    0x0000000005b90       0x0000000005f90       SAMPLER_TEXTURE
>       13312    -- hole --
>        1080    0x0000000009390       0x00000000097c8       SAMPLER_TEXTURE, DEPTH_BUFFER
>        2304    -- hole --
>         512    0x000000000a0c8       0x000000000a2c8       SAMPLER_TEXTURE, COLOR_BUFFER
>         512    0x000000000a2c8       0x000000000a4c8       SAMPLER_TEXTURE, COLOR_BUFFER
>         512    0x000000000a4c8       0x000000000a6c8       SAMPLER_TEXTURE, COLOR_BUFFER
>         512    0x000000000a6c8       0x000000000a8c8       SAMPLER_TEXTURE, COLOR_BUFFER
>         512    0x000000000a8c8       0x000000000aac8       SAMPLER_TEXTURE, COLOR_BUFFER
>         512    0x000000000aac8       0x000000000acc8       SAMPLER_TEXTURE, COLOR_BUFFER
>        1712    -- hole --
>         748    0x000000000b378       0x000000000b664       SAMPLER_TEXTURE
>         748    0x000000000b664       0x000000000b950       SAMPLER_TEXTURE
>         748    -- hole --
>         748    0x000000000bc3c       0x000000000bf28       SAMPLER_TEXTURE, COLOR_BUFFER
>        2248    -- hole --
>         748    0x000000000c7f0       0x000000000cadc       SAMPLER_TEXTURE
>         640    -- hole --
>         480    0x000000000cd5c       0x000000000cf3c       RINGS_STREAMOUT
>         384    0x000000000cf3c       0x000000000d0bc       RINGS_STREAMOUT
>           2    0x000000000d0bc       0x000000000d0be       CP_DMA, CMASK
>           1    -- hole --
>           1    0x000000000d0bf       0x000000000d0c0       USER_SHADER
>        5496    -- hole --
>        1496    0x000000000e638       0x000000000ec10       SAMPLER_TEXTURE
>         481    -- hole --
>           2    0x000000000edf1       0x000000000edf3       CMASK
>         677    -- hole --
>        1496    0x000000000f098       0x000000000f670       SAMPLER_TEXTURE, COLOR_BUFFER
>        1496    -- hole --
>        1496    0x000000000fc48       0x0000000010220       SAMPLER_TEXTURE, COLOR_BUFFER
>        2136    -- hole --
>           2    0x0000000010a78       0x0000000010a7a       SAMPLER_TEXTURE
>         334    -- hole --
>           2    0x0000000010bc8       0x0000000010bca       SAMPLER_TEXTURE
>          14    -- hole --
>           2    0x0000000010bd8       0x0000000010bda       SAMPLER_TEXTURE
>         598    -- hole --
>           3    0x0000000010e30       0x0000000010e33       SAMPLER_TEXTURE
>        6218    -- hole --
>           1    0x000000001267d       0x000000001267e       INDEX_BUFFER
>           1    0x000000001267e       0x000000001267f       VERTEX_BUFFER
>           1    0x000000001267f       0x0000000012680       VERTEX_BUFFER
>         296    -- hole --
>           2    0x00000000127a8       0x00000000127aa       SAMPLER_TEXTURE
>         910    -- hole --
>           1    0x0000000012b38       0x0000000012b39       CONST_BUFFER
>       13210    -- hole --
>           5    0x0000000015ed3       0x0000000015ed8       VERTEX_BUFFER
>           2    -- hole --
>           6    0x0000000015eda       0x0000000015ee0       VERTEX_BUFFER
>           3    -- hole --
>           3    0x0000000015ee3       0x0000000015ee6       INDEX_BUFFER
>           1    0x0000000015ee6       0x0000000015ee7       SAMPLER_TEXTURE
>           1    0x0000000015ee7       0x0000000015ee8       CONST_BUFFER
>       36096    -- hole --
>         128    0x000000001ebe8       0x000000001ec68       SAMPLER_TEXTURE
>         310    -- hole --
>           1    0x000000001ed9e       0x000000001ed9f       USER_SHADER
>           1    0x000000001ed9f       0x000000001eda0       USER_SHADER
>         636    -- hole --
>           1    0x000000001f01c       0x000000001f01d       USER_SHADER
>           2    0x000000001f01d       0x000000001f01f       USER_SHADER
>           1    0x000000001f01f       0x000000001f020       CONST_BUFFER
>          46    -- hole --
>           1    0x000000001f04e       0x000000001f04f       USER_SHADER
>           1    0x000000001f04f       0x000000001f050       USER_SHADER
>           4    -- hole --
>           1    0x000000001f054       0x000000001f055       USER_SHADER
>           1    0x000000001f055       0x000000001f056       USER_SHADER
>           1    0x000000001f056       0x000000001f057       USER_SHADER
>           8    -- hole --
>           1    0x000000001f05f       0x000000001f060       USER_SHADER
>        1552    -- hole --
>           2    0x000000001f670       0x000000001f672       SAMPLER_TEXTURE
>           6    -- hole --
>           2    0x000000001f678       0x000000001f67a       SAMPLER_TEXTURE
>           1    0x000000001f67a       0x000000001f67b       CONST_BUFFER
>         799    -- hole --
>          86    0x000000001f99a       0x000000001f9f0       VERTEX_BUFFER
>          90    -- hole --
>           1    0x000000001fa4a       0x000000001fa4b       CONST_BUFFER
>        2628    -- hole --
>           1    0x000000002048f       0x0000000020490       CONST_BUFFER
>        1892    -- hole --
>           6    0x0000000020bf4       0x0000000020bfa       SAMPLER_TEXTURE
>         233    -- hole --
>          84    0x0000000020ce3       0x0000000020d37       INDEX_BUFFER
>         143    0x0000000020d37       0x0000000020dc6       VERTEX_BUFFER
>        8246    -- hole --
>           1    0x0000000022dfc       0x0000000022dfd       CONST_BUFFER
>          14    -- hole --
>           1    0x0000000022e0b       0x0000000022e0c       CONST_BUFFER
>           1    0x0000000022e0c       0x0000000022e0d       CONST_BUFFER
>           1    0x0000000022e0d       0x0000000022e0e       CONST_BUFFER
>           5    -- hole --
>           1    0x0000000022e13       0x0000000022e14       CONST_BUFFER
>           1    -- hole --
>           1    0x0000000022e15       0x0000000022e16       CONST_BUFFER
>           1    -- hole --
>           1    0x0000000022e17       0x0000000022e18       CONST_BUFFER
>        3021    -- hole --
>           1    0x00000000239e5       0x00000000239e6       CONST_BUFFER
>       17382    -- hole --
>          16    0x0000000027dcc       0x0000000027ddc       SAMPLER_TEXTURE
>         251    -- hole --
>           1    0x0000000027ed7       0x0000000027ed8       CONST_BUFFER
>           1    -- hole --
>           1    0x0000000027ed9       0x0000000027eda       CONST_BUFFER
>           4    -- hole --
>           1    0x0000000027ede       0x0000000027edf       SAMPLER_TEXTURE
>         131    -- hole --
>           1    0x0000000027f62       0x0000000027f63       CONST_BUFFER
>          18    -- hole --
>           1    0x0000000027f75       0x0000000027f76       CONST_BUFFER
>         366    -- hole --
>           2    0x00000000280e4       0x00000000280e6       SAMPLER_TEXTURE
>       19189    -- hole --
>           1    0x000000002cbdb       0x000000002cbdc       CONST_BUFFER
>         359    -- hole --
>           1    0x000000002cd43       0x000000002cd44       CONST_BUFFER
>        1708    -- hole --
>         344    0x000000002d3f0       0x000000002d548       SAMPLER_TEXTURE
>         344    0x000000002d548       0x000000002d6a0       SAMPLER_TEXTURE
>        4776    -- hole --
>           1    0x000000002e948       0x000000002e949       CONST_BUFFER
>           7    -- hole --
>        4096    0x000000002e950       0x000000002f950       SAMPLER_TEXTURE
>        2048    -- hole --
>        4096    0x0000000030150       0x0000000031150       SAMPLER_TEXTURE
>        2048    0x0000000031150       0x0000000031950       SAMPLER_TEXTURE
>        1024    0x0000000031950       0x0000000031d50       SAMPLER_TEXTURE
>       32184    -- hole --
>           6    0x0000000039b08       0x0000000039b0e       SAMPLER_TEXTURE
>       21546    -- hole --
>           2    0x000000003ef38       0x000000003ef3a       SAMPLER_TEXTURE
>           2    -- hole --
>           6    0x000000003ef3c       0x000000003ef42       SAMPLER_TEXTURE
>           4    -- hole --
>           1    0x000000003ef46       0x000000003ef47       CONST_BUFFER
>           1    0x000000003ef47       0x000000003ef48       INDEX_BUFFER
>           1    0x000000003ef48       0x000000003ef49       VERTEX_BUFFER
>           1    0x000000003ef49       0x000000003ef4a       VERTEX_BUFFER
>           1    -- hole --
>           1    0x000000003ef4b       0x000000003ef4c       CONST_BUFFER
>           1    0x000000003ef4c       0x000000003ef4d       INDEX_BUFFER
>           1    0x000000003ef4d       0x000000003ef4e       VERTEX_BUFFER
>           1    0x000000003ef4e       0x000000003ef4f       VERTEX_BUFFER
>           6    -- hole --
>           1    0x000000003ef55       0x000000003ef56       CONST_BUFFER
>           1    -- hole --
>           1    0x000000003ef57       0x000000003ef58       CONST_BUFFER
>        2452    -- hole --
>           6    0x000000003f8ec       0x000000003f8f2       SAMPLER_TEXTURE
>        8634    -- hole --
>           1    0x0000000041aac       0x0000000041aad       CONST_BUFFER
>           2    0x0000000041aad       0x0000000041aaf       USER_SHADER
>           5    0x0000000041aaf       0x0000000041ab4       USER_SHADER
>           1    0x0000000041ab4       0x0000000041ab5       CONST_BUFFER
>           1    0x0000000041ab5       0x0000000041ab6       CONST_BUFFER
>           1    0x0000000041ab6       0x0000000041ab7       CONST_BUFFER
>          29    0x0000000041ab7       0x0000000041ad4       VERTEX_BUFFER
>           1    0x0000000041ad4       0x0000000041ad5       CONST_BUFFER
>           2    0x0000000041ad5       0x0000000041ad7       USER_SHADER
>           4    0x0000000041ad7       0x0000000041adb       USER_SHADER
>           2    0x0000000041adb       0x0000000041add       USER_SHADER
>           1    0x0000000041add       0x0000000041ade       USER_SHADER
>           1    0x0000000041ade       0x0000000041adf       USER_SHADER
>           1    0x0000000041adf       0x0000000041ae0       USER_SHADER
>           1    0x0000000041ae0       0x0000000041ae1       USER_SHADER
>           1    0x0000000041ae1       0x0000000041ae2       USER_SHADER
>          12    -- hole --
>           1    0x0000000041aee       0x0000000041aef       TRACE
>          62    -- hole --
>           1    0x0000000041b2d       0x0000000041b2e       CONST_BUFFER
>       13990    -- hole --
>        3168    0x00000000451d4       0x0000000045e34       SCRATCH_BUFFER
>         748    0x0000000045e34       0x0000000046120       COLOR_BUFFER
>        1315    -- hole --
>           1    0x0000000046643       0x0000000046644       CONST_BUFFER
>         233    -- hole --
>           1    0x000000004672d       0x000000004672e       CONST_BUFFER
>         349    -- hole --
>         256    0x000000004688b       0x000000004698b       CONST_BUFFER, DESCRIPTORS, VERTEX_BUFFER
>          43    -- hole --
>           1    0x00000000469b6       0x00000000469b7       CONST_BUFFER
>         197    -- hole --
>          16    0x0000000046a7c       0x0000000046a8c       VERTEX_BUFFER
>        8320    -- hole --
>         342    0x0000000048b0c       0x0000000048c62       SAMPLER_TEXTURE
>         256    0x0000000048c62       0x0000000048d62       DESCRIPTORS
>       11710    -- hole --
>           7    0x000000004bb20       0x000000004bb27       SAMPLER_TEXTURE
>        2276    -- hole --
>           3    0x000000004c40b       0x000000004c40e       USER_SHADER
>         173    -- hole --
>           3    0x000000004c4bb       0x000000004c4be       USER_SHADER
>         173    -- hole --
>           3    0x000000004c56b       0x000000004c56e       USER_SHADER
>         173    -- hole --
>           3    0x000000004c61b       0x000000004c61e       USER_SHADER
>        1721    -- hole --
>          16    0x000000004ccd7       0x000000004cce7       VERTEX_BUFFER
>       26415    -- hole --
>           2    0x0000000053416       0x0000000053418       USER_SHADER
>          38    -- hole --
>           1    0x000000005343e       0x000000005343f       USER_SHADER
>           1    0x000000005343f       0x0000000053440       USER_SHADER
>          38    -- hole --
>           2    0x0000000053466       0x0000000053468       USER_SHADER
>          38    -- hole --
>           1    0x000000005348e       0x000000005348f       USER_SHADER
>           1    0x000000005348f       0x0000000053490       USER_SHADER
>          38    -- hole --
>           1    0x00000000534b6       0x00000000534b7       USER_SHADER
>           1    0x00000000534b7       0x00000000534b8       USER_SHADER
>         118    -- hole --
>           1    0x000000005352e       0x000000005352f       CONST_BUFFER
>           1    0x000000005352f       0x0000000053530       CONST_BUFFER
>          38    -- hole --
>           1    0x0000000053556       0x0000000053557       CONST_BUFFER
>          79    -- hole --
>           1    0x00000000535a6       0x00000000535a7       CONST_BUFFER
>         360    -- hole --
>           1    0x000000005370f       0x0000000053710       SAMPLER_BUFFER
>         942    -- hole --
>           2    0x0000000053abe       0x0000000053ac0       SAMPLER_BUFFER
>          12    -- hole --
>           1    0x0000000053acc       0x0000000053acd       SAMPLER_BUFFER
>         633    -- hole --
>           1    0x0000000053d46       0x0000000053d47       CONST_BUFFER
>         142    -- hole --
>           2    0x0000000053dd5       0x0000000053dd7       USER_SHADER
>           1    0x0000000053dd7       0x0000000053dd8       USER_SHADER
>           2    0x0000000053dd8       0x0000000053dda       USER_SHADER
>           1    0x0000000053dda       0x0000000053ddb       USER_SHADER
>           3    0x0000000053ddb       0x0000000053dde       USER_SHADER
>           1    -- hole --
>           1    0x0000000053ddf       0x0000000053de0       USER_SHADER
>           6    -- hole --
>           1    0x0000000053de6       0x0000000053de7       CONST_BUFFER
>         129    -- hole --
>           1    0x0000000053e68       0x0000000053e69       CONST_BUFFER
>           1    0x0000000053e69       0x0000000053e6a       CONST_BUFFER
>           1    0x0000000053e6a       0x0000000053e6b       CONST_BUFFER
>           1    0x0000000053e6b       0x0000000053e6c       CONST_BUFFER
>           1    0x0000000053e6c       0x0000000053e6d       CONST_BUFFER
>           1    0x0000000053e6d       0x0000000053e6e       CONST_BUFFER
>           1    0x0000000053e6e       0x0000000053e6f       CONST_BUFFER
>           1    0x0000000053e6f       0x0000000053e70       CONST_BUFFER
>           2    -- hole --
>           1    0x0000000053e72       0x0000000053e73       CONST_BUFFER
>         220    -- hole --
>           1    0x0000000053f4f       0x0000000053f50       SAMPLER_BUFFER
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f (0x42800000)
>        [1;33mVGT_HOS_MIN_TESS_LEVEL[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128 (0x80)
>        [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64 (0x40)
>        [1;33mVGT_GS_PER_VS[0m <- GS_PER_VS = 2
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_RESET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>        [1;33mVGT_VTX_CNT_EN[0m <- VTX_CNT_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                     DISTANCE_1 = 1
>                                     DISTANCE_2 = 2
>                                     DISTANCE_3 = 3
>                                     DISTANCE_4 = 4
>                                     DISTANCE_5 = 5
>                                     DISTANCE_6 = 6
>                                     DISTANCE_7 = 7
>        [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 8
>                                     DISTANCE_9 = 9
>                                     DISTANCE_10 = 10 (0xa)
>                                     DISTANCE_11 = 11 (0xb)
>                                     DISTANCE_12 = 12 (0xc)
>                                     DISTANCE_13 = 13 (0xd)
>                                     DISTANCE_14 = 14 (0xe)
>                                     DISTANCE_15 = 15 (0xf)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_PRIM_FILTER_CNTL[0m <- TRIANGLE_FILTER_DISABLE = 0
>                                  LINE_FILTER_DISABLE = 0
>                                  POINT_FILTER_DISABLE = 0
>                                  RECTANGLE_FILTER_DISABLE = 0
>                                  TRIANGLE_EXPAND_ENA = 0
>                                  LINE_EXPAND_ENA = 0
>                                  POINT_EXPAND_ENA = 0
>                                  RECTANGLE_EXPAND_ENA = 0
>                                  PRIM_EXPAND_CONSTANT = 0
>                                  XMAX_RIGHT_EXCLUSION = 0
>                                  YMAX_BOTTOM_EXCLUSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_1[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_1[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_2[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_2[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_3[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_3[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_4[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_4[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_5[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_5[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_6[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_6[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_7[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_7[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_8[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_8[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_9[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_9[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_10[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_10[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_11[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_11[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_12[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_12[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_13[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_13[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_14[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_14[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_15[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_15[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
>                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
>                               RB_XSEL = 0
>                               RB_YSEL = 0
>                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                               SC_MAP = RASTER_CONFIG_SC_MAP_0
>                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                               SE_MAP = RASTER_CONFIG_SE_MAP_2
>                               SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
>                               SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
>        [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_0
>                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE
>                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>                                   WINDOW_OFFSET_DISABLE = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_GENERIC_SCISSOR_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_GENERIC_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                    BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_SCREEN_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>        [1;33mPA_SC_SCREEN_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                   BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CLIPRECT_RULE[0m <- CLIP_RULE = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_EDGERULE[0m <- ER_TRI = 10 (0xa)
>                          ER_POINT = 10 (0xa)
>                          ER_RECT = 10 (0xa)
>                          ER_LINE_LR = 42 (0x2a)
>                          ER_LINE_RL = 42 (0x2a)
>                          ER_LINE_TB = 10 (0xa)
>                          ER_LINE_BT = 10 (0xa)
>        [1;33mPA_SU_HARDWARE_SCREEN_OFFSET[0m <- HW_SCREEN_OFFSET_X = 0
>                                        HW_SCREEN_OFFSET_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_NANINF_CNTL[0m <- VTE_XY_INF_DISCARD = 0
>                             VTE_Z_INF_DISCARD = 0
>                             VTE_W_INF_DISCARD = 0
>                             VTE_0XNANINF_IS_0 = 0
>                             VTE_XY_NAN_RETAIN = 0
>                             VTE_Z_NAN_RETAIN = 0
>                             VTE_W_NAN_RETAIN = 0
>                             VTE_W_RECIP_NAN_IS_0 = 0
>                             VS_XY_NAN_TO_INF = 0
>                             VS_XY_INF_RETAIN = 0
>                             VS_Z_NAN_TO_INF = 0
>                             VS_Z_INF_RETAIN = 0
>                             VS_W_NAN_TO_INF = 0
>                             VS_W_INF_RETAIN = 0
>                             VS_CLIP_DIST_INF_DISCARD = 0
>                             VTE_NO_OUTPUT_NEG_0 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f (0x3f800000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SRESULTS_COMPARE_STATE0[0m <- COMPAREFUNC0 = REF_NEVER
>                                      COMPAREVALUE0 = 0
>                                      COMPAREMASK0 = 0
>                                      ENABLE0 = 0
>        [1;33mDB_SRESULTS_COMPARE_STATE1[0m <- COMPAREFUNC1 = REF_NEVER
>                                      COMPAREVALUE1 = 0
>                                      COMPAREMASK1 = 0
>                                      ENABLE1 = 0
>        [1;33mDB_PRELOAD_CONTROL[0m <- START_X = 0
>                              START_Y = 0
>                              MAX_X = 0
>                              MAX_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE[0m <- FORCE_HIZ_ENABLE = FORCE_OFF
>                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
>                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
>                              FORCE_SHADER_Z_ORDER = 0
>                              FAST_Z_DISABLE = 0
>                              FAST_STENCIL_DISABLE = 0
>                              NOOP_CULL_DISABLE = 0
>                              FORCE_COLOR_KILL = 0
>                              FORCE_Z_READ = 0
>                              FORCE_STENCIL_READ = 0
>                              FORCE_FULL_Z_RANGE = FORCE_OFF
>                              FORCE_QC_SMASK_CONFLICT = 0
>                              DISABLE_VIEWPORT_CLAMP = 0
>                              IGNORE_SC_ZRANGE = 0
>                              DISABLE_FULLY_COVERED = 0
>                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
>                              MAX_TILES_IN_DTT = 0
>                              DISABLE_TILE_RATE_TILES = 0
>                              FORCE_Z_DIRTY = 0
>                              FORCE_STENCIL_DIRTY = 0
>                              FORCE_Z_VALID = 0
>                              FORCE_STENCIL_VALID = 0
>                              PRESERVE_COMPRESSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>        [1;33mVGT_MIN_VTX_INDX[0m <- 0
>        [1;33mVGT_INDX_OFFSET[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0xfffc
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0xfffe
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>        [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mTA_BC_BASE_ADDR[0m <- 0x00008710
>        [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = VGT_FLUSH
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>------------------- IB2: Init config end -------------------
>
>------------------ IB2: Init GS rings begin ------------------
>[1;36mSET_UCONFIG_REG[1;36m:
>        [1;33mVGT_ESGS_RING_SIZE[0m <- 7680 (0x00001e00)
>        [1;33mVGT_GSVS_RING_SIZE[0m <- 6144 (0x00001800)
>------------------- IB2: Init GS rings end -------------------
>
>------------------ IB begin ------------------
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000001
>[1;32mNOP[0m:
>        [31mTrace point ID: 1
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDIRECT_BUFFER_CIK[0m:
>        0x052df000
>        0x00000000
>        0x00000088
>[1;36mSET_UCONFIG_REG[1;36m:
>        [1;33mVGT_ESGS_RING_SIZE[0m <- 7680 (0x00001e00)
>        [1;33mVGT_GSVS_RING_SIZE[0m <- 6144 (0x00001800)
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                              STREAMOUT_1_EN = 0
>                              STREAMOUT_2_EN = 0
>                              STREAMOUT_3_EN = 0
>                              RAST_STREAM = 0
>                              RAST_STREAM_MASK = 0
>                              USE_RAST_STREAM_MASK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000a6c80
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 7
>                           FMASK_TILE_MAX = 7
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 63 (0x3f)
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000a6c80
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000a6c80
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_BASE[0m <- 0x000a4c80
>        [1;33mCB_COLOR1_PITCH[0m <- TILE_MAX = 7
>                           FMASK_TILE_MAX = 7
>        [1;33mCB_COLOR1_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR1_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 63 (0x3f)
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR1_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR1_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR1_CMASK[0m <- 0x000a4c80
>        [1;33mCB_COLOR1_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR1_FMASK[0m <- 0x000a4c80
>        [1;33mCB_COLOR1_FMASK_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR1_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR1_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR2_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR3_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR4_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR5_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR6_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR7_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_INVALID
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 0
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 0
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_INVALID
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 64 (0x040)
>                                   BR_Y = 64 (0x040)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_LINE_CNTL[0m <- EXPAND_LINE_WIDTH = 0
>                           LAST_PIXEL = 1
>                           PERPENDICULAR_ENDCAP_ENA = 0
>                           DX10_DIAMOND_TEST_ENA = 0
>        [1;33mPA_SC_AA_CONFIG[0m <- MSAA_NUM_SAMPLES = 0
>                           AA_MASK_CENTROID_DTMN = 0
>                           MAX_SAMPLE_DIST = 0
>                           MSAA_EXPOSED_SAMPLES = 0
>                           DETAIL_TO_EXPOSED_MODE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                   PS_ITER_SAMPLES = 0
>                   MASK_EXPORT_NUM_SAMPLES = 0
>                   ALPHA_TO_MASK_NUM_SAMPLES = 0
>                   HIGH_QUALITY_INTERSECTIONS = 1
>                   INCOHERENT_EQAA_READS = 0
>                   INTERPOLATE_COMP_Z = 0
>                   INTERPOLATE_SRC_Z = 0
>                   STATIC_ANCHOR_ASSOCIATIONS = 1
>                   ALPHA_TO_MASK_EQAA_DISABLE = 0
>                   OVERRASTERIZATION_AMOUNT = 0
>                   ENABLE_POSTZ_OVERRASTERIZATION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                             WALK_ALIGNMENT = 0
>                             WALK_ALIGN8_PRIM_FITS_ST = 0
>                             WALK_FENCE_ENABLE = 0
>                             WALK_FENCE_SIZE = 0
>                             SUPERTILE_WALK_ORDER_ENABLE = 0
>                             TILE_WALK_ORDER_ENABLE = 0
>                             TILE_COVER_DISABLE = 0
>                             TILE_COVER_NO_SCISSOR = 0
>                             ZMM_LINE_EXTENT = 0
>                             ZMM_LINE_OFFSET = 0
>                             ZMM_RECT_EXTENT = 0
>                             KILL_PIX_POST_HI_Z = 0
>                             KILL_PIX_POST_DETAIL_MASK = 0
>                             PS_ITER_SAMPLE = 0
>                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
>                             MULTI_GPU_SUPERTILE_ENABLE = 0
>                             GPU_ID_OVERRIDE_ENABLE = 0
>                             GPU_ID_OVERRIDE = 0
>                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                             FORCE_EOV_CNTDWN_ENABLE = 1
>                             FORCE_EOV_REZ_ENABLE = 1
>                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                             OUT_OF_ORDER_WATER_MARK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                   AA_MASK_X1Y0 = 0xffff
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                   AA_MASK_X1Y1 = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 7
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND_RED[0m <- 0
>        [1;33mCB_BLEND_GREEN[0m <- 0
>        [1;33mCB_BLEND_BLUE[0m <- 0
>        [1;33mCB_BLEND_ALPHA[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 1
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 1
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_UCP_0_X[0m <- 0
>        [1;33mPA_CL_UCP_0_Y[0m <- 0
>        [1;33mPA_CL_UCP_0_Z[0m <- 0
>        [1;33mPA_CL_UCP_0_W[0m <- 0
>        [1;33mPA_CL_UCP_1_X[0m <- 0
>        [1;33mPA_CL_UCP_1_Y[0m <- 0
>        [1;33mPA_CL_UCP_1_Z[0m <- 0
>        [1;33mPA_CL_UCP_1_W[0m <- 0
>        [1;33mPA_CL_UCP_2_X[0m <- 0
>        [1;33mPA_CL_UCP_2_Y[0m <- 0
>        [1;33mPA_CL_UCP_2_Z[0m <- 0
>        [1;33mPA_CL_UCP_2_W[0m <- 0
>        [1;33mPA_CL_UCP_3_X[0m <- 0
>        [1;33mPA_CL_UCP_3_Y[0m <- 0
>        [1;33mPA_CL_UCP_3_Z[0m <- 0
>        [1;33mPA_CL_UCP_3_W[0m <- 0
>        [1;33mPA_CL_UCP_4_X[0m <- 0
>        [1;33mPA_CL_UCP_4_Y[0m <- 0
>        [1;33mPA_CL_UCP_4_Z[0m <- 0
>        [1;33mPA_CL_UCP_4_W[0m <- 0
>        [1;33mPA_CL_UCP_5_X[0m <- 0
>        [1;33mPA_CL_UCP_5_Y[0m <- 0
>        [1;33mPA_CL_UCP_5_Z[0m <- 0
>        [1;33mPA_CL_UCP_5_W[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18594.0f (0x46914400)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18582.5f (0x46912d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_0[0m <- 18582.5f (0x46912d00)
>        [1;33mSPI_SHADER_USER_DATA_ES_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_0[0m <- 18582.5f (0x46912d00)
>        [1;33mSPI_SHADER_USER_DATA_ES_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_2[0m <- 18594.0f (0x46914400)
>        [1;33mSPI_SHADER_USER_DATA_ES_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_6[0m <- 0x48cac200
>        [1;33mSPI_SHADER_USER_DATA_ES_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_4[0m <- 0x48cac700
>        [1;33mSPI_SHADER_USER_DATA_ES_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x04988d00
>        [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18595.0f (0x46914600)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18587.0f (0x46913600)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18589.5f (0x46913b00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 18591.5f (0x46913f00)
>        [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18596.0f (0x46914800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_6[0m <- 0x04989800
>        [1;33mSPI_SHADER_USER_DATA_GS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_4[0m <- 0x04989d00
>        [1;33mSPI_SHADER_USER_DATA_GS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x0498a100
>        [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0x049b0300
>        [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_6[0m <- 0x0498a200
>        [1;33mSPI_SHADER_USER_DATA_HS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_4[0m <- 0x0498a700
>        [1;33mSPI_SHADER_USER_DATA_HS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_8[0m <- 18597.0f (0x46914a00)
>        [1;33mSPI_SHADER_USER_DATA_ES_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 64 (0x040)
>                                    BR_Y = 64 (0x040)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_ESGS_RING_ITEMSIZE[0m <- ITEMSIZE = 20 (0x014)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_ES[0m <- 0x001f05f0
>        [1;33mSPI_SHADER_PGM_HI_ES[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_ES[0m <- VGPRS = 2
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_ES[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12 (0xc)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   EXCP_EN = 0
>                                   LDS_SIZE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_SCENARIO_G
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_128
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 1
>                       GS_WRITE_OPTIMIZE = 1
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GSVS_RING_OFFSET_1[0m <- OFFSET = 48 (0x030)
>        [1;33mVGT_GSVS_RING_OFFSET_2[0m <- OFFSET = 48 (0x030)
>        [1;33mVGT_GSVS_RING_OFFSET_3[0m <- OFFSET = 48 (0x030)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GSVS_RING_ITEMSIZE[0m <- ITEMSIZE = 48 (0x030)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MAX_VERT_OUT[0m <- MAX_VERT_OUT = 3
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_VERT_ITEMSIZE[0m <- ITEMSIZE = 16 (0x010)
>        [1;33mVGT_GS_VERT_ITEMSIZE_1[0m <- ITEMSIZE = 0
>        [1;33mVGT_GS_VERT_ITEMSIZE_2[0m <- ITEMSIZE = 0
>        [1;33mVGT_GS_VERT_ITEMSIZE_3[0m <- ITEMSIZE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_INSTANCE_CNT[0m <- ENABLE = 1
>                               CNT = 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_GS[0m <- 0x001f0540
>        [1;33mSPI_SHADER_PGM_HI_GS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_GS[0m <- VGPRS = 7
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_GS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 8
>                                   TRAP_PRESENT = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                HS_EN = 0
>                                ES_EN = ES_STAGE_REAL
>                                GS_EN = 1
>                                VS_EN = VS_STAGE_COPY_SHADER
>                                DYNAMIC_HS = 0
>                                DISPATCH_DRAW_EN = 0
>                                DIS_DEALLOC_ACCUM_0 = 0
>                                DIS_DEALLOC_ACCUM_1 = 0
>                                VS_WAVE_ID_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x001f0550
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 0
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 0
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 4
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 15 (0xf)
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x001f0560
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 3
>                                   SGPRS = 5
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 384 (0x180)
>                            WAVESIZE = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRISTRIP
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 63 (0x003f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_OUT_PRIM_TYPE[0m <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
>                                OUTPRIM_TYPE_1 = 0
>                                OUTPRIM_TYPE_2 = 0
>                                OUTPRIM_TYPE_3 = 0
>                                UNIQUE_TYPE_PER_STREAM = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 64 (0x00000040)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_ES_11[0m <- 0
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000002
>[1;32mNOP[0m:
>        [31mTrace point ID: 2
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000a2c80
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 7
>                           FMASK_TILE_MAX = 7
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 63 (0x3f)
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000a2c80
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000a2c80
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_BASE[0m <- 0x000a0c80
>        [1;33mCB_COLOR1_PITCH[0m <- TILE_MAX = 7
>                           FMASK_TILE_MAX = 7
>        [1;33mCB_COLOR1_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR1_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 63 (0x3f)
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR1_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR1_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR1_CMASK[0m <- 0x000a0c80
>        [1;33mCB_COLOR1_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR1_FMASK[0m <- 0x000a0c80
>        [1;33mCB_COLOR1_FMASK_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR1_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR1_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 64 (0x040)
>                                   BR_Y = 64 (0x040)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 15 (0xf)
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 1
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 1
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18599.0f (0x46914e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_2[0m <- 18599.0f (0x46914e00)
>        [1;33mSPI_SHADER_USER_DATA_ES_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18600.0f (0x46915000)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18601.0f (0x46915200)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18603.5f (0x46915700)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18604.5f (0x46915900)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_8[0m <- 18605.5f (0x46915b00)
>        [1;33mSPI_SHADER_USER_DATA_ES_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_1[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_1[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_2[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_2[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_3[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_3[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_4[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_4[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_5[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_5[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_6[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_6[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_7[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_7[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_8[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_8[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_9[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_9[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_10[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_10[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_11[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_11[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_12[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_12[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_13[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_13[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_14[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_14[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_15[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_15[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_ESGS_RING_ITEMSIZE[0m <- ITEMSIZE = 20 (0x014)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_ES[0m <- 0x00051880
>        [1;33mSPI_SHADER_PGM_HI_ES[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_ES[0m <- VGPRS = 2
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_ES[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 12 (0xc)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   EXCP_EN = 0
>                                   LDS_SIZE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_SCENARIO_G
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_128
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 1
>                       GS_WRITE_OPTIMIZE = 1
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GSVS_RING_OFFSET_1[0m <- OFFSET = 48 (0x030)
>        [1;33mVGT_GSVS_RING_OFFSET_2[0m <- OFFSET = 48 (0x030)
>        [1;33mVGT_GSVS_RING_OFFSET_3[0m <- OFFSET = 48 (0x030)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GSVS_RING_ITEMSIZE[0m <- ITEMSIZE = 48 (0x030)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MAX_VERT_OUT[0m <- MAX_VERT_OUT = 3
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_VERT_ITEMSIZE[0m <- ITEMSIZE = 16 (0x010)
>        [1;33mVGT_GS_VERT_ITEMSIZE_1[0m <- ITEMSIZE = 0
>        [1;33mVGT_GS_VERT_ITEMSIZE_2[0m <- ITEMSIZE = 0
>        [1;33mVGT_GS_VERT_ITEMSIZE_3[0m <- ITEMSIZE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_INSTANCE_CNT[0m <- ENABLE = 1
>                               CNT = 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_GS[0m <- 0x00051890
>        [1;33mSPI_SHADER_PGM_HI_GS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_GS[0m <- VGPRS = 7
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_GS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 8
>                                   TRAP_PRESENT = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x000518a0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 0
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 0
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 4
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 15 (0xf)
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00008810
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 16 (0x10)
>                                   SGPRS = 3
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 64 (0x00000040)
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000003
>[1;32mNOP[0m:
>        [31mTrace point ID: 3
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000aac80
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 7
>                           FMASK_TILE_MAX = 7
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 63 (0x3f)
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000aac80
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000aac80
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_BASE[0m <- 0x000a8c80
>        [1;33mCB_COLOR1_PITCH[0m <- TILE_MAX = 7
>                           FMASK_TILE_MAX = 7
>        [1;33mCB_COLOR1_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR1_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 63 (0x3f)
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR1_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR1_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR1_CMASK[0m <- 0x000a8c80
>        [1;33mCB_COLOR1_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR1_FMASK[0m <- 0x000a8c80
>        [1;33mCB_COLOR1_FMASK_SLICE[0m <- TILE_MAX = 63 (0x0003f)
>        [1;33mCB_COLOR1_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR1_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 64 (0x040)
>                                   BR_Y = 64 (0x040)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 15 (0xf)
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18607.5f (0x46915f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_2[0m <- 18607.5f (0x46915f00)
>        [1;33mSPI_SHADER_USER_DATA_ES_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18608.5f (0x46916100)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18609.5f (0x46916300)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18612.0f (0x46916800)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18613.0f (0x46916a00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_1[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_1[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_1[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_2[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_2[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_2[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_3[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_3[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_3[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_4[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_4[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_4[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_5[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_5[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_5[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_6[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_6[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_6[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_7[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_7[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_7[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_8[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_8[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_8[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_9[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_9[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_9[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_10[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_10[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_10[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_11[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_11[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_11[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_12[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_12[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_12[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_13[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_13[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_13[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_14[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_14[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_14[0m <- 0
>        [1;33mPA_CL_VPORT_XSCALE_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_XOFFSET_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YSCALE_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_YOFFSET_15[0m <- 32.0f (0x42000000)
>        [1;33mPA_CL_VPORT_ZSCALE_15[0m <- 0
>        [1;33mPA_CL_VPORT_ZOFFSET_15[0m <- 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 64 (0x00000040)
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000004
>[1;32mNOP[0m:
>        [31mTrace point ID: 4
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000fc480
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000edf10
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000fc480
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 7
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18582.5f (0x46912d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18615.0f (0x46916e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 0x48cac200
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0x48cac700
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18616.0f (0x46917000)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18617.0f (0x46917200)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18619.5f (0x46917700)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18620.5f (0x46917900)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18621.5f (0x46917b00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 1080 (0x438)
>                                    BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ONE
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                HS_EN = 0
>                                ES_EN = ES_STAGE_OFF
>                                GS_EN = 0
>                                VS_EN = VS_STAGE_REAL
>                                DYNAMIC_HS = 0
>                                DISPATCH_DRAW_EN = 0
>                                DIS_DEALLOC_ACCUM_0 = 0
>                                DIS_DEALLOC_ACCUM_1 = 0
>                                VS_WAVE_ID_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x000518d0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000518e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 10 (0xa)
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9
>        [1;33mVGT_DMA_BASE[0m <- 0x00b03000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000005
>[1;32mNOP[0m:
>        [31mTrace point ID: 5
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mDMA_DATA[0m:
>        [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                          SRC_SEL = DATA
>                          DSL_SEL = DST_ADDR
>                          ENGINE = ME
>        [1;33mSRC_ADDR_LO[0m <- 0
>        [1;33mSRC_ADDR_HI[0m <- 0
>        [1;33mDST_ADDR_LO[0m <- 0x0d0bc000
>        [1;33mDST_ADDR_HI[0m <- 0
>        [1;33mCOMMAND[0m <- BYTE_COUNT = 8192 (0x02000)
>                   DISABLE_WR_CONFIRM = 0
>                   SRC_SWAP = NONE
>                   DST_SWAP = NONE
>                   SAS = MEMORY
>                   DAS = MEMORY
>                   SAIC = INCREMENT
>                   DAIC = INCREMENT
>                   RAW_WAIT = 1
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18625.0f (0x46918200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18624.0f (0x46918000)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18625.5f (0x46918300)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18626.5f (0x46918500)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18629.0f (0x46918a00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18630.0f (0x46918c00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18631.0f (0x46918e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000006
>[1;32mNOP[0m:
>        [31mTrace point ID: 6
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000fc480
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000edf10
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000fc480
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_INVALID
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 0
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 0
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_INVALID
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                   AA_MASK_X1Y0 = 0xffff
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                   AA_MASK_X1Y1 = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18632.0f (0x46919000)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18632.5f (0x46919100)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_ELIMINATE_FAST_CLEAR
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000518c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000007
>[1;32mNOP[0m:
>        [31mTrace point ID: 7
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18633.0f (0x46919200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18633.5f (0x46919300)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x000d0bf0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000518f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 7
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3
>        [1;33mVGT_DMA_BASE[0m <- 0x00b0300c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000008
>[1;32mNOP[0m:
>        [31mTrace point ID: 8
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_INVALID
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 0
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 0
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_INVALID
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                   AA_MASK_X1Y0 = 0xffff
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                   AA_MASK_X1Y1 = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18636.5f (0x46919900)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18635.5f (0x46919700)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18637.0f (0x46919a00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18638.0f (0x46919c00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18640.5f (0x4691a100)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18641.5f (0x4691a300)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18642.5f (0x4691a500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_ELIMINATE_FAST_CLEAR
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000518c0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000009
>[1;32mNOP[0m:
>        [31mTrace point ID: 9
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000fc480
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000edf10
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000fc480
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18643.0f (0x4691a600)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18643.5f (0x4691a700)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ONE
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x001f04e0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x001f04f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 7
>                                   SGPRS = 5
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 9
>        [1;33mVGT_DMA_BASE[0m <- 0x00b03000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000000a
>[1;32mNOP[0m:
>        [31mTrace point ID: 10
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18646.5f (0x4691ad00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18645.5f (0x4691ab00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18647.0f (0x4691ae00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18648.0f (0x4691b000)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18650.5f (0x4691b500)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18651.5f (0x4691b700)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18652.5f (0x4691b900)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000000b
>[1;32mNOP[0m:
>        [31mTrace point ID: 11
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000fc480
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000edf10
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000fc480
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 7
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18653.0f (0x4691ba00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18653.5f (0x4691bb00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ONE
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 1
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x001f01c0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 2
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x001f01d0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 21 (0x15)
>                                   SGPRS = 6
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x0005e280
>        [1;33mVGT_DMA_BASE[0m <- 0x0566cb00
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000000c
>[1;32mNOP[0m:
>        [31mTrace point ID: 12
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000bc3c0
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000bc3c0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000bc3c0
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18655.0f (0x4691be00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18656.0f (0x4691c000)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18657.0f (0x4691c200)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18659.5f (0x4691c700)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18660.5f (0x4691c900)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18661.5f (0x4691cb00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE_1[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_1[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_1[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_1[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_1[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_1[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_2[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_2[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_2[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_2[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_2[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_2[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_3[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_3[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_3[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_3[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_3[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_3[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_4[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_4[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_4[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_4[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_4[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_4[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_5[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_5[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_5[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_5[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_5[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_5[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_6[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_6[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_6[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_6[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_6[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_6[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_7[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_7[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_7[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_7[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_7[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_7[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_8[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_8[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_8[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_8[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_8[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_8[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_9[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_9[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_9[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_9[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_9[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_9[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_10[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_10[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_10[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_10[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_10[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_10[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_11[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_11[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_11[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_11[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_11[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_11[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_12[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_12[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_12[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_12[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_12[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_12[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_13[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_13[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_13[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_13[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_13[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_13[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_14[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_14[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_14[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_14[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_14[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_14[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_15[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_15[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_15[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_15[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_15[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_15[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x001ed9e0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 1
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x001ed9f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3
>        [1;33mVGT_DMA_BASE[0m <- 0x00b0300c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000000d
>[1;32mNOP[0m:
>        [31mTrace point ID: 13
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18665.0f (0x4691d200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18664.0f (0x4691d000)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18665.5f (0x4691d300)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18668.0f (0x4691d800)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18669.0f (0x4691da00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18670.0f (0x4691dc00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18672.5f (0x4691e100)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18673.5f (0x4691e300)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18674.5f (0x4691e500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000000e
>[1;32mNOP[0m:
>        [31mTrace point ID: 14
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000fc480
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000edf10
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000fc480
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18675.0f (0x4691e600)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18675.5f (0x4691e700)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 1
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0041aad0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 27 (0x1b)
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0041aaf0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 41 (0x29)
>                                   SGPRS = 12 (0xc)
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 1
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00029fac
>        [1;33mVGT_DMA_BASE[0m <- 0x20ce3000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 0x00029fac
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000000f
>[1;32mNOP[0m:
>        [31mTrace point ID: 15
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000bc3c0
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000bc3c0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000bc3c0
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18677.0f (0x4691ea00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18678.0f (0x4691ec00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18679.0f (0x4691ee00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18681.5f (0x4691f300)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18682.5f (0x4691f500)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18683.5f (0x4691f700)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE_1[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_1[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_1[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_1[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_1[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_1[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_2[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_2[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_2[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_2[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_2[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_2[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_3[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_3[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_3[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_3[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_3[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_3[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_4[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_4[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_4[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_4[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_4[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_4[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_5[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_5[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_5[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_5[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_5[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_5[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_6[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_6[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_6[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_6[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_6[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_6[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_7[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_7[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_7[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_7[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_7[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_7[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_8[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_8[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_8[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_8[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_8[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_8[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_9[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_9[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_9[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_9[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_9[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_9[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_10[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_10[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_10[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_10[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_10[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_10[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_11[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_11[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_11[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_11[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_11[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_11[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_12[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_12[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_12[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_12[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_12[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_12[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_13[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_13[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_13[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_13[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_13[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_13[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_14[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_14[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_14[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_14[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_14[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_14[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_XSCALE_15[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET_15[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE_15[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET_15[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE_15[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET_15[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x001ed9e0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 1
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x001ed9f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 3
>        [1;33mVGT_DMA_BASE[0m <- 0x00b0300c
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000010
>[1;32mNOP[0m:
>        [31mTrace point ID: 16
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18687.0f (0x4691fe00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18686.0f (0x4691fc00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18687.5f (0x4691ff00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18688.5f (0x46920100)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18689.5f (0x46920300)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18692.0f (0x46920800)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18693.0f (0x46920a00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18694.0f (0x46920c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000011
>[1;32mNOP[0m:
>        [31mTrace point ID: 17
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000fc480
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000edf10
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000fc480
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18694.5f (0x46920d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18695.0f (0x46920e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_5[0m <- OFFSET = 5
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 5
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0041ad50
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 27 (0x1b)
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 6
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0041ad70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 41 (0x29)
>                                   SGPRS = 12 (0xc)
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 1
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00029fac
>        [1;33mVGT_DMA_BASE[0m <- 0x20ce3000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 0x00029fac
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000012
>[1;32mNOP[0m:
>        [31mTrace point ID: 18
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mDMA_DATA[0m:
>        [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                          SRC_SEL = DATA
>                          DSL_SEL = DST_ADDR
>                          ENGINE = ME
>        [1;33mSRC_ADDR_LO[0m <- 0
>        [1;33mSRC_ADDR_HI[0m <- 0
>        [1;33mDST_ADDR_LO[0m <- 0x0d0bc000
>        [1;33mDST_ADDR_HI[0m <- 0
>        [1;33mCOMMAND[0m <- BYTE_COUNT = 8192 (0x02000)
>                   DISABLE_WR_CONFIRM = 0
>                   SRC_SWAP = NONE
>                   DST_SWAP = NONE
>                   SAS = MEMORY
>                   DAS = MEMORY
>                   SAIC = INCREMENT
>                   DAIC = INCREMENT
>                   RAW_WAIT = 1
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18700.0f (0x46921800)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18699.0f (0x46921600)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18700.5f (0x46921900)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18701.5f (0x46921b00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18702.5f (0x46921d00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18705.0f (0x46922200)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18706.0f (0x46922400)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18707.0f (0x46922600)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000013
>[1;32mNOP[0m:
>        [31mTrace point ID: 19
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18707.5f (0x46922700)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18708.0f (0x46922800)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c61b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00534b60
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 27 (0x0000001b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000014
>[1;32mNOP[0m:
>        [31mTrace point ID: 20
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18711.5f (0x46922f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18710.5f (0x46922d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18712.0f (0x46923000)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18713.0f (0x46923200)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18714.0f (0x46923400)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18715.0f (0x46923600)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18716.0f (0x46923800)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000015
>[1;32mNOP[0m:
>        [31mTrace point ID: 21
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18716.5f (0x46923900)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18717.0f (0x46923a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c56b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00534b70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 27 (0x0000001b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000016
>[1;32mNOP[0m:
>        [31mTrace point ID: 22
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18720.5f (0x46924100)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18719.5f (0x46923f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18721.0f (0x46924200)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18722.0f (0x46924400)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18723.0f (0x46924600)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18724.0f (0x46924800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18725.0f (0x46924a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000017
>[1;32mNOP[0m:
>        [31mTrace point ID: 23
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18725.5f (0x46924b00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18726.0f (0x46924c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c61b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00534b60
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 27 (0x0000001b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000018
>[1;32mNOP[0m:
>        [31mTrace point ID: 24
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18729.5f (0x46925300)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18728.5f (0x46925100)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18730.0f (0x46925400)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18731.0f (0x46925600)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18732.0f (0x46925800)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18733.0f (0x46925a00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18734.0f (0x46925c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000019
>[1;32mNOP[0m:
>        [31mTrace point ID: 25
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18734.5f (0x46925d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18735.0f (0x46925e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c56b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00534b70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 27 (0x0000001b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000001a
>[1;32mNOP[0m:
>        [31mTrace point ID: 26
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18738.5f (0x46926500)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18737.5f (0x46926300)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18739.0f (0x46926600)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18740.0f (0x46926800)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18741.0f (0x46926a00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18743.5f (0x46926f00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18744.5f (0x46927100)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18745.5f (0x46927300)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000001b
>[1;32mNOP[0m:
>        [31mTrace point ID: 27
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18746.0f (0x46927400)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18746.5f (0x46927500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c4bb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 26 (0x1a)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005348e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000001c
>[1;32mNOP[0m:
>        [31mTrace point ID: 28
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18750.0f (0x46927c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18749.0f (0x46927a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18750.5f (0x46927d00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18751.5f (0x46927f00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18752.5f (0x46928100)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000001d
>[1;32mNOP[0m:
>        [31mTrace point ID: 29
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18753.0f (0x46928200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18753.5f (0x46928300)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c4bb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 26 (0x1a)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005348e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 11 (0x0000000b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000001e
>[1;32mNOP[0m:
>        [31mTrace point ID: 30
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18757.0f (0x46928a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18756.0f (0x46928800)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18757.5f (0x46928b00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18758.5f (0x46928d00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18759.5f (0x46928f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000001f
>[1;32mNOP[0m:
>        [31mTrace point ID: 31
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18760.0f (0x46929000)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18760.5f (0x46929100)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c4bb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 26 (0x1a)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005348e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 9
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000020
>[1;32mNOP[0m:
>        [31mTrace point ID: 32
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18764.0f (0x46929800)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18763.0f (0x46929600)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18764.5f (0x46929900)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18765.5f (0x46929b00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18766.5f (0x46929d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000021
>[1;32mNOP[0m:
>        [31mTrace point ID: 33
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18767.0f (0x46929e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18767.5f (0x46929f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c4bb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 26 (0x1a)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005348e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 11 (0x0000000b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000022
>[1;32mNOP[0m:
>        [31mTrace point ID: 34
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18769.5f (0x4692a300)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18770.5f (0x4692a500)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18773.0f (0x4692aa00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18774.0f (0x4692ac00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18775.0f (0x4692ae00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18777.5f (0x4692b300)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18778.5f (0x4692b500)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18779.5f (0x4692b700)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 1
>                             STENCILMASK = 255 (0xff)
>                             STENCILWRITEMASK = 255 (0xff)
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 1
>                                STENCILMASK_BF = 255 (0xff)
>                                STENCILWRITEMASK_BF = 255 (0xff)
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 1
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_ALWAYS
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_REPLACE_TEST
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c40b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 26 (0x1a)
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005348f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 2
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 6
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 96 (0x00000060)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000023
>[1;32mNOP[0m:
>        [31mTrace point ID: 35
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18781.5f (0x4692bb00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18782.5f (0x4692bd00)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18785.0f (0x4692c200)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18786.0f (0x4692c400)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18787.0f (0x4692c600)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18788.0f (0x4692c800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 96 (0x00000060)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000024
>[1;32mNOP[0m:
>        [31mTrace point ID: 36
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18790.5f (0x4692cd00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18791.5f (0x4692cf00)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18794.0f (0x4692d400)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18795.0f (0x4692d600)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18796.0f (0x4692d800)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18797.0f (0x4692da00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 27 (0x0000001b)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 96 (0x00000060)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000025
>[1;32mNOP[0m:
>        [31mTrace point ID: 37
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18801.0f (0x4692e200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18800.0f (0x4692e000)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18801.5f (0x4692e300)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18804.0f (0x4692e800)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18805.0f (0x4692ea00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18806.0f (0x4692ec00)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18808.5f (0x4692f100)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18809.5f (0x4692f300)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18810.5f (0x4692f500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000026
>[1;32mNOP[0m:
>        [31mTrace point ID: 38
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18811.0f (0x4692f600)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18811.5f (0x4692f700)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534660
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000027
>[1;32mNOP[0m:
>        [31mTrace point ID: 39
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18815.0f (0x4692fe00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18814.0f (0x4692fc00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18815.5f (0x4692ff00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18816.5f (0x46930100)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18817.5f (0x46930300)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000028
>[1;32mNOP[0m:
>        [31mTrace point ID: 40
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18818.0f (0x46930400)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18818.5f (0x46930500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534660
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000029
>[1;32mNOP[0m:
>        [31mTrace point ID: 41
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18822.0f (0x46930c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18821.0f (0x46930a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18822.5f (0x46930d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18823.5f (0x46930f00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18824.5f (0x46931100)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18825.5f (0x46931300)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18826.5f (0x46931500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000002a
>[1;32mNOP[0m:
>        [31mTrace point ID: 42
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18827.0f (0x46931600)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18827.5f (0x46931700)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534160
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000002b
>[1;32mNOP[0m:
>        [31mTrace point ID: 43
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18831.0f (0x46931e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18830.0f (0x46931c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18831.5f (0x46931f00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18832.5f (0x46932100)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18833.5f (0x46932300)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000002c
>[1;32mNOP[0m:
>        [31mTrace point ID: 44
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18834.0f (0x46932400)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18834.5f (0x46932500)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534160
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000002d
>[1;32mNOP[0m:
>        [31mTrace point ID: 45
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18838.0f (0x46932c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18837.0f (0x46932a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18838.5f (0x46932d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18839.5f (0x46932f00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18840.5f (0x46933100)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18843.0f (0x46933600)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18844.0f (0x46933800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18845.0f (0x46933a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000002e
>[1;32mNOP[0m:
>        [31mTrace point ID: 46
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18845.5f (0x46933b00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18846.0f (0x46933c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0053dd50
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0053dd70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000002f
>[1;32mNOP[0m:
>        [31mTrace point ID: 47
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18848.0f (0x46934000)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18849.0f (0x46934200)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18850.0f (0x46934400)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18851.0f (0x46934600)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18853.5f (0x46934b00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18854.5f (0x46934d00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18855.5f (0x46934f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0053dd80
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0053dda0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 2
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 6
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 4194 (0x00001062)
>        [1;33mVGT_DMA_BASE[0m <- 0x15ee3000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 4194 (0x00001062)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000030
>[1;32mNOP[0m:
>        [31mTrace point ID: 48
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18857.5f (0x46935300)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18858.5f (0x46935500)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18861.0f (0x46935a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18862.0f (0x46935c00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18863.0f (0x46935e00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18864.0f (0x46936000)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18865.0f (0x46936200)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 1
>                             STENCILMASK = 255 (0xff)
>                             STENCILWRITEMASK = 255 (0xff)
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 1
>                                STENCILMASK_BF = 255 (0xff)
>                                STENCILWRITEMASK_BF = 255 (0xff)
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 1
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_ALWAYS
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_REPLACE_TEST
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x004c40b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 26 (0x1a)
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005348f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 2
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 100 (0x00000064)
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 96 (0x00000060)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000031
>[1;32mNOP[0m:
>        [31mTrace point ID: 49
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18868.5f (0x46936900)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18867.5f (0x46936700)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 18869.0f (0x46936a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18871.5f (0x46936f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18872.5f (0x46937100)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18873.5f (0x46937300)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18876.0f (0x46937800)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18877.0f (0x46937a00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18878.0f (0x46937c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000032
>[1;32mNOP[0m:
>        [31mTrace point ID: 50
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18878.5f (0x46937d00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18879.0f (0x46937e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534660
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000033
>[1;32mNOP[0m:
>        [31mTrace point ID: 51
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18882.5f (0x46938500)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18881.5f (0x46938300)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18883.0f (0x46938600)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18884.0f (0x46938800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18885.0f (0x46938a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000034
>[1;32mNOP[0m:
>        [31mTrace point ID: 52
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18885.5f (0x46938b00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18886.0f (0x46938c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534660
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000035
>[1;32mNOP[0m:
>        [31mTrace point ID: 53
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18889.5f (0x46939300)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18888.5f (0x46939100)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18890.0f (0x46939400)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18891.0f (0x46939600)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18892.0f (0x46939800)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000036
>[1;32mNOP[0m:
>        [31mTrace point ID: 54
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18892.5f (0x46939900)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18893.0f (0x46939a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534660
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343e0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000037
>[1;32mNOP[0m:
>        [31mTrace point ID: 55
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18896.5f (0x4693a100)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18895.5f (0x46939f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18897.0f (0x4693a200)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18898.0f (0x4693a400)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18899.0f (0x4693a600)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18900.0f (0x4693a800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18901.0f (0x4693aa00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000038
>[1;32mNOP[0m:
>        [31mTrace point ID: 56
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18901.5f (0x4693ab00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18902.0f (0x4693ac00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534160
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000039
>[1;32mNOP[0m:
>        [31mTrace point ID: 57
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18905.5f (0x4693b300)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18904.5f (0x4693b100)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18906.0f (0x4693b400)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18907.0f (0x4693b600)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18908.0f (0x4693b800)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000003a
>[1;32mNOP[0m:
>        [31mTrace point ID: 58
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18908.5f (0x4693b900)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18909.0f (0x4693ba00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534160
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 7
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000003b
>[1;32mNOP[0m:
>        [31mTrace point ID: 59
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18912.5f (0x4693c100)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18911.5f (0x4693bf00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18913.0f (0x4693c200)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18914.0f (0x4693c400)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18915.0f (0x4693c600)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000003c
>[1;32mNOP[0m:
>        [31mTrace point ID: 60
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18915.5f (0x4693c700)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18916.0f (0x4693c800)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00534160
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 24 (0x18)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x005343f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 4
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 2
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 432 (0x000001b0)
>        [1;33mVGT_DMA_BASE[0m <- 0x1267d000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 432 (0x000001b0)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000003d
>[1;32mNOP[0m:
>        [31mTrace point ID: 61
>        [31mThis trace point was reached by the CP.[0m
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18918.0f (0x4693cc00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18919.0f (0x4693ce00)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18920.0f (0x4693d000)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18921.0f (0x4693d200)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18923.5f (0x4693d700)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18924.5f (0x4693d900)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18925.5f (0x4693db00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0053ddb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 25 (0x19)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 3
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0053ddf0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 11 (0xb)
>                                   SGPRS = 12 (0xc)
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 1
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 3
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00018000
>        [1;33mVGT_DMA_BASE[0m <- 0x00a60000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 6
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000003e
>[1;32mNOP[0m:
>        [31mTrace point ID: 62
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18929.0f (0x4693e200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18928.0f (0x4693e000)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 18929.5f (0x4693e300)
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18930.5f (0x4693e500)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18931.5f (0x4693e700)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18934.0f (0x4693ec00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18935.0f (0x4693ee00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18936.0f (0x4693f000)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000003f
>[1;32mNOP[0m:
>        [31mTrace point ID: 63
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18936.5f (0x4693f100)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18937.0f (0x4693f200)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0041adb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 23 (0x17)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0041add0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 6
>                                   SGPRS = 6
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 252 (0x000000fc)
>        [1;33mVGT_DMA_BASE[0m <- 0x3ef4c000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 252 (0x000000fc)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000040
>[1;32mNOP[0m:
>        [31mTrace point ID: 64
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18940.5f (0x4693f900)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18939.5f (0x4693f700)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18941.0f (0x4693fa00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18942.0f (0x4693fc00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18943.0f (0x4693fe00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000041
>[1;32mNOP[0m:
>        [31mTrace point ID: 65
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x000f0980
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x000d0bc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 59 (0x03b)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x000f0980
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18943.5f (0x4693ff00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18944.0f (0x46940000)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_SRC_ALPHA
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             SEPARATE_ALPHA_BLEND = 1
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0041adb0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 23 (0x17)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0041add0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 6
>                                   SGPRS = 6
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 528 (0x00000210)
>        [1;33mVGT_DMA_BASE[0m <- 0x3ef47000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 528 (0x00000210)
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000042
>[1;32mNOP[0m:
>        [31mTrace point ID: 66
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18945.5f (0x46940300)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18946.0f (0x46940400)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18947.0f (0x46940600)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 1076 (0x434)
>                                    BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000043
>[1;32mNOP[0m:
>        [31mTrace point ID: 67
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x0045e340
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x0045e340
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x0045e340
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18947.5f (0x46940700)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18948.0f (0x46940800)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 540.0f (0x44070000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 540.0f (0x44070000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 1
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x000513f0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000511f0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRIFAN
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000044
>[1;32mNOP[0m:
>        [31mTrace point ID: 68
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18951.0f (0x46940e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18950.0f (0x46940c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18951.5f (0x46940f00)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18952.5f (0x46941100)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18955.0f (0x46941600)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18956.0f (0x46941800)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18957.0f (0x46941a00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 1080 (0x438)
>                                    BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000045
>[1;32mNOP[0m:
>        [31mTrace point ID: 69
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x0045e340
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x0045e340
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x0045e340
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18957.5f (0x46941b00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18958.0f (0x46941c00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 1
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0041ade0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0041adf0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 15 (0xf)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00029fac
>        [1;33mVGT_DMA_BASE[0m <- 0x20ce3000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 0x00029fac
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000046
>[1;32mNOP[0m:
>        [31mTrace point ID: 70
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18961.0f (0x46942200)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18960.0f (0x46942000)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18961.5f (0x46942300)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18962.5f (0x46942500)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18965.0f (0x46942a00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18966.0f (0x46942c00)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18967.0f (0x46942e00)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000047
>[1;32mNOP[0m:
>        [31mTrace point ID: 71
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x0045e340
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 135 (0x87)
>                           FMASK_TILE_MAX = 135 (0x87)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x0045e340
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x0045e340
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 11967 (0x02ebf)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18967.5f (0x46942f00)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18968.0f (0x46943000)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 538.0f (0x44068000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 336.0f (0x43a80000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_4[0m <- OFFSET = 4
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 1
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 4
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0041ae00
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 9
>                                   SGPRS = 4
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 5
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0041ae10
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 15 (0xf)
>                                   SGPRS = 8
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 1
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              RDREQ_POLICY_VI = 0
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 0x00029fac
>        [1;33mVGT_DMA_BASE[0m <- 0x20ce3000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 0
>        [1;33mVGT_NUM_INDICES[0m <- 0x00029fac
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000048
>[1;32mNOP[0m:
>        [31mTrace point ID: 72
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x0004b500
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P4_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 1
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x00096f00
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x00093900
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x00096f00
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 143 (0x8f)
>                         HEIGHT_TILE_MAX = 95 (0x5f)
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 13823 (0x035ff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232 (0xe8)
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1080 (0x438)
>                                   BR_Y = 672 (0x2a0)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 1
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 0
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 18971.0f (0x46943600)
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 18970.0f (0x46943400)
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 18971.5f (0x46943700)
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 18972.5f (0x46943900)
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 18975.0f (0x46943e00)
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 18976.0f (0x46944000)
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 18977.0f (0x46944200)
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 0
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 1
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 0
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 0
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_DISABLE
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0005a130
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 2
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 0
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 0
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00053ff0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 0
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 10 (0xa)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 3
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000049
>[1;32mNOP[0m:
>        [31mTrace point ID: 73
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x41aee000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x0000004a
>[1;32mNOP[0m:
>        [31mTrace point ID: 74
>        [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>------------------- IB end -------------------
>

Actions: View

Attachments on bug 93436: 120588

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.