Attachment 121540 Details for Bug 94012 – vm debug

vm debug

clpeak_3814_00000000 (text/plain), 24.95 KB, created by Andy Furniss on 2016-02-05 18:29:44 UTC

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Creator: Andy Furniss

Created: 2016-02-05 18:29:44 UTC

Size: 24.95 KB

patch

obsolete

>VM fault report.
>
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD TONGA (DRM 3.1.0, LLVM 3.9.0)
>
>Failing VM page: 0x002309be
>
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>          16    0x0000000100214       0x0000000100224       BORDER_COLORS
>           1    0x0000000100224       0x0000000100225       IB2
>           4    -- hole --
>       32768    0x0000000100229       0x0000000108229       COMPUTE_GLOBAL
>           2    -- hole --
>       32768    0x000000010822b       0x000000011022b       COMPUTE_GLOBAL
>        2989    -- hole --
>           1    0x0000000110dd8       0x0000000110dd9       QUERY
>           1    0x0000000110dd9       0x0000000110dda       QUERY
>           5    -- hole --
>           1    0x0000000110ddf       0x0000000110de0       QUERY
>          26    -- hole --
>           1    0x0000000110dfa       0x0000000110dfb       TRACE
>       23975    -- hole --
>        2912    0x0000000116ba2       0x0000000117702       SCRATCH_BUFFER
>          76    0x0000000117702       0x000000011774e       USER_SHADER
>           1    0x000000011774e       0x000000011774f       CONST_BUFFER
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f (0x42800000)
>        [1;33mVGT_HOS_MIN_TESS_LEVEL[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128 (0x80)
>        [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64 (0x40)
>        [1;33mVGT_GS_PER_VS[0m <- GS_PER_VS = 2
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_RESET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_VTX_CNT_EN[0m <- VTX_CNT_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                     DISTANCE_1 = 1
>                                     DISTANCE_2 = 2
>                                     DISTANCE_3 = 3
>                                     DISTANCE_4 = 4
>                                     DISTANCE_5 = 5
>                                     DISTANCE_6 = 6
>                                     DISTANCE_7 = 7
>        [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 8
>                                     DISTANCE_9 = 9
>                                     DISTANCE_10 = 10 (0xa)
>                                     DISTANCE_11 = 11 (0xb)
>                                     DISTANCE_12 = 12 (0xc)
>                                     DISTANCE_13 = 13 (0xd)
>                                     DISTANCE_14 = 14 (0xe)
>                                     DISTANCE_15 = 15 (0xf)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_PRIM_FILTER_CNTL[0m <- TRIANGLE_FILTER_DISABLE = 0
>                                  LINE_FILTER_DISABLE = 0
>                                  POINT_FILTER_DISABLE = 0
>                                  RECTANGLE_FILTER_DISABLE = 0
>                                  TRIANGLE_EXPAND_ENA = 0
>                                  LINE_EXPAND_ENA = 0
>                                  POINT_EXPAND_ENA = 0
>                                  RECTANGLE_EXPAND_ENA = 0
>                                  PRIM_EXPAND_CONSTANT = 0
>                                  XMAX_RIGHT_EXCLUSION = 0
>                                  YMAX_BOTTOM_EXCLUSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_1[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_1[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_2[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_2[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_3[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_3[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_4[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_4[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_5[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_5[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_6[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_6[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_7[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_7[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_8[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_8[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_9[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_9[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_10[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_10[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_11[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_11[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_12[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_12[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_13[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_13[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_14[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_14[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_15[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_15[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
>                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
>                               RB_XSEL = 0
>                               RB_YSEL = 0
>                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                               SC_MAP = RASTER_CONFIG_SC_MAP_0
>                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                               SE_MAP = RASTER_CONFIG_SE_MAP_2
>                               SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
>                               SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
>        [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_2
>                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE
>                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>                                   WINDOW_OFFSET_DISABLE = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_GENERIC_SCISSOR_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_GENERIC_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                    BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_SCREEN_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>        [1;33mPA_SC_SCREEN_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                   BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CLIPRECT_RULE[0m <- CLIP_RULE = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_EDGERULE[0m <- ER_TRI = 10 (0xa)
>                          ER_POINT = 10 (0xa)
>                          ER_RECT = 10 (0xa)
>                          ER_LINE_LR = 42 (0x2a)
>                          ER_LINE_RL = 42 (0x2a)
>                          ER_LINE_TB = 10 (0xa)
>                          ER_LINE_BT = 10 (0xa)
>        [1;33mPA_SU_HARDWARE_SCREEN_OFFSET[0m <- HW_SCREEN_OFFSET_X = 0
>                                        HW_SCREEN_OFFSET_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_NANINF_CNTL[0m <- VTE_XY_INF_DISCARD = 0
>                             VTE_Z_INF_DISCARD = 0
>                             VTE_W_INF_DISCARD = 0
>                             VTE_0XNANINF_IS_0 = 0
>                             VTE_XY_NAN_RETAIN = 0
>                             VTE_Z_NAN_RETAIN = 0
>                             VTE_W_NAN_RETAIN = 0
>                             VTE_W_RECIP_NAN_IS_0 = 0
>                             VS_XY_NAN_TO_INF = 0
>                             VS_XY_INF_RETAIN = 0
>                             VS_Z_NAN_TO_INF = 0
>                             VS_Z_INF_RETAIN = 0
>                             VS_W_NAN_TO_INF = 0
>                             VS_W_INF_RETAIN = 0
>                             VS_CLIP_DIST_INF_DISCARD = 0
>                             VTE_NO_OUTPUT_NEG_0 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f (0x3f800000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SRESULTS_COMPARE_STATE0[0m <- COMPAREFUNC0 = REF_NEVER
>                                      COMPAREVALUE0 = 0
>                                      COMPAREMASK0 = 0
>                                      ENABLE0 = 0
>        [1;33mDB_SRESULTS_COMPARE_STATE1[0m <- COMPAREFUNC1 = REF_NEVER
>                                      COMPAREVALUE1 = 0
>                                      COMPAREMASK1 = 0
>                                      ENABLE1 = 0
>        [1;33mDB_PRELOAD_CONTROL[0m <- START_X = 0
>                              START_Y = 0
>                              MAX_X = 0
>                              MAX_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE[0m <- FORCE_HIZ_ENABLE = FORCE_OFF
>                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
>                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
>                              FORCE_SHADER_Z_ORDER = 0
>                              FAST_Z_DISABLE = 0
>                              FAST_STENCIL_DISABLE = 0
>                              NOOP_CULL_DISABLE = 0
>                              FORCE_COLOR_KILL = 0
>                              FORCE_Z_READ = 0
>                              FORCE_STENCIL_READ = 0
>                              FORCE_FULL_Z_RANGE = FORCE_OFF
>                              FORCE_QC_SMASK_CONFLICT = 0
>                              DISABLE_VIEWPORT_CLAMP = 0
>                              IGNORE_SC_ZRANGE = 0
>                              DISABLE_FULLY_COVERED = 0
>                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
>                              MAX_TILES_IN_DTT = 0
>                              DISABLE_TILE_RATE_TILES = 0
>                              FORCE_Z_DIRTY = 0
>                              FORCE_STENCIL_DIRTY = 0
>                              FORCE_Z_VALID = 0
>                              FORCE_STENCIL_VALID = 0
>                              PRESERVE_COMPRESSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>        [1;33mVGT_MIN_VTX_INDX[0m <- 0
>        [1;33mVGT_INDX_OFFSET[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0xfffe
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0xfffe
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>        [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 31 (0x1f)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                          OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1
>                          OVERWRITE_COMBINER_WATERMARK = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_VERTEX_REUSE_BLOCK_CNTL[0m <- VTX_REUSE_DEPTH = 30 (0x1e)
>        [1;33mVGT_OUT_DEALLOC_CNTL[0m <- DEALLOC_DIST = 32 (0x20)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mTA_BC_BASE_ADDR[0m <- 0x01002140
>        [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>------------------- IB2: Init config end -------------------
>
>------------------ IB begin ------------------
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x10dfa000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000001
>[1;32mNOP[0m:
>        [31mTrace point ID: 1
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDIRECT_BUFFER_CIK[0m:
>        0x00224000
>        0x00000001
>        0x00000090
>[1;32mEVENT_WRITE_EOP[0m:
>        0x00000514
>        0x10dd9000
>        0x60000001
>        0x00000000
>        0x00000000
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;32mEVENT_WRITE_EOP[0m:
>        0x0000052d
>        0x00000000
>        0x00000000
>        0x00000000
>        0x00000000
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = CACHE_FLUSH
>        [1;33mEVENT_INDEX[0m <- 7
>        [1;33mINV_L2[0m <- 1
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mCOMPUTE_USER_DATA_0[0m <- 0x1774e000
>        [1;33mCOMPUTE_USER_DATA_1[0m <- 1
>        [1;33mCOMPUTE_USER_DATA_2[0m <- 0x16ba2000
>        [1;33mCOMPUTE_USER_DATA_3[0m <- 0x00900001
>[1;36mSET_SH_REG[1;36m:
>        [1;33mCOMPUTE_START_X[0m <- 0
>        [1;33mCOMPUTE_START_Y[0m <- 0
>        [1;33mCOMPUTE_START_Z[0m <- 0
>        [1;33mCOMPUTE_NUM_THREAD_X[0m <- NUM_THREAD_FULL = 256 (0x0100)
>                                NUM_THREAD_PARTIAL = 0
>        [1;33mCOMPUTE_NUM_THREAD_Y[0m <- NUM_THREAD_FULL = 1
>                                NUM_THREAD_PARTIAL = 0
>        [1;33mCOMPUTE_NUM_THREAD_Z[0m <- NUM_THREAD_FULL = 1
>                                NUM_THREAD_PARTIAL = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mCOMPUTE_PGM_LO[0m <- 0x01177053
>        [1;33mCOMPUTE_PGM_HI[0m <- DATA = 0
>                          INST_ATC = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mCOMPUTE_PGM_RSRC1[0m <- VGPRS = 63 (0x3f)
>                             SGPRS = 9
>                             PRIORITY = 0
>                             FLOAT_MODE = 192 (0xc0)
>                             PRIV = 0
>                             DX10_CLAMP = 1
>                             DEBUG_MODE = 0
>                             IEEE_MODE = 0
>                             BULKY = 0
>                             CDBG_USER = 0
>        [1;33mCOMPUTE_PGM_RSRC2[0m <- SCRATCH_EN = 1
>                             USER_SGPR = 2
>                             TRAP_PRESENT = 0
>                             TGID_X_EN = 1
>                             TGID_Y_EN = 0
>                             TGID_Z_EN = 0
>                             TG_SIZE_EN = 0
>                             TIDIG_COMP_CNT = 0
>                             EXCP_EN_MSB = 0
>                             LDS_SIZE = 0
>                             EXCP_EN = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mCOMPUTE_RESOURCE_LIMITS[0m <- WAVES_PER_SH = 0
>                                   WAVES_PER_SH_CIK = 0
>                                   TG_PER_CU = 0
>                                   LOCK_THRESHOLD = 0
>                                   SIMD_DEST_CNTL = 0
>                                   FORCE_SIMD_DIST = 0
>                                   CU_GROUP_COUNT = 0
>        [1;33mCOMPUTE_STATIC_THREAD_MGMT_SE0[0m <- SH0_CU_EN = 0xffff
>                                          SH1_CU_EN = 0xffff
>        [1;33mCOMPUTE_STATIC_THREAD_MGMT_SE1[0m <- SH0_CU_EN = 0xffff
>                                          SH1_CU_EN = 0xffff
>        [1;33mCOMPUTE_TMPRING_SIZE[0m <- WAVES = 896 (0x380)
>                                WAVESIZE = 9
>[1;32mDISPATCH_DIRECT[0m:
>        0x00000200
>        0x00000001
>        0x00000001
>        0x00000001
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = CS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 0
>                         CB1_DEST_BASE_ENA = 0
>                         CB2_DEST_BASE_ENA = 0
>                         CB3_DEST_BASE_ENA = 0
>                         CB4_DEST_BASE_ENA = 0
>                         CB5_DEST_BASE_ENA = 0
>                         CB6_DEST_BASE_ENA = 0
>                         CB7_DEST_BASE_ENA = 0
>                         DB_DEST_BASE_ENA = 0
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 0
>                         DB_ACTION_ENA = 0
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mEVENT_WRITE_EOP[0m:
>        0x00000514
>        0x10dd8000
>        0x60000001
>        0x00000000
>        0x00000000
>[1;32mEVENT_WRITE_EOP[0m:
>        0x00000514
>        0x10ddf000
>        0x60000001
>        0x00000000
>        0x00000000
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = CACHE_FLUSH
>        [1;33mEVENT_INDEX[0m <- 7
>        [1;33mINV_L2[0m <- 1
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 0
>                         CB1_DEST_BASE_ENA = 0
>                         CB2_DEST_BASE_ENA = 0
>                         CB3_DEST_BASE_ENA = 0
>                         CB4_DEST_BASE_ENA = 0
>                         CB5_DEST_BASE_ENA = 0
>                         CB6_DEST_BASE_ENA = 0
>                         CB7_DEST_BASE_ENA = 0
>                         DB_DEST_BASE_ENA = 0
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 0
>                         DB_ACTION_ENA = 0
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mEVENT_WRITE_EOP[0m:
>        0x0000052d
>        0x00000000
>        0x00000000
>        0x00000000
>        0x00000000
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x10dfa000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000002
>[1;32mNOP[0m:
>        [31mTrace point ID: 2
>        [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>------------------- IB end -------------------
>

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Attachments on bug 94012: 121540 | 121541

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