Attachment 41942 Details for Bug 28306 – Poke SSC bits

[patch] Poke SSC bits

0001-drm-i915-Disable-SSC-for-outputs-other-than-LVDS-or-.patch (text/plain), 5.23 KB, created by Chris Wilson on 2011-01-12 15:10:44 UTC

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Creator: Chris Wilson

Created: 2011-01-12 15:10:44 UTC

Size: 5.23 KB

patch

obsolete

>From 35c7b575fd368d49c8f190a05f92fc062090e0b2 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Wed, 12 Jan 2011 20:22:10 +0000
>Subject: [PATCH] drm/i915: Disable SSC for outputs other than LVDS or DP
>
>For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we
>must clear any enabling bits left-over from earlier outputs.
>
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_drv.h      |    1 +
> drivers/gpu/drm/i915/i915_reg.h      |    1 +
> drivers/gpu/drm/i915/intel_bios.c    |    1 +
> drivers/gpu/drm/i915/intel_bios.h    |    4 ++-
> drivers/gpu/drm/i915/intel_display.c |   56 +++++++++++++++++++---------------
> 5 files changed, 37 insertions(+), 26 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 5969f46..adfeff0 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -344,6 +344,7 @@ typedef struct drm_i915_private {
> 	unsigned int lvds_vbt:1;
> 	unsigned int int_crt_support:1;
> 	unsigned int lvds_use_ssc:1;
>+	unsigned int display_clock_mode:1;
> 	int lvds_ssc_freq;
> 	struct {
> 		int rate;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 40a407f..7683916 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2898,6 +2898,7 @@
> #define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
> #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
> #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
>+#define  DREF_SUPERSPREAD_SOURCE_MASK           (3<<7)
> #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
> #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
> #define  DREF_SSC1_DISABLE                      (0<<1)
>diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>index 0b44956..c0377f3 100644
>--- a/drivers/gpu/drm/i915/intel_bios.c
>+++ b/drivers/gpu/drm/i915/intel_bios.c
>@@ -263,6 +263,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
> 		dev_priv->int_tv_support = general->int_tv_support;
> 		dev_priv->int_crt_support = general->int_crt_support;
> 		dev_priv->lvds_use_ssc = general->enable_ssc;
>+		dev_priv->display_clock_mode = general->display_clock_mode;
> 
> 		if (IS_I85X(dev))
> 			dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
>diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
>index 5f8e4ed..02b1b624 100644
>--- a/drivers/gpu/drm/i915/intel_bios.h
>+++ b/drivers/gpu/drm/i915/intel_bios.h
>@@ -120,7 +120,9 @@ struct bdb_general_features {
> 	u8 ssc_freq:1;
> 	u8 enable_lfp_on_override:1;
> 	u8 disable_ssc_ddt:1;
>-	u8 rsvd8:3; /* finish byte */
>+	u8 rsvd7:1;
>+	u8 display_clock_mode:1;
>+	u8 rsvd8:1; /* finish byte */
> 
>         /* bits 3 */
> 	u8 disable_smooth_vision:1;
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 98967f3..b72f174 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -4052,44 +4052,50 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
> 	 * ignoring this setting.
> 	 */
> 	if (HAS_PCH_SPLIT(dev)) {
>+		/*XXX BIOS treats 16:31 as a mask for 0:15 */
>+
> 		temp = I915_READ(PCH_DREF_CONTROL);
>-		/* Always enable nonspread source */
>+
>+		/* First clear the current state for output switching */
>+		temp &= ~DREF_SSC1_ENABLE;
>+		temp &= ~DREF_SSC4_ENABLE;
>+		temp &= ~DREF_SUPERSPREAD_SOURCE_MASK;
> 		temp &= ~DREF_NONSPREAD_SOURCE_MASK;
>-		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
> 		temp &= ~DREF_SSC_SOURCE_MASK;
>-		temp |= DREF_SSC_SOURCE_ENABLE;
>+		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> 		I915_WRITE(PCH_DREF_CONTROL, temp);
> 
> 		POSTING_READ(PCH_DREF_CONTROL);
> 		udelay(200);
> 
>-		if (has_edp_encoder) {
>-			if (intel_panel_use_ssc(dev_priv)) {
>-				temp |= DREF_SSC1_ENABLE;
>-				I915_WRITE(PCH_DREF_CONTROL, temp);
>-
>-				POSTING_READ(PCH_DREF_CONTROL);
>-				udelay(200);
>-			}
>-			temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
>-
>-			/* Enable CPU source on CPU attached eDP */
>-			if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
>-				if (intel_panel_use_ssc(dev_priv))
>+		if ((is_lvds || has_edp_encoder) &&
>+		    intel_panel_use_ssc(dev_priv)) {
>+			temp |= DREF_SSC_SOURCE_ENABLE;
>+			if (has_edp_encoder) {
>+				if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
>+					/* Enable CPU source on CPU attached eDP */
> 					temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
>-				else
>-					temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
>-			} else {
>-				/* Enable SSC on PCH eDP if needed */
>-				if (intel_panel_use_ssc(dev_priv)) {
>-					DRM_ERROR("enabling SSC on PCH\n");
>+				} else {
>+					/* Enable SSC on PCH eDP if needed */
> 					temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
> 				}
>+				I915_WRITE(PCH_DREF_CONTROL, temp);
> 			}
>-			I915_WRITE(PCH_DREF_CONTROL, temp);
>-			POSTING_READ(PCH_DREF_CONTROL);
>-			udelay(200);
>+			if (!dev_priv->display_clock_mode)
>+				temp |= DREF_SSC1_ENABLE;
>+		} else {
>+			if (dev_priv->display_clock_mode)
>+				temp |= DREF_NONSPREAD_CK505_ENABLE;
>+			else
>+				temp |= DREF_NONSPREAD_SOURCE_ENABLE;
>+			if (has_edp_encoder &&
>+			    !intel_encoder_is_pch_edp(&has_edp_encoder->base))
>+				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> 		}
>+
>+		I915_WRITE(PCH_DREF_CONTROL, temp);
>+		POSTING_READ(PCH_DREF_CONTROL);
>+		udelay(200);
> 	}
> 
> 	if (IS_PINEVIEW(dev)) {
>-- 
>1.7.2.3
>

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Attachments on bug 28306: 36009 | 36010 | 36015 | 36016 | 36017 | 39279 | 39280 | 41942 | 46540

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