Attachment 59975 Details for Bug 41092 – gnoutchd-v3.4-rc1+-intel_reg_dumper.txt

gnoutchd-v3.4-rc1+-intel_reg_dumper.txt

intel_reg_dumper (text/plain), 11.10 KB, created by Daniel Gnoutcheff on 2012-04-14 08:28:53 UTC

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Creator: Daniel Gnoutcheff

Created: 2012-04-14 08:28:53 UTC

Size: 11.10 KB

patch

obsolete

>                 DCC: 0x000f0002 (dual channel interleaved, XOR randomization: enabled, XOR bit: 11)
>           CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>              C0DRB0: 0x000f0002 (0x0002)
>              C0DRB1: 0x0010000f (0x000f)
>              C0DRB2: 0x00000010 (0x0010)
>              C0DRB3: 0x0e000000 (0x0000)
>              C1DRB0: 0x17cbe000 (0xe000)
>              C1DRB1: 0x000017cb (0x17cb)
>              C1DRB2: 0x00000000 (0x0000)
>              C1DRB3: 0x00000000 (0x0000)
>             C0DRA01: 0x00030e00 (0x0e00)
>             C0DRA23: 0x000c0003 (0x0003)
>             C1DRA01: 0x00000000 (0x0000)
>             C1DRA23: 0x00000000 (0x0000)
>          PGETBL_CTL: 0x7df80001
>   VCLK_DIVISOR_VGA0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>   VCLK_DIVISOR_VGA1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>       VCLK_POST_DIV: 0x00000000 (vga0 p1 = 2, p2 = 2, vga1 p1 = 2, p2 = 2)
>           DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>        CACHE_MODE_0: 0x00000000
>             D_STATE: 0x00000000
>       DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>      RENCLK_GATE_D1: 0x00000000
>      RENCLK_GATE_D2: 0x00000000
>               SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>               SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>             SDVOUDI: 0x00000000
>              DSPARB: 0x00000000
>              DSPFW1: 0x00000000
>              DSPFW2: 0x00000000
>              DSPFW3: 0x00000000
>                ADPA: 0x00000000 (disabled, pipe A, -hsync, -vsync)
>                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>                DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>                DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>         DVOA_SRCDIM: 0x00000000
>         DVOB_SRCDIM: 0x00000000
>         DVOC_SRCDIM: 0x00000000
>          PP_CONTROL: 0x00000000 (power target: off)
>           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>        PP_ON_DELAYS: 0x00000000
>       PP_OFF_DELAYS: 0x00000000
>          PP_DIVISOR: 0x00000000
>        PFIT_CONTROL: 0x00000000
>     PFIT_PGM_RATIOS: 0x00000000
>     PORT_HOTPLUG_EN: 0x00000000
>   PORT_HOTPLUG_STAT: 0x00000000
>            DSPACNTR: 0x00000000 (disabled, pipe A)
>          DSPASTRIDE: 0x00000000 (0 bytes)
>             DSPAPOS: 0x00000000 (0, 0)
>            DSPASIZE: 0x00000000 (1, 1)
>            DSPABASE: 0x00000000
>            DSPASURF: 0x00000000
>         DSPATILEOFF: 0x00000000
>           PIPEACONF: 0x00000000 (disabled, inactive)
>            PIPEASRC: 0x00000000 (1, 1)
>           PIPEASTAT: 0x00000000 (status:)
>   PIPEA_GMCH_DATA_M: 0x00000000
>   PIPEA_GMCH_DATA_N: 0x00000000
>     PIPEA_DP_LINK_M: 0x00000000
>     PIPEA_DP_LINK_N: 0x00000000
>       CURSOR_A_BASE: 0x00000000
>    CURSOR_A_CONTROL: 0x00000000
>   CURSOR_A_POSITION: 0x00000000
>                FPA0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>                FPA1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>              DPLL_A: 0x00000000 (disabled, non-dvo, VGA, default clock, unknown mode, p1 = 0, p2 = 0)
>           DPLL_A_MD: 0x00000000
>            HTOTAL_A: 0x00000000 (1 active, 1 total)
>            HBLANK_A: 0x00000000 (1 start, 1 end)
>             HSYNC_A: 0x00000000 (1 start, 1 end)
>            VTOTAL_A: 0x00000000 (1 active, 1 total)
>            VBLANK_A: 0x00000000 (1 start, 1 end)
>             VSYNC_A: 0x00000000 (1 start, 1 end)
>           BCLRPAT_A: 0x00000000
>        VSYNCSHIFT_A: 0x00000000
>            DSPBCNTR: 0x00000000 (disabled, pipe A)
>          DSPBSTRIDE: 0x00000000 (0 bytes)
>             DSPBPOS: 0x00000000 (0, 0)
>            DSPBSIZE: 0x00000000 (1, 1)
>            DSPBBASE: 0x00000000
>            DSPBSURF: 0x00000000
>         DSPBTILEOFF: 0x00000000
>           PIPEBCONF: 0x00000000 (disabled, inactive)
>            PIPEBSRC: 0x00000000 (1, 1)
>           PIPEBSTAT: 0x00000000 (status:)
>   PIPEB_GMCH_DATA_M: 0x00000000
>   PIPEB_GMCH_DATA_N: 0x00000000
>     PIPEB_DP_LINK_M: 0x00000000
>     PIPEB_DP_LINK_N: 0x00000000
>       CURSOR_B_BASE: 0x00000000
>    CURSOR_B_CONTROL: 0x00000000
>   CURSOR_B_POSITION: 0x00000000
>                FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>                FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0)
>              DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, unknown mode, p1 = 0, p2 = 0)
>           DPLL_B_MD: 0x00000000
>            HTOTAL_B: 0x00000000 (1 active, 1 total)
>            HBLANK_B: 0x00000000 (1 start, 1 end)
>             HSYNC_B: 0x00000000 (1 start, 1 end)
>            VTOTAL_B: 0x00000000 (1 active, 1 total)
>            VBLANK_B: 0x00000000 (1 start, 1 end)
>             VSYNC_B: 0x00000000 (1 start, 1 end)
>           BCLRPAT_B: 0x00000000
>        VSYNCSHIFT_B: 0x00000000
>   VCLK_DIVISOR_VGA0: 0x00000000
>   VCLK_DIVISOR_VGA1: 0x00000000
>       VCLK_POST_DIV: 0x00000000
>            VGACNTRL: 0x00000000 (enabled)
>              TV_CTL: 0x00000000
>              TV_DAC: 0x00000000
>            TV_CSC_Y: 0x00000000
>           TV_CSC_Y2: 0x00000000
>            TV_CSC_U: 0x00000000
>           TV_CSC_U2: 0x00000000
>            TV_CSC_V: 0x00000000
>           TV_CSC_V2: 0x00000000
>        TV_CLR_KNOBS: 0x00000000
>        TV_CLR_LEVEL: 0x00000000
>          TV_H_CTL_1: 0x00000000
>          TV_H_CTL_2: 0x00000000
>          TV_H_CTL_3: 0x00000000
>          TV_V_CTL_1: 0x00000000
>          TV_V_CTL_2: 0x00000000
>          TV_V_CTL_3: 0x00000000
>          TV_V_CTL_4: 0x00000000
>          TV_V_CTL_5: 0x00000000
>          TV_V_CTL_6: 0x00000000
>          TV_V_CTL_7: 0x00000000
>         TV_SC_CTL_1: 0x00000000
>         TV_SC_CTL_2: 0x00000000
>         TV_SC_CTL_3: 0x00000000
>          TV_WIN_POS: 0x00000000
>         TV_WIN_SIZE: 0x00000000
>     TV_FILTER_CTL_1: 0x00000000
>     TV_FILTER_CTL_2: 0x00000000
>     TV_FILTER_CTL_3: 0x00000000
>       TV_CC_CONTROL: 0x00000000
>          TV_CC_DATA: 0x00000000
>         TV_H_LUMA_0: 0x00000000
>        TV_H_LUMA_59: 0x00000000
>       TV_H_CHROMA_0: 0x00000000
>      TV_H_CHROMA_59: 0x00000000
>        FBC_CFB_BASE: 0x00000000
>         FBC_LL_BASE: 0x00000000
>         FBC_CONTROL: 0x00000000
>         FBC_COMMAND: 0x00000000
>          FBC_STATUS: 0x00000000
>        FBC_CONTROL2: 0x00000000
>       FBC_FENCE_OFF: 0x00000000
>         FBC_MOD_NUM: 0x00000000
>             MI_MODE: 0x00000000
>        MI_ARB_STATE: 0x00000000
>      MI_RDRET_STATE: 0x00000000
>             ECOSKPD: 0x00000000
>                DP_B: 0x00000000
>      DPB_AUX_CH_CTL: 0x00000000
>    DPB_AUX_CH_DATA1: 0x00000000
>    DPB_AUX_CH_DATA2: 0x00000000
>    DPB_AUX_CH_DATA3: 0x00000000
>    DPB_AUX_CH_DATA4: 0x00000000
>    DPB_AUX_CH_DATA5: 0x00000000
>                DP_C: 0x00000000
>      DPC_AUX_CH_CTL: 0x00000000
>    DPC_AUX_CH_DATA1: 0x00000000
>    DPC_AUX_CH_DATA2: 0x00000000
>    DPC_AUX_CH_DATA3: 0x00000000
>    DPC_AUX_CH_DATA4: 0x00000000
>    DPC_AUX_CH_DATA5: 0x00000000
>                DP_D: 0x00000000
>      DPD_AUX_CH_CTL: 0x00000000
>    DPD_AUX_CH_DATA1: 0x00000000
>    DPD_AUX_CH_DATA2: 0x00000000
>    DPD_AUX_CH_DATA3: 0x00000000
>    DPD_AUX_CH_DATA4: 0x00000000
>    DPD_AUX_CH_DATA5: 0x00000000
>          AUD_CONFIG: 0x00000000
>    AUD_HDMIW_STATUS: 0x00000000
>      AUD_CONV_CHCNT: 0x00000000
>       VIDEO_DIP_CTL: 0x00000000
>       AUD_PINW_CNTR: 0x00000000
>         AUD_CNTL_ST: 0x00000000
>         AUD_PIN_CAP: 0x00000000
>        AUD_PINW_CAP: 0x00000000
>  AUD_PINW_UNSOLRESP: 0x00000000
>    AUD_OUT_DIG_CNVT: 0x00000000
>       AUD_OUT_CWCAP: 0x00000000
>         AUD_GRP_CAP: 0x00000000
>            FENCE  0: 0x00000000 (enabled)
>            FENCE  1: 0x00000000 (enabled)
>            FENCE  2: 0x00000000 (enabled)
>            FENCE  3: 0x00000000 (enabled)
>            FENCE  4: 0x00000000 (enabled)
>            FENCE  5: 0x00000000 (enabled)
>            FENCE  6: 0x00000000 (enabled)
>            FENCE  7: 0x00000000 (enabled)
>            FENCE  8: 0x0d85209d (enabled)
>            FENCE  9: 0x0dc51000 (enabled)
>           FENCE  10: 0x01c4a09d (enabled)
>           FENCE  11: 0x02049000 (enabled)
>           FENCE  12: 0x035fb09d (enabled)
>           FENCE  13: 0x039fa000 (enabled)
>           FENCE  14: 0x02e0909d (enabled)
>           FENCE  15: 0x03208000 (enabled)
>       FENCE START 0: 0x0d85209d ( enabled, X tile walk, 5120 pitch, 0x0d852000 start)
>         FENCE END 0: 0x0dc51000 (                                   0x0dc51000 end)
>       FENCE START 1: 0x01c4a09d ( enabled, X tile walk, 5120 pitch, 0x01c4a000 start)
>         FENCE END 1: 0x02049000 (                                   0x02049000 end)
>       FENCE START 2: 0x035fb09d ( enabled, X tile walk, 5120 pitch, 0x035fb000 start)
>         FENCE END 2: 0x039fa000 (                                   0x039fa000 end)
>       FENCE START 3: 0x02e0909d ( enabled, X tile walk, 5120 pitch, 0x02e09000 start)
>         FENCE END 3: 0x03208000 (                                   0x03208000 end)
>       FENCE START 4: 0x06c2d01d ( enabled, X tile walk, 1024 pitch, 0x06c2d000 start)
>         FENCE END 4: 0x06c38000 (                                   0x06c38000 end)
>       FENCE START 5: 0x0cc4309d ( enabled, X tile walk, 5120 pitch, 0x0cc43000 start)
>         FENCE END 5: 0x0d042000 (                                   0x0d042000 end)
>       FENCE START 6: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>         FENCE END 6: 0x00000000 (                                   0x00000000 end)
>       FENCE START 7: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>         FENCE END 7: 0x00000000 (                                   0x00000000 end)
>       FENCE START 8: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>         FENCE END 8: 0x00000000 (                                   0x00000000 end)
>       FENCE START 9: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>         FENCE END 9: 0x00000000 (                                   0x00000000 end)
>      FENCE START 10: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>        FENCE END 10: 0x00000000 (                                   0x00000000 end)
>      FENCE START 11: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>        FENCE END 11: 0x00000000 (                                   0x00000000 end)
>      FENCE START 12: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>        FENCE END 12: 0x00000000 (                                   0x00000000 end)
>      FENCE START 13: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>        FENCE END 13: 0x00000000 (                                   0x00000000 end)
>      FENCE START 14: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>        FENCE END 14: 0x00000000 (                                   0x00000000 end)
>      FENCE START 15: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>        FENCE END 15: 0x00000000 (                                   0x00000000 end)
>             INST_PM: 0x00000000
>p1 out of range
>SDVO phase shift 0 out of range -- probobly not an issue.
>pipe A dot 57600 n 0 m1 0 m2 0 p1 1 p2 10
>p1 out of range
>SDVO phase shift 0 out of range -- probobly not an issue.
>pipe B dot 57600 n 0 m1 0 m2 0 p1 1 p2 10

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Attachments on bug 41092: 51466 | 51467 | 51468 | 51469 | 51470 | 57259 | 57260 | 57261 | 57262 | 57263 | 59973 | 59974 | 59975 | 59976 | 81216

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