Attachment 94052 Details for Bug 74955 – drm/i915: Fix DDI port_clock for VGA output

[patch] drm/i915: Fix DDI port_clock for VGA output

0001-drm-i915-Fix-DDI-port_clock-for-VGA-output.patch (text/plain), 1.45 KB, created by Ville Syrjala on 2014-02-14 09:09:06 UTC

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Creator: Ville Syrjala

Created: 2014-02-14 09:09:06 UTC

Size: 1.45 KB

patch

obsolete

>From f1b10af35025caf89ecbd1b682ad59d24b1ad1bb Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Fri, 14 Feb 2014 10:57:31 +0200
>Subject: [PATCH] drm/i915: Fix DDI port_clock for VGA output
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>On DDI there's no PLL as such to generate the pixel clock for VGA.
>Instead we derive the pixel clock from the FDI link frequency. So
>to make .compute_config match what .get_config does, we need to
>set the port_clock based on the FDI link frequency.
>
>Note that we don't even check the port_clock when selecting the
>PLL for VGA output. We just assume SPLL at 1.35GHz is what we want,
>and that does match with the asumption of FDI frequency of 2.7Ghz
>we have in intel_fdi_link_freq().
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74955
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_crt.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
>index 5b444a4..c5f4008 100644
>--- a/drivers/gpu/drm/i915/intel_crt.c
>+++ b/drivers/gpu/drm/i915/intel_crt.c
>@@ -262,6 +262,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
> 	if (HAS_PCH_LPT(dev))
> 		pipe_config->pipe_bpp = 24;
> 
>+	/* assume SPLL @ 1.35 GHz */
>+	if (HAS_DDI(dev))
>+		pipe_config->port_clock = 135000 * 2;
>+
> 	return true;
> }
> 
>-- 
>1.8.3.2
>

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Attachments on bug 74955: 94037 | 94052

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