Attachment 95081 Details for Bug 75623 – Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"

[patch] Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"

0001-Revert-drm-i915-enable-HiZ-Raw-Stall-Optimization-on.patch (text/plain), 2.15 KB, created by Chris Wilson on 2014-03-04 09:43:45 UTC

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Creator: Chris Wilson

Created: 2014-03-04 09:43:45 UTC

Size: 2.15 KB

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obsolete

>From ab070056478185df07d8a2a0972b742e9d177010 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Tue, 4 Mar 2014 09:31:21 +0000
>Subject: [PATCH] Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>This reverts commit 116f2b6da868dec7539103574d0421cd6221e931.
>
>This optimization causes widespread corruption in games, and even in
>glxgears, on my ivb:gt1. The corruption appears like z-fighting of
>overlapping polygons in the HiZ buffer.
>
>The observation ties in very closely with the description of the
>optimization disabled by default on IVB:
>
>"The Hierarchical Z RAW Stall Optimization allows non-overlapping
>polygons in the same 8x4 pixel/sample area to be processed without
>stalling waiting for the earlier ones to write to Hierarchical Z
>buffer."
>
>No reason is given for why it is disabled by default, usually for such
>optimizations it is that it is incomplete. However, there is no
>indication whether this a gt1 only issue either. Before considering
>reenabling this optimization, I would first suggest reproducing the
>corruption in piglit.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75623
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Chia-I Wu <olv@lunarg.com>
>Cc: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_pm.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index b016d9bcd7c1..6b4d1a89e9bc 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -4908,9 +4908,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> 
> 	gen7_setup_fixed_func_scheduler(dev_priv);
> 
>-	/* enable HiZ Raw Stall Optimization */
>-	I915_WRITE(CACHE_MODE_0_GEN7,
>-		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
>+	if (0) { /* causes HiZ corruption on ivb:gt1 */
>+		/* enable HiZ Raw Stall Optimization */
>+		I915_WRITE(CACHE_MODE_0_GEN7,
>+			   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
>+	}
> 
> 	/* WaDisable4x2SubspanOptimization:ivb */
> 	I915_WRITE(CACHE_MODE_1,
>-- 
>1.9.0
>

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