From: Egbert Eich <eich@suse.com>
Date: Tue Oct 9 16:45:13 2012 +0200
Subject: DRM/i915: On GEN2 map lower and upper mmio Register Ranges separately.
Git-commit: ceb74fdfc95e571c1bb36790729098fe803cf7e2
Signed-off-by: Egbert Eich <eich@suse.de>
intel_gtt now maps the GTT range WC. The MMIO registers need
to be mapped uncached however.
On GEN2 hardware the GTT aperture is located right in the middle
of the PCI BAR which also contains the MMIO registers.
Mapping the full BAR in the intel driver fails however due
to the different memory type.
This patch maps the lower and upper MMIO range of the PCI BAR
separately on GEN2 hardware and adjusts the access functions
accordingly.
Signed-off-by: Egbert Eich <eich@suse.com>