Created attachment 68395 [details] [review]
Patch for solution a.
The DRM driver from drm-intel-next currently fails to initialize on GEN2 hardware.
Reason: the intel_gtt module maps the GTT aperture WC. This aperture however is located right in the middle of BAR 1 (where the MMIO registers are located). When the i915 driver loads it tries to map the entire bar uncached which conflicts with the earlier mapping in intel_gtt.
There are two ways to fix this:
a. map the lower and upper MMIO register ranges separately and adjust the
access functions accordingly. (elaborate patch).
b. map the GTT aperture uncached (tiny patch).
Created attachment 68396 [details] [review]
Patch for solution b.
Not all gen2 are affected, the wc mapping works on 855gm. But disabling it is the simplest patch.. :|
(In reply to comment #2)
> Not all gen2 are affected, the wc mapping works on 855gm. But disabling it
> is the simplest patch.. :|
This only seems to happen when PAT support is enabled.
Chris, could you please check if you get a "PAT not supported by CPU" on your system?
This is at least what happens here on my i855 test system where I don't see the issue either.
No PAT on my gen2 systems either. Okay, now that is bizarre.
Yeah, my i855gm also doesn't support PAT. I guess we simply need to disable the wc gtt pte mapping on gen2, not worth the trouble.
What's behind door number 2?
Author: Daniel Vetter <email@example.com>
Date: Wed Oct 10 23:14:01 2012 +0200
drm/i915: disable wc gtt pte mappings on gen2
It doesn't work since the gtt pte range sits in the middle of the mmio
bar. We didn't notice that since both my and Chris' gen2 machines
don't support PAT and hence all wc io mapping request will
automatically be demoted to uc.
This regression has been introduce in
Author: Chris Wilson <firstname.lastname@example.org>
Date: Fri Sep 14 11:57:47 2012 +0100
agp/intel: Use a write-combining map for updating PTEs
Reported-by: Egbert Eich <email@example.com>
Acked-by: Chris Wilson <firstname.lastname@example.org>
Signed-off-by: Daniel Vetter <email@example.com>