| Summary: | [GLK] cdclock frequency is always the same | ||||||
|---|---|---|---|---|---|---|---|
| Product: | DRI | Reporter: | Luis Botello <luis.botello.ortega> | ||||
| Component: | DRM/Intel | Assignee: | Dhinakaran Pandiyan <dhinakaran.pandiyan> | ||||
| Status: | CLOSED NOTABUG | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
| Severity: | normal | ||||||
| Priority: | medium | CC: | conselvan2, dhinakaran.pandiyan, intel-gfx-bugs | ||||
| Version: | DRI git | ||||||
| Hardware: | x86-64 (AMD64) | ||||||
| OS: | Linux (All) | ||||||
| Whiteboard: | |||||||
| i915 platform: | GLK | i915 features: | display/Other | ||||
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Description
Luis Botello
2017-03-29 01:06:15 UTC
The culprits are likely these two commits: commit 8cbeb06dc6b584009d7492c667a3c9a4b96cdefa Author: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com> Date: Tue Mar 14 15:45:56 2017 -0700 drm/i915: Implement cdclk restrictions based on Azalia BCLK commit 78cfa580f81e69857815c59c8908aee454726da1 Author: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com> Date: Tue Mar 7 16:12:51 2017 -0800 drm/i915/glk: Apply cdclk workaround for DP audio Updated to highest/blocker due to the impact on CDCLK Alpha feature HDMI audio is being enabled, which restricts cdclk going lower than 2*Azalia bclk (96 MHz by default). The choices for cdclk on GLK are 316.8 MHz, 158.4 MHz and 79.2 MHz. So, the only value greater than 2*96 MHz is 316.8 MHz. From BSpec "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is 96 MHz) 316.8 MHz CD 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single pipe eDP/MIPI configurations, no audio support)" Not entirely sure what happens if we violate this restriction in practice, but I think it makes sense to define a new API to get the actual Azalia bclk from the audio driver and explore options to lower that. This isn't a bug IMO, should we close this? Priority decreased, test is planned again ww15 It was tested again using new requirements. So closed. (In reply to Dhinakaran Pandiyan from comment #3) > HDMI audio is being enabled, which restricts cdclk going lower than 2*Azalia > bclk (96 MHz by default). The choices for cdclk on GLK are 316.8 MHz, 158.4 > MHz and 79.2 MHz. So, the only value greater than 2*96 MHz is 316.8 MHz. > > From BSpec > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is 96 > MHz) > 316.8 MHz CD > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single > pipe eDP/MIPI configurations, no audio support)" > > Not entirely sure what happens if we violate this restriction in practice, Adding my two cents to it. Due to violation I've seen igt tests@pm_rpm,kms@flip failing as HDA was not suspending. Test name kms_flip --run-subtest vblank-vs-modeset-rpm kms_flip --run-subtest vblank-vs-modeset-rpm-interruptible kms_flip --run-subtest vblank-vs-dpms-rpm kms_flip --run-subtest vblank-vs-dpms-rpm-interruptible pm_rpm --run-subtest basic-pci-d3-state pm_rpm --run-subtest basic-rte > but I think it makes sense to define a new API to get the actual Azalia bclk > from the audio driver and explore options to lower that. |
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