Bug 100439 - [GLK] cdclock frequency is always the same
Summary: [GLK] cdclock frequency is always the same
Status: CLOSED NOTABUG
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: DRI git
Hardware: x86-64 (AMD64) Linux (All)
: medium normal
Assignee: Dhinakaran Pandiyan
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2017-03-29 01:06 UTC by Luis Botello
Modified: 2018-03-09 03:26 UTC (History)
3 users (show)

See Also:
i915 platform: GLK
i915 features: display/Other


Attachments
dmesg (250.55 KB, text/plain)
2017-03-29 01:06 UTC, Luis Botello
no flags Details

Description Luis Botello 2017-03-29 01:06:15 UTC
Created attachment 130517 [details]
dmesg

==Bug detailed description==
--------------------------------------------------
cdclock frequency is always the same, it does not matter if reslution is changed on displays

==Steps to reproduce==
--------------------------------------------------
1. set a 4k resolution
2. cat /sys/kernel/debug/dri/0/i915_frequency_info |grep "Current CD clock frequency:"
3. set a HD resolution
4. cat /sys/kernel/debug/dri/0/i915_frequency_info |grep "Current CD clock frequency:"

==Actual results==
--------------------------------------------------
cdclock frequency is always the same (316800 kHz) , it does not matter if reslution is changed on displays 

==Expected results==
--------------------------------------------------
cdclock frequency must change according to resolution set on display

==Hardware configuration==
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CPU Name : Genuine Intel(R) CPU @ 1.10GHz (family: 6, model: 122) 4 cores
Graphic: Intel Corporation Device 3184 (rev 01) prog-if 00 VGA controller
RVP SKU : GLK RVP1
SOC : GML A1 Soc
QDF : Ql9R
Reworks : F23

==Software configuration==
--------------------------------------------------
kernel version            : 4.11.0-rc4-drm-tip-ww14-commit-dabd992+
architecture              : x86_64
os version                : Ubuntu 16.10
os codename               : yakkety
[sudo] password for gfx: kernel driver             : i915
bios revision             : 36.51
ksc                       : 1.13
modesetting               : modesetting_drv.so
xorg-xserver              : 1.18.4
libdrm                    : 2.4.75
vaapi (intel-driver)      : Intel i965 driver for Intel(R) Geminilake - 1.8.1.pre1 (1.7.3-358-g228e4fc)
cairo                     : 1.15.5
xserver                   : X.Org X Server 1.19.99.1
intel-gpu-tools (tag)     : intel-gpu-tools-1.18-40-g429dd43
intel-gpu-tools (commit)  : 429dd43

==kernel configuration==
--------------------------------------------------
commit dabd992961047cf26698036f563aa86a083284ac
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Tue Mar 28 18:26:27 2017 +0300

    drm-tip: 2017y-03m-28d-15h-25m-54s UTC integration manifest


Kernel version : 4.11.0-rc4-dabd992
Architecture : source amd64 all
Comment 1 Ville Syrjala 2017-03-29 08:52:33 UTC
The culprits are likely these two commits:

commit 8cbeb06dc6b584009d7492c667a3c9a4b96cdefa
Author: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Date:   Tue Mar 14 15:45:56 2017 -0700

    drm/i915: Implement cdclk restrictions based on Azalia BCLK

commit 78cfa580f81e69857815c59c8908aee454726da1
Author: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Date:   Tue Mar 7 16:12:51 2017 -0800

    drm/i915/glk: Apply cdclk workaround for DP audio
Comment 2 cprigent 2017-03-29 12:33:27 UTC
Updated to highest/blocker due to the impact on CDCLK Alpha feature
Comment 3 Dhinakaran Pandiyan 2017-03-29 20:59:22 UTC
HDMI audio is being enabled, which restricts cdclk going lower than 2*Azalia bclk (96 MHz by default). The choices for cdclk on GLK are 316.8 MHz, 158.4 MHz and 79.2 MHz. So, the only value greater than 2*96 MHz is 316.8 MHz.

From BSpec
"158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is 96 MHz)
316.8 MHz CD
79.2 MHz CD (exclusively for resolutions up to 1080p in low power single pipe eDP/MIPI configurations, no audio support)"

Not entirely sure what happens if we violate this restriction in practice, but I think it makes sense to define a new API to get the actual Azalia bclk from the audio driver and explore options to lower that.
Comment 4 Dhinakaran Pandiyan 2017-04-03 21:10:45 UTC
This isn't a bug IMO, should we close this?
Comment 5 cprigent 2017-04-07 09:47:14 UTC
Priority decreased, test is planned again ww15
Comment 6 cprigent 2017-04-18 14:14:55 UTC
It was tested again using new requirements.
So closed.
Comment 7 Abhijeet Kumar 2018-03-09 03:26:07 UTC
(In reply to Dhinakaran Pandiyan from comment #3)
> HDMI audio is being enabled, which restricts cdclk going lower than 2*Azalia
> bclk (96 MHz by default). The choices for cdclk on GLK are 316.8 MHz, 158.4
> MHz and 79.2 MHz. So, the only value greater than 2*96 MHz is 316.8 MHz.
> 
> From BSpec
> "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is 96
> MHz)
> 316.8 MHz CD
> 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
> pipe eDP/MIPI configurations, no audio support)"
> 
> Not entirely sure what happens if we violate this restriction in practice,

Adding my two cents to it. Due to violation I've seen igt tests@pm_rpm,kms@flip failing as HDA was not suspending.

Test name
kms_flip --run-subtest vblank-vs-modeset-rpm
kms_flip --run-subtest vblank-vs-modeset-rpm-interruptible
kms_flip --run-subtest vblank-vs-dpms-rpm
kms_flip --run-subtest vblank-vs-dpms-rpm-interruptible
pm_rpm --run-subtest basic-pci-d3-state
pm_rpm --run-subtest basic-rte

> but I think it makes sense to define a new API to get the actual Azalia bclk
> from the audio driver and explore options to lower that.


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