Summary: | [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks | ||
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Product: | Mesa | Reporter: | Mark Janes <mark.a.janes> |
Component: | Drivers/DRI/i965 | Assignee: | Matt Turner <mattst88> |
Status: | RESOLVED FIXED | QA Contact: | Intel 3D Bugs Mailing List <intel-3d-bugs> |
Severity: | normal | ||
Priority: | medium | ||
Version: | git | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | |||
i915 platform: | i915 features: | ||
Bug Depends on: | |||
Bug Blocks: | 103491 | ||
Attachments: | Patch that probably fixes it |
Description
Mark Janes
2017-11-08 18:20:15 UTC
This fails because of: mov(8) g21<1>UQ g19<8,1,0>UB { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit ERROR: Vstride must be Width * Hstride when the execution type is 64-bit Both of those seem valid and are specific to the Gen8/9 low power parts. Created attachment 135365 [details] [review] Patch that probably fixes it Here's a completely untested patch that should fix it. It's a bit ugly, but I don't know what else we can do. I'll test it properly later. That works, modulo the off by one error. I think we can just use AND 0xff with a word type to do the unsigned extract in one instruction. I'll send that patch with a few other clean ups after some testing. This is probably not useful by now, but the bisection from CI was: ab9220edd69fcb7016e15d4d96186eac524b45a4 Author: Jason Ekstrand <jason@jlekstrand.net> nir,intel/compiler: Use a fixed subgroup size Send i965/fs: Fix extract_i8/u8 to a 64-bit destination (In reply to Matt Turner from comment #5) > Send i965/fs: Fix extract_i8/u8 to a 64-bit destination sent* commit 6ac2d16901927013393f873a34c717ece5014c1a Author: Matt Turner <mattst88@gmail.com> Date: Fri Nov 10 14:00:24 2017 -0800 i965/fs: Fix extract_i8/u8 to a 64-bit destination |
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