Bug 103628 - [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Summary: [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/i965 (show other bugs)
Version: git
Hardware: Other All
: medium normal
Assignee: Matt Turner
QA Contact: Intel 3D Bugs Mailing List
Depends on:
Blocks: mesa-17.3
  Show dependency treegraph
Reported: 2017-11-08 18:20 UTC by Mark Janes
Modified: 2017-11-14 18:57 UTC (History)
0 users

See Also:
i915 platform:
i915 features:

Patch that probably fixes it (1.45 KB, patch)
2017-11-10 01:02 UTC, Jason Ekstrand
Details | Splinter Review

Description Mark Janes 2017-11-08 18:20:15 UTC
int fs_generator::generate_code(const cfg_t*, int): Assertion
          `validated' failed.  [10:14]

first detected in the series ending in:
Author:     Jason Ekstrand <jason@jlekstrand.net>

intel/fs/nir: Return Q types from brw_reg_type_for_bit_size

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Comment 1 Matt Turner 2017-11-09 22:27:19 UTC
This fails because of:

mov(8)          g21<1>UQ        g19<8,1,0>UB                    { align1 1Q };
        ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit
        ERROR: Vstride must be Width * Hstride when the execution type is 64-bit

Both of those seem valid and are specific to the Gen8/9 low power parts.
Comment 2 Jason Ekstrand 2017-11-10 01:02:12 UTC
Created attachment 135365 [details] [review]
Patch that probably fixes it

Here's a completely untested patch that should fix it.  It's a bit ugly, but I don't know what else we can do.  I'll test it properly later.
Comment 3 Matt Turner 2017-11-10 22:55:53 UTC
That works, modulo the off by one error.

I think we can just use AND 0xff with a word type to do the unsigned extract in one instruction. I'll send that patch with a few other clean ups after some testing.
Comment 4 Mark Janes 2017-11-13 21:41:42 UTC
This is probably not useful by now, but the bisection from CI was:

Author:     Jason Ekstrand <jason@jlekstrand.net>
nir,intel/compiler: Use a fixed subgroup size
Comment 5 Matt Turner 2017-11-13 23:24:27 UTC
Send i965/fs: Fix extract_i8/u8 to a 64-bit destination
Comment 6 Matt Turner 2017-11-13 23:25:30 UTC
(In reply to Matt Turner from comment #5)
> Send i965/fs: Fix extract_i8/u8 to a 64-bit destination

Comment 7 Matt Turner 2017-11-14 18:57:33 UTC
commit 6ac2d16901927013393f873a34c717ece5014c1a
Author: Matt Turner <mattst88@gmail.com>
Date:   Fri Nov 10 14:00:24 2017 -0800

    i965/fs: Fix extract_i8/u8 to a 64-bit destination

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