| Summary: | AMD HAINAN (Radeon R5 M330) Clock frequency is 750MHz while it is supposed to be 1030MHz | ||||||||
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| Product: | DRI | Reporter: | Yassine Oudjana <y.oudjana> | ||||||
| Component: | DRM/Radeon | Assignee: | Default DRI bug account <dri-devel> | ||||||
| Status: | RESOLVED MOVED | QA Contact: | |||||||
| Severity: | normal | ||||||||
| Priority: | medium | CC: | kai.heng.feng | ||||||
| Version: | unspecified | ||||||||
| Hardware: | x86-64 (AMD64) | ||||||||
| OS: | Linux (All) | ||||||||
| Whiteboard: | |||||||||
| i915 platform: | i915 features: | ||||||||
| Attachments: |
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Created attachment 142420 [details] [review] root/drivers/gpu/drm/radeon/si_dpm.c with 1 line modified blob: 8fb60b3af015804d6d5ee3ef5d6f24ba74e2b1d9 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/radeon/si_dpm.c Line 2985 modified from: max_sclk = 75000; to: max_sclk = 103000; A number of boards had stability issues at the default clocks. Please attach your dmesg output. Created attachment 142424 [details]
dmesg output
Comment on attachment 142424 [details]
dmesg output
Note: I have not modified the kernel dmesg was ran under. Core clock is still 750MHz.
Why is the core clock for this GPU (HAINAN) and what seems to have codename OLAND hard-coded anyway? The other GPUs do not have their clocks hard-coded, which allows them to be modified without modifying and rebuilding the module. -- GitLab Migration Automatic Message -- This bug has been migrated to freedesktop.org's GitLab instance and has been closed from further activity. You can subscribe and participate further through the new bug through this link to our GitLab instance: https://gitlab.freedesktop.org/drm/amd/issues/846. |
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Kernel source: /drivers/gpu/drm/radeon/si_dpm.c line 2985: max_sclk = 75000; instead of max_sclk = 103000; Why is that? I changed it and rebuilt the kernel, and I can say that there are absolutely no issues when using the 1030MHz clock, **which is the default frequency this GPU is designed for**.