Bug 105664 - AMD HAINAN (Radeon R5 M330) Clock frequency is 750MHz while it is supposed to be 1030MHz
Summary: AMD HAINAN (Radeon R5 M330) Clock frequency is 750MHz while it is supposed to...
Status: RESOLVED MOVED
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Radeon (show other bugs)
Version: unspecified
Hardware: x86-64 (AMD64) Linux (All)
: medium normal
Assignee: Default DRI bug account
QA Contact:
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2018-03-21 14:53 UTC by Yassine Oudjana
Modified: 2019-11-19 09:32 UTC (History)
1 user (show)

See Also:
i915 platform:
i915 features:


Attachments
root/drivers/gpu/drm/radeon/si_dpm.c with 1 line modified (229.38 KB, patch)
2018-11-09 14:28 UTC, Yassine Oudjana
no flags Details | Splinter Review
dmesg output (108.93 KB, text/plain)
2018-11-10 14:16 UTC, Yassine Oudjana
no flags Details

Description Yassine Oudjana 2018-03-21 14:53:34 UTC
Kernel source: /drivers/gpu/drm/radeon/si_dpm.c line 2985:

                          max_sclk = 75000;

  instead of

                          max_sclk = 103000;

Why is that? I changed it and rebuilt the kernel, and I can say that
there are absolutely no issues when using the 1030MHz clock, **which is the default frequency this GPU is designed for**.
Comment 1 Yassine Oudjana 2018-11-09 14:28:45 UTC
Created attachment 142420 [details] [review]
root/drivers/gpu/drm/radeon/si_dpm.c with 1 line modified

blob: 8fb60b3af015804d6d5ee3ef5d6f24ba74e2b1d9
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/radeon/si_dpm.c

Line 2985 modified from:
			max_sclk = 75000;
to:
			max_sclk = 103000;
Comment 2 Alex Deucher 2018-11-09 15:46:26 UTC
A number of boards had stability issues at the default clocks. Please attach your dmesg output.
Comment 3 Yassine Oudjana 2018-11-10 14:16:12 UTC
Created attachment 142424 [details]
dmesg output
Comment 4 Yassine Oudjana 2018-11-10 14:17:34 UTC
Comment on attachment 142424 [details]
dmesg output

Note: I have not modified the kernel dmesg was ran under. Core clock is still 750MHz.
Comment 5 Yassine Oudjana 2019-10-27 16:24:23 UTC
Why is the core clock for this GPU (HAINAN) and what seems to have codename OLAND hard-coded anyway? The other GPUs do not have their clocks hard-coded, which allows them to be modified without modifying and rebuilding the module.
Comment 6 Martin Peres 2019-11-19 09:32:47 UTC
-- GitLab Migration Automatic Message --

This bug has been migrated to freedesktop.org's GitLab instance and has been closed from further activity.

You can subscribe and participate further through the new bug through this link to our GitLab instance: https://gitlab.freedesktop.org/drm/amd/issues/846.


Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.