Summary: | [CI][DRMTIP] igt@kms_psr2_su@page_flip - skip - PSR2 can not be enabled | ||
---|---|---|---|
Product: | DRI | Reporter: | Lakshmi <lakshminarayana.vudum> |
Component: | DRM/Intel | Assignee: | Jose Roberto de Souza <jose.souza> |
Status: | RESOLVED DUPLICATE | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
Severity: | normal | ||
Priority: | medium | CC: | intel-gfx-bugs, james.ausmus |
Version: | DRI git | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | ReadyForDev | ||
i915 platform: | ICL | i915 features: | display/PSR |
Description
Lakshmi
2019-03-19 17:03:41 UTC
The CI Bug Log issue associated to this bug has been updated. ### New filters associated * fi-icl-u2: igt@kms_psr2_su@page_flip - skip - PSR2 can not be enabled\n.*SKIP - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_244/fi-icl-u2/igt@kms_psr2_su@page_flip.html Jose - another one to double check if PSR2 should be supported with this Panel/HW config, or if this is expected results. If this is the current expected results, then this can be closed as NOTABUG A CI Bug Log filter associated to this bug has been updated: {- fi-icl-u2: igt@kms_psr2_su@page_flip - skip - PSR2 can not be enabled\n.*SKIP -} {+ ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP +} New failures caught by the filter: * https://intel-gfx-ci.01.org/tree/drm-tip/IGT_4891/shard-iclb2/igt@kms_psr2_su@frontbuffer.html (In reply to CI Bug Log from comment #1) > The CI Bug Log issue associated to this bug has been updated. > > ### New filters associated > > * fi-icl-u2: igt@kms_psr2_su@page_flip - skip - PSR2 can not be > enabled\n.*SKIP > - > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_244/fi-icl-u2/ > igt@kms_psr2_su@page_flip.html A fifo underrun happened, blocking the modeset that would enable PSR2 for more than 500msec causing a timeout on kms_psr2_su while still on the igt_fixture(). <7>[ 609.947314] [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A <7>[ 609.947375] [drm:intel_fbc_reset_underrun [i915]] Re-allowing FBC after fifo underrun <3>[ 609.947442] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun <7>[ 610.481955] [drm:skl_compute_wm [i915]] [PLANE:30:plane 1A] ddb ( 0 - 992) -> ( 0 - 0), size 992 -> 0 That is a real issue so I leave this bug open to investigate. (In reply to CI Bug Log from comment #3) > A CI Bug Log filter associated to this bug has been updated: > > {- fi-icl-u2: igt@kms_psr2_su@page_flip - skip - PSR2 can not be > enabled\n.*SKIP -} > {+ ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP +} > > New failures caught by the filter: > > * > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_4891/shard-iclb2/ > igt@kms_psr2_su@frontbuffer.html It skipped in shard-iclb2 because DSC is enabled: <7> [3087.533143] [drm:intel_psr_compute_config [i915]] PSR2 cannot be enabled since DSC is enabled This is expected to skip. (In reply to Jose Roberto de Souza from comment #5) > (In reply to CI Bug Log from comment #3) > > A CI Bug Log filter associated to this bug has been updated: > > > > {- fi-icl-u2: igt@kms_psr2_su@page_flip - skip - PSR2 can not be > > enabled\n.*SKIP -} > > {+ ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP +} > > > > New failures caught by the filter: > > > > * > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_4891/shard-iclb2/ > > igt@kms_psr2_su@frontbuffer.html > > It skipped in shard-iclb2 because DSC is enabled: > <7> [3087.533143] [drm:intel_psr_compute_config [i915]] PSR2 cannot be > enabled since DSC is enabled > > This is expected to skip. Sorry, CI Bug Log does not support the concept of negative matches (AKA, if a line is present in the log, DO NOT MATCH). Could the test itself skip on "DSC is enabled"? That would be easy to close as NOTABUG. A CI Bug Log filter associated to this bug has been updated: {- ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP -} {+ CML ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP +} New failures caught by the filter: * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_265/fi-cml-u/igt@kms_psr2_su@frontbuffer.html * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_265/fi-cml-u/igt@kms_psr2_su@page_flip.html A CI Bug Log filter associated to this bug has been updated: {- CML ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP -} {+ CML ICL TGL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP +} New failures caught by the filter: * https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr2_su@page_flip.html (In reply to CI Bug Log from comment #8) > A CI Bug Log filter associated to this bug has been updated: > > {- CML ICL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP -} > {+ CML ICL TGL: igt@kms_psr2_su@* - skip - PSR2 can not be enabled\n.*SKIP +} > > New failures caught by the filter: > > * > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/ > igt@kms_psr2_su@page_flip.html @Jose, This is on TGL which happens on resume run. *** This bug has been marked as a duplicate of bug 111842 *** The CI Bug Log issue associated to this bug has been archived. New failures matching the above filters will not be associated to this bug anymore. |
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